1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 #cooling-cells = <2>; 340 mediatek,cci = <&cci>; 341 }; 342 343 cpu1: cpu@1 { 344 device_type = "cpu"; 345 compatible = "arm,cortex-a53"; 346 reg = <0x001>; 347 enable-method = "psci"; 348 capacity-dmips-mhz = <741>; 349 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 350 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 351 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 352 clock-names = "cpu", "intermediate"; 353 operating-points-v2 = <&cluster0_opp>; 354 dynamic-power-coefficient = <84>; 355 #cooling-cells = <2>; 356 mediatek,cci = <&cci>; 357 }; 358 359 cpu2: cpu@2 { 360 device_type = "cpu"; 361 compatible = "arm,cortex-a53"; 362 reg = <0x002>; 363 enable-method = "psci"; 364 capacity-dmips-mhz = <741>; 365 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 366 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 367 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 368 clock-names = "cpu", "intermediate"; 369 operating-points-v2 = <&cluster0_opp>; 370 dynamic-power-coefficient = <84>; 371 #cooling-cells = <2>; 372 mediatek,cci = <&cci>; 373 }; 374 375 cpu3: cpu@3 { 376 device_type = "cpu"; 377 compatible = "arm,cortex-a53"; 378 reg = <0x003>; 379 enable-method = "psci"; 380 capacity-dmips-mhz = <741>; 381 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 382 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 383 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 384 clock-names = "cpu", "intermediate"; 385 operating-points-v2 = <&cluster0_opp>; 386 dynamic-power-coefficient = <84>; 387 #cooling-cells = <2>; 388 mediatek,cci = <&cci>; 389 }; 390 391 cpu4: cpu@100 { 392 device_type = "cpu"; 393 compatible = "arm,cortex-a73"; 394 reg = <0x100>; 395 enable-method = "psci"; 396 capacity-dmips-mhz = <1024>; 397 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 398 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 399 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 400 clock-names = "cpu", "intermediate"; 401 operating-points-v2 = <&cluster1_opp>; 402 dynamic-power-coefficient = <211>; 403 #cooling-cells = <2>; 404 mediatek,cci = <&cci>; 405 }; 406 407 cpu5: cpu@101 { 408 device_type = "cpu"; 409 compatible = "arm,cortex-a73"; 410 reg = <0x101>; 411 enable-method = "psci"; 412 capacity-dmips-mhz = <1024>; 413 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 414 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 415 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 416 clock-names = "cpu", "intermediate"; 417 operating-points-v2 = <&cluster1_opp>; 418 dynamic-power-coefficient = <211>; 419 #cooling-cells = <2>; 420 mediatek,cci = <&cci>; 421 }; 422 423 cpu6: cpu@102 { 424 device_type = "cpu"; 425 compatible = "arm,cortex-a73"; 426 reg = <0x102>; 427 enable-method = "psci"; 428 capacity-dmips-mhz = <1024>; 429 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 430 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 431 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 432 clock-names = "cpu", "intermediate"; 433 operating-points-v2 = <&cluster1_opp>; 434 dynamic-power-coefficient = <211>; 435 #cooling-cells = <2>; 436 mediatek,cci = <&cci>; 437 }; 438 439 cpu7: cpu@103 { 440 device_type = "cpu"; 441 compatible = "arm,cortex-a73"; 442 reg = <0x103>; 443 enable-method = "psci"; 444 capacity-dmips-mhz = <1024>; 445 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 446 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 447 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 448 clock-names = "cpu", "intermediate"; 449 operating-points-v2 = <&cluster1_opp>; 450 dynamic-power-coefficient = <211>; 451 #cooling-cells = <2>; 452 mediatek,cci = <&cci>; 453 }; 454 455 idle-states { 456 entry-method = "psci"; 457 458 CPU_SLEEP: cpu-sleep { 459 compatible = "arm,idle-state"; 460 local-timer-stop; 461 arm,psci-suspend-param = <0x00010001>; 462 entry-latency-us = <200>; 463 exit-latency-us = <200>; 464 min-residency-us = <800>; 465 }; 466 467 CLUSTER_SLEEP0: cluster-sleep-0 { 468 compatible = "arm,idle-state"; 469 local-timer-stop; 470 arm,psci-suspend-param = <0x01010001>; 471 entry-latency-us = <250>; 472 exit-latency-us = <400>; 473 min-residency-us = <1000>; 474 }; 475 CLUSTER_SLEEP1: cluster-sleep-1 { 476 compatible = "arm,idle-state"; 477 local-timer-stop; 478 arm,psci-suspend-param = <0x01010001>; 479 entry-latency-us = <250>; 480 exit-latency-us = <400>; 481 min-residency-us = <1300>; 482 }; 483 }; 484 }; 485 486 gpu_opp_table: opp-table-0 { 487 compatible = "operating-points-v2"; 488 opp-shared; 489 490 opp-300000000 { 491 opp-hz = /bits/ 64 <300000000>; 492 opp-microvolt = <625000>, <850000>; 493 }; 494 495 opp-320000000 { 496 opp-hz = /bits/ 64 <320000000>; 497 opp-microvolt = <631250>, <850000>; 498 }; 499 500 opp-340000000 { 501 opp-hz = /bits/ 64 <340000000>; 502 opp-microvolt = <637500>, <850000>; 503 }; 504 505 opp-360000000 { 506 opp-hz = /bits/ 64 <360000000>; 507 opp-microvolt = <643750>, <850000>; 508 }; 509 510 opp-380000000 { 511 opp-hz = /bits/ 64 <380000000>; 512 opp-microvolt = <650000>, <850000>; 513 }; 514 515 opp-400000000 { 516 opp-hz = /bits/ 64 <400000000>; 517 opp-microvolt = <656250>, <850000>; 518 }; 519 520 opp-420000000 { 521 opp-hz = /bits/ 64 <420000000>; 522 opp-microvolt = <662500>, <850000>; 523 }; 524 525 opp-460000000 { 526 opp-hz = /bits/ 64 <460000000>; 527 opp-microvolt = <675000>, <850000>; 528 }; 529 530 opp-500000000 { 531 opp-hz = /bits/ 64 <500000000>; 532 opp-microvolt = <687500>, <850000>; 533 }; 534 535 opp-540000000 { 536 opp-hz = /bits/ 64 <540000000>; 537 opp-microvolt = <700000>, <850000>; 538 }; 539 540 opp-580000000 { 541 opp-hz = /bits/ 64 <580000000>; 542 opp-microvolt = <712500>, <850000>; 543 }; 544 545 opp-620000000 { 546 opp-hz = /bits/ 64 <620000000>; 547 opp-microvolt = <725000>, <850000>; 548 }; 549 550 opp-653000000 { 551 opp-hz = /bits/ 64 <653000000>; 552 opp-microvolt = <743750>, <850000>; 553 }; 554 555 opp-698000000 { 556 opp-hz = /bits/ 64 <698000000>; 557 opp-microvolt = <768750>, <868750>; 558 }; 559 560 opp-743000000 { 561 opp-hz = /bits/ 64 <743000000>; 562 opp-microvolt = <793750>, <893750>; 563 }; 564 565 opp-800000000 { 566 opp-hz = /bits/ 64 <800000000>; 567 opp-microvolt = <825000>, <925000>; 568 }; 569 }; 570 571 pmu-a53 { 572 compatible = "arm,cortex-a53-pmu"; 573 interrupt-parent = <&gic>; 574 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 575 }; 576 577 pmu-a73 { 578 compatible = "arm,cortex-a73-pmu"; 579 interrupt-parent = <&gic>; 580 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 581 }; 582 583 psci { 584 compatible = "arm,psci-1.0"; 585 method = "smc"; 586 }; 587 588 clk26m: oscillator { 589 compatible = "fixed-clock"; 590 #clock-cells = <0>; 591 clock-frequency = <26000000>; 592 clock-output-names = "clk26m"; 593 }; 594 595 timer { 596 compatible = "arm,armv8-timer"; 597 interrupt-parent = <&gic>; 598 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 599 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 600 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 601 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 602 }; 603 604 soc { 605 #address-cells = <2>; 606 #size-cells = <2>; 607 compatible = "simple-bus"; 608 ranges; 609 610 soc_data: efuse@8000000 { 611 compatible = "mediatek,mt8183-efuse", 612 "mediatek,efuse"; 613 reg = <0 0x08000000 0 0x0010>; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 status = "disabled"; 617 }; 618 619 gic: interrupt-controller@c000000 { 620 compatible = "arm,gic-v3"; 621 #interrupt-cells = <4>; 622 interrupt-parent = <&gic>; 623 interrupt-controller; 624 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 625 <0 0x0c100000 0 0x200000>, /* GICR */ 626 <0 0x0c400000 0 0x2000>, /* GICC */ 627 <0 0x0c410000 0 0x1000>, /* GICH */ 628 <0 0x0c420000 0 0x2000>; /* GICV */ 629 630 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 631 ppi-partitions { 632 ppi_cluster0: interrupt-partition-0 { 633 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 634 }; 635 ppi_cluster1: interrupt-partition-1 { 636 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 637 }; 638 }; 639 }; 640 641 mcucfg: syscon@c530000 { 642 compatible = "mediatek,mt8183-mcucfg", "syscon"; 643 reg = <0 0x0c530000 0 0x1000>; 644 #clock-cells = <1>; 645 }; 646 647 sysirq: interrupt-controller@c530a80 { 648 compatible = "mediatek,mt8183-sysirq", 649 "mediatek,mt6577-sysirq"; 650 interrupt-controller; 651 #interrupt-cells = <3>; 652 interrupt-parent = <&gic>; 653 reg = <0 0x0c530a80 0 0x50>; 654 }; 655 656 cpu_debug0: cpu-debug@d410000 { 657 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 658 reg = <0x0 0xd410000 0x0 0x1000>; 659 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 660 clock-names = "apb_pclk"; 661 cpu = <&cpu0>; 662 }; 663 664 cpu_debug1: cpu-debug@d510000 { 665 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 666 reg = <0x0 0xd510000 0x0 0x1000>; 667 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 668 clock-names = "apb_pclk"; 669 cpu = <&cpu1>; 670 }; 671 672 cpu_debug2: cpu-debug@d610000 { 673 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 674 reg = <0x0 0xd610000 0x0 0x1000>; 675 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 676 clock-names = "apb_pclk"; 677 cpu = <&cpu2>; 678 }; 679 680 cpu_debug3: cpu-debug@d710000 { 681 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 682 reg = <0x0 0xd710000 0x0 0x1000>; 683 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 684 clock-names = "apb_pclk"; 685 cpu = <&cpu3>; 686 }; 687 688 cpu_debug4: cpu-debug@d810000 { 689 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 690 reg = <0x0 0xd810000 0x0 0x1000>; 691 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 692 clock-names = "apb_pclk"; 693 cpu = <&cpu4>; 694 }; 695 696 cpu_debug5: cpu-debug@d910000 { 697 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 698 reg = <0x0 0xd910000 0x0 0x1000>; 699 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 700 clock-names = "apb_pclk"; 701 cpu = <&cpu5>; 702 }; 703 704 cpu_debug6: cpu-debug@da10000 { 705 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 706 reg = <0x0 0xda10000 0x0 0x1000>; 707 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 708 clock-names = "apb_pclk"; 709 cpu = <&cpu6>; 710 }; 711 712 cpu_debug7: cpu-debug@db10000 { 713 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 714 reg = <0x0 0xdb10000 0x0 0x1000>; 715 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 716 clock-names = "apb_pclk"; 717 cpu = <&cpu7>; 718 }; 719 720 topckgen: syscon@10000000 { 721 compatible = "mediatek,mt8183-topckgen", "syscon"; 722 reg = <0 0x10000000 0 0x1000>; 723 #clock-cells = <1>; 724 }; 725 726 infracfg: syscon@10001000 { 727 compatible = "mediatek,mt8183-infracfg", "syscon"; 728 reg = <0 0x10001000 0 0x1000>; 729 #clock-cells = <1>; 730 #reset-cells = <1>; 731 }; 732 733 pericfg: syscon@10003000 { 734 compatible = "mediatek,mt8183-pericfg", "syscon"; 735 reg = <0 0x10003000 0 0x1000>; 736 #clock-cells = <1>; 737 }; 738 739 pio: pinctrl@10005000 { 740 compatible = "mediatek,mt8183-pinctrl"; 741 reg = <0 0x10005000 0 0x1000>, 742 <0 0x11f20000 0 0x1000>, 743 <0 0x11e80000 0 0x1000>, 744 <0 0x11e70000 0 0x1000>, 745 <0 0x11e90000 0 0x1000>, 746 <0 0x11d30000 0 0x1000>, 747 <0 0x11d20000 0 0x1000>, 748 <0 0x11c50000 0 0x1000>, 749 <0 0x11f30000 0 0x1000>, 750 <0 0x1000b000 0 0x1000>; 751 reg-names = "iocfg0", "iocfg1", "iocfg2", 752 "iocfg3", "iocfg4", "iocfg5", 753 "iocfg6", "iocfg7", "iocfg8", 754 "eint"; 755 gpio-controller; 756 #gpio-cells = <2>; 757 gpio-ranges = <&pio 0 0 192>; 758 interrupt-controller; 759 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 760 #interrupt-cells = <2>; 761 }; 762 763 scpsys: syscon@10006000 { 764 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; 765 reg = <0 0x10006000 0 0x1000>; 766 767 /* System Power Manager */ 768 spm: power-controller { 769 compatible = "mediatek,mt8183-power-controller"; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 #power-domain-cells = <1>; 773 774 /* power domain of the SoC */ 775 power-domain@MT8183_POWER_DOMAIN_AUDIO { 776 reg = <MT8183_POWER_DOMAIN_AUDIO>; 777 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 778 <&infracfg CLK_INFRA_AUDIO>, 779 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 780 clock-names = "audio", "audio1", "audio2"; 781 #power-domain-cells = <0>; 782 }; 783 784 power-domain@MT8183_POWER_DOMAIN_CONN { 785 reg = <MT8183_POWER_DOMAIN_CONN>; 786 mediatek,infracfg = <&infracfg>; 787 #power-domain-cells = <0>; 788 }; 789 790 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 791 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 792 clocks = <&topckgen CLK_TOP_MUX_MFG>; 793 clock-names = "mfg"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 #power-domain-cells = <1>; 797 798 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 799 reg = <MT8183_POWER_DOMAIN_MFG>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 #power-domain-cells = <1>; 803 804 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 805 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 806 #power-domain-cells = <0>; 807 }; 808 809 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 810 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 811 #power-domain-cells = <0>; 812 }; 813 814 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 815 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 816 mediatek,infracfg = <&infracfg>; 817 #power-domain-cells = <0>; 818 }; 819 }; 820 }; 821 822 power-domain@MT8183_POWER_DOMAIN_DISP { 823 reg = <MT8183_POWER_DOMAIN_DISP>; 824 clocks = <&topckgen CLK_TOP_MUX_MM>, 825 <&mmsys CLK_MM_SMI_COMMON>, 826 <&mmsys CLK_MM_SMI_LARB0>, 827 <&mmsys CLK_MM_SMI_LARB1>, 828 <&mmsys CLK_MM_GALS_COMM0>, 829 <&mmsys CLK_MM_GALS_COMM1>, 830 <&mmsys CLK_MM_GALS_CCU2MM>, 831 <&mmsys CLK_MM_GALS_IPU12MM>, 832 <&mmsys CLK_MM_GALS_IMG2MM>, 833 <&mmsys CLK_MM_GALS_CAM2MM>, 834 <&mmsys CLK_MM_GALS_IPU2MM>; 835 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 836 "mm-4", "mm-5", "mm-6", "mm-7", 837 "mm-8", "mm-9"; 838 mediatek,infracfg = <&infracfg>; 839 mediatek,smi = <&smi_common>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 #power-domain-cells = <1>; 843 844 power-domain@MT8183_POWER_DOMAIN_CAM { 845 reg = <MT8183_POWER_DOMAIN_CAM>; 846 clocks = <&topckgen CLK_TOP_MUX_CAM>, 847 <&camsys CLK_CAM_LARB6>, 848 <&camsys CLK_CAM_LARB3>, 849 <&camsys CLK_CAM_SENINF>, 850 <&camsys CLK_CAM_CAMSV0>, 851 <&camsys CLK_CAM_CAMSV1>, 852 <&camsys CLK_CAM_CAMSV2>, 853 <&camsys CLK_CAM_CCU>; 854 clock-names = "cam", "cam-0", "cam-1", 855 "cam-2", "cam-3", "cam-4", 856 "cam-5", "cam-6"; 857 mediatek,infracfg = <&infracfg>; 858 mediatek,smi = <&smi_common>; 859 #power-domain-cells = <0>; 860 }; 861 862 power-domain@MT8183_POWER_DOMAIN_ISP { 863 reg = <MT8183_POWER_DOMAIN_ISP>; 864 clocks = <&topckgen CLK_TOP_MUX_IMG>, 865 <&imgsys CLK_IMG_LARB5>, 866 <&imgsys CLK_IMG_LARB2>; 867 clock-names = "isp", "isp-0", "isp-1"; 868 mediatek,infracfg = <&infracfg>; 869 mediatek,smi = <&smi_common>; 870 #power-domain-cells = <0>; 871 }; 872 873 power-domain@MT8183_POWER_DOMAIN_VDEC { 874 reg = <MT8183_POWER_DOMAIN_VDEC>; 875 mediatek,smi = <&smi_common>; 876 #power-domain-cells = <0>; 877 }; 878 879 power-domain@MT8183_POWER_DOMAIN_VENC { 880 reg = <MT8183_POWER_DOMAIN_VENC>; 881 mediatek,smi = <&smi_common>; 882 #power-domain-cells = <0>; 883 }; 884 885 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 886 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 887 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 888 <&topckgen CLK_TOP_MUX_DSP>, 889 <&ipu_conn CLK_IPU_CONN_IPU>, 890 <&ipu_conn CLK_IPU_CONN_AHB>, 891 <&ipu_conn CLK_IPU_CONN_AXI>, 892 <&ipu_conn CLK_IPU_CONN_ISP>, 893 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 894 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 895 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 896 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 897 mediatek,infracfg = <&infracfg>; 898 mediatek,smi = <&smi_common>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 #power-domain-cells = <1>; 902 903 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 904 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 905 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 906 clock-names = "vpu2"; 907 mediatek,infracfg = <&infracfg>; 908 #power-domain-cells = <0>; 909 }; 910 911 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 912 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 913 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 914 clock-names = "vpu3"; 915 mediatek,infracfg = <&infracfg>; 916 #power-domain-cells = <0>; 917 }; 918 }; 919 }; 920 }; 921 }; 922 923 watchdog: watchdog@10007000 { 924 compatible = "mediatek,mt8183-wdt"; 925 reg = <0 0x10007000 0 0x100>; 926 #reset-cells = <1>; 927 }; 928 929 apmixedsys: syscon@1000c000 { 930 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 931 reg = <0 0x1000c000 0 0x1000>; 932 #clock-cells = <1>; 933 }; 934 935 pwrap: pwrap@1000d000 { 936 compatible = "mediatek,mt8183-pwrap"; 937 reg = <0 0x1000d000 0 0x1000>; 938 reg-names = "pwrap"; 939 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 941 <&infracfg CLK_INFRA_PMIC_AP>; 942 clock-names = "spi", "wrap"; 943 }; 944 945 keyboard: keyboard@10010000 { 946 compatible = "mediatek,mt6779-keypad"; 947 reg = <0 0x10010000 0 0x1000>; 948 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; 949 clocks = <&clk26m>; 950 clock-names = "kpd"; 951 status = "disabled"; 952 }; 953 954 scp: scp@10500000 { 955 compatible = "mediatek,mt8183-scp"; 956 reg = <0 0x10500000 0 0x80000>, 957 <0 0x105c0000 0 0x19080>; 958 reg-names = "sram", "cfg"; 959 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&infracfg CLK_INFRA_SCPSYS>; 961 clock-names = "main"; 962 memory-region = <&scp_mem_reserved>; 963 status = "disabled"; 964 }; 965 966 systimer: timer@10017000 { 967 compatible = "mediatek,mt8183-timer", 968 "mediatek,mt6765-timer"; 969 reg = <0 0x10017000 0 0x1000>; 970 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&topckgen CLK_TOP_CLK13M>; 972 clock-names = "clk13m"; 973 }; 974 975 iommu: iommu@10205000 { 976 compatible = "mediatek,mt8183-m4u"; 977 reg = <0 0x10205000 0 0x1000>; 978 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 979 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 980 <&larb4>, <&larb5>, <&larb6>; 981 #iommu-cells = <1>; 982 }; 983 984 gce: mailbox@10238000 { 985 compatible = "mediatek,mt8183-gce"; 986 reg = <0 0x10238000 0 0x4000>; 987 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 988 #mbox-cells = <2>; 989 clocks = <&infracfg CLK_INFRA_GCE>; 990 clock-names = "gce"; 991 }; 992 993 auxadc: auxadc@11001000 { 994 compatible = "mediatek,mt8183-auxadc", 995 "mediatek,mt8173-auxadc"; 996 reg = <0 0x11001000 0 0x1000>; 997 clocks = <&infracfg CLK_INFRA_AUXADC>; 998 clock-names = "main"; 999 #io-channel-cells = <1>; 1000 status = "disabled"; 1001 }; 1002 1003 uart0: serial@11002000 { 1004 compatible = "mediatek,mt8183-uart", 1005 "mediatek,mt6577-uart"; 1006 reg = <0 0x11002000 0 0x1000>; 1007 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 1008 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 1009 clock-names = "baud", "bus"; 1010 status = "disabled"; 1011 }; 1012 1013 uart1: serial@11003000 { 1014 compatible = "mediatek,mt8183-uart", 1015 "mediatek,mt6577-uart"; 1016 reg = <0 0x11003000 0 0x1000>; 1017 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1018 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1019 clock-names = "baud", "bus"; 1020 status = "disabled"; 1021 }; 1022 1023 uart2: serial@11004000 { 1024 compatible = "mediatek,mt8183-uart", 1025 "mediatek,mt6577-uart"; 1026 reg = <0 0x11004000 0 0x1000>; 1027 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1028 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1029 clock-names = "baud", "bus"; 1030 status = "disabled"; 1031 }; 1032 1033 i2c6: i2c@11005000 { 1034 compatible = "mediatek,mt8183-i2c"; 1035 reg = <0 0x11005000 0 0x1000>, 1036 <0 0x11000600 0 0x80>; 1037 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1038 clocks = <&infracfg CLK_INFRA_I2C6>, 1039 <&infracfg CLK_INFRA_AP_DMA>; 1040 clock-names = "main", "dma"; 1041 clock-div = <1>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c0: i2c@11007000 { 1048 compatible = "mediatek,mt8183-i2c"; 1049 reg = <0 0x11007000 0 0x1000>, 1050 <0 0x11000080 0 0x80>; 1051 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1052 clocks = <&infracfg CLK_INFRA_I2C0>, 1053 <&infracfg CLK_INFRA_AP_DMA>; 1054 clock-names = "main", "dma"; 1055 clock-div = <1>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 i2c4: i2c@11008000 { 1062 compatible = "mediatek,mt8183-i2c"; 1063 reg = <0 0x11008000 0 0x1000>, 1064 <0 0x11000100 0 0x80>; 1065 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1066 clocks = <&infracfg CLK_INFRA_I2C1>, 1067 <&infracfg CLK_INFRA_AP_DMA>, 1068 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1069 clock-names = "main", "dma","arb"; 1070 clock-div = <1>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 i2c2: i2c@11009000 { 1077 compatible = "mediatek,mt8183-i2c"; 1078 reg = <0 0x11009000 0 0x1000>, 1079 <0 0x11000280 0 0x80>; 1080 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1081 clocks = <&infracfg CLK_INFRA_I2C2>, 1082 <&infracfg CLK_INFRA_AP_DMA>, 1083 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1084 clock-names = "main", "dma", "arb"; 1085 clock-div = <1>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 spi0: spi@1100a000 { 1092 compatible = "mediatek,mt8183-spi"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 reg = <0 0x1100a000 0 0x1000>; 1096 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1097 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1098 <&topckgen CLK_TOP_MUX_SPI>, 1099 <&infracfg CLK_INFRA_SPI0>; 1100 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1101 status = "disabled"; 1102 }; 1103 1104 svs: svs@1100b000 { 1105 compatible = "mediatek,mt8183-svs"; 1106 reg = <0 0x1100b000 0 0x1000>; 1107 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 1108 clocks = <&infracfg CLK_INFRA_THERM>; 1109 clock-names = "main"; 1110 nvmem-cells = <&svs_calibration>, 1111 <&thermal_calibration>; 1112 nvmem-cell-names = "svs-calibration-data", 1113 "t-calibration-data"; 1114 }; 1115 1116 thermal: thermal@1100b000 { 1117 #thermal-sensor-cells = <1>; 1118 compatible = "mediatek,mt8183-thermal"; 1119 reg = <0 0x1100b000 0 0x1000>; 1120 clocks = <&infracfg CLK_INFRA_THERM>, 1121 <&infracfg CLK_INFRA_AUXADC>; 1122 clock-names = "therm", "auxadc"; 1123 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1124 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1125 mediatek,auxadc = <&auxadc>; 1126 mediatek,apmixedsys = <&apmixedsys>; 1127 nvmem-cells = <&thermal_calibration>; 1128 nvmem-cell-names = "calibration-data"; 1129 }; 1130 1131 thermal_zones: thermal-zones { 1132 cpu_thermal: cpu-thermal { 1133 polling-delay-passive = <100>; 1134 polling-delay = <500>; 1135 thermal-sensors = <&thermal 0>; 1136 sustainable-power = <5000>; 1137 1138 trips { 1139 threshold: trip-point0 { 1140 temperature = <68000>; 1141 hysteresis = <2000>; 1142 type = "passive"; 1143 }; 1144 1145 target: trip-point1 { 1146 temperature = <80000>; 1147 hysteresis = <2000>; 1148 type = "passive"; 1149 }; 1150 1151 cpu_crit: cpu-crit { 1152 temperature = <115000>; 1153 hysteresis = <2000>; 1154 type = "critical"; 1155 }; 1156 }; 1157 1158 cooling-maps { 1159 map0 { 1160 trip = <&target>; 1161 cooling-device = <&cpu0 1162 THERMAL_NO_LIMIT 1163 THERMAL_NO_LIMIT>, 1164 <&cpu1 1165 THERMAL_NO_LIMIT 1166 THERMAL_NO_LIMIT>, 1167 <&cpu2 1168 THERMAL_NO_LIMIT 1169 THERMAL_NO_LIMIT>, 1170 <&cpu3 1171 THERMAL_NO_LIMIT 1172 THERMAL_NO_LIMIT>; 1173 contribution = <3072>; 1174 }; 1175 map1 { 1176 trip = <&target>; 1177 cooling-device = <&cpu4 1178 THERMAL_NO_LIMIT 1179 THERMAL_NO_LIMIT>, 1180 <&cpu5 1181 THERMAL_NO_LIMIT 1182 THERMAL_NO_LIMIT>, 1183 <&cpu6 1184 THERMAL_NO_LIMIT 1185 THERMAL_NO_LIMIT>, 1186 <&cpu7 1187 THERMAL_NO_LIMIT 1188 THERMAL_NO_LIMIT>; 1189 contribution = <1024>; 1190 }; 1191 }; 1192 }; 1193 1194 /* The tzts1 ~ tzts6 don't need to polling */ 1195 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 1196 1197 tzts1: tzts1 { 1198 polling-delay-passive = <0>; 1199 polling-delay = <0>; 1200 thermal-sensors = <&thermal 1>; 1201 sustainable-power = <5000>; 1202 trips {}; 1203 cooling-maps {}; 1204 }; 1205 1206 tzts2: tzts2 { 1207 polling-delay-passive = <0>; 1208 polling-delay = <0>; 1209 thermal-sensors = <&thermal 2>; 1210 sustainable-power = <5000>; 1211 trips {}; 1212 cooling-maps {}; 1213 }; 1214 1215 tzts3: tzts3 { 1216 polling-delay-passive = <0>; 1217 polling-delay = <0>; 1218 thermal-sensors = <&thermal 3>; 1219 sustainable-power = <5000>; 1220 trips {}; 1221 cooling-maps {}; 1222 }; 1223 1224 tzts4: tzts4 { 1225 polling-delay-passive = <0>; 1226 polling-delay = <0>; 1227 thermal-sensors = <&thermal 4>; 1228 sustainable-power = <5000>; 1229 trips {}; 1230 cooling-maps {}; 1231 }; 1232 1233 tzts5: tzts5 { 1234 polling-delay-passive = <0>; 1235 polling-delay = <0>; 1236 thermal-sensors = <&thermal 5>; 1237 sustainable-power = <5000>; 1238 trips {}; 1239 cooling-maps {}; 1240 }; 1241 1242 tztsABB: tztsABB { 1243 polling-delay-passive = <0>; 1244 polling-delay = <0>; 1245 thermal-sensors = <&thermal 6>; 1246 sustainable-power = <5000>; 1247 trips {}; 1248 cooling-maps {}; 1249 }; 1250 }; 1251 1252 pwm0: pwm@1100e000 { 1253 compatible = "mediatek,mt8183-disp-pwm"; 1254 reg = <0 0x1100e000 0 0x1000>; 1255 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1256 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1257 #pwm-cells = <2>; 1258 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1259 <&infracfg CLK_INFRA_DISP_PWM>; 1260 clock-names = "main", "mm"; 1261 }; 1262 1263 pwm1: pwm@11006000 { 1264 compatible = "mediatek,mt8183-pwm"; 1265 reg = <0 0x11006000 0 0x1000>; 1266 #pwm-cells = <2>; 1267 clocks = <&infracfg CLK_INFRA_PWM>, 1268 <&infracfg CLK_INFRA_PWM_HCLK>, 1269 <&infracfg CLK_INFRA_PWM1>, 1270 <&infracfg CLK_INFRA_PWM2>, 1271 <&infracfg CLK_INFRA_PWM3>, 1272 <&infracfg CLK_INFRA_PWM4>; 1273 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1274 "pwm4"; 1275 }; 1276 1277 i2c3: i2c@1100f000 { 1278 compatible = "mediatek,mt8183-i2c"; 1279 reg = <0 0x1100f000 0 0x1000>, 1280 <0 0x11000400 0 0x80>; 1281 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1282 clocks = <&infracfg CLK_INFRA_I2C3>, 1283 <&infracfg CLK_INFRA_AP_DMA>; 1284 clock-names = "main", "dma"; 1285 clock-div = <1>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 spi1: spi@11010000 { 1292 compatible = "mediatek,mt8183-spi"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 reg = <0 0x11010000 0 0x1000>; 1296 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1297 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1298 <&topckgen CLK_TOP_MUX_SPI>, 1299 <&infracfg CLK_INFRA_SPI1>; 1300 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1301 status = "disabled"; 1302 }; 1303 1304 i2c1: i2c@11011000 { 1305 compatible = "mediatek,mt8183-i2c"; 1306 reg = <0 0x11011000 0 0x1000>, 1307 <0 0x11000480 0 0x80>; 1308 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1309 clocks = <&infracfg CLK_INFRA_I2C4>, 1310 <&infracfg CLK_INFRA_AP_DMA>; 1311 clock-names = "main", "dma"; 1312 clock-div = <1>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 spi2: spi@11012000 { 1319 compatible = "mediatek,mt8183-spi"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 reg = <0 0x11012000 0 0x1000>; 1323 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1324 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1325 <&topckgen CLK_TOP_MUX_SPI>, 1326 <&infracfg CLK_INFRA_SPI2>; 1327 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1328 status = "disabled"; 1329 }; 1330 1331 spi3: spi@11013000 { 1332 compatible = "mediatek,mt8183-spi"; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 reg = <0 0x11013000 0 0x1000>; 1336 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1337 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1338 <&topckgen CLK_TOP_MUX_SPI>, 1339 <&infracfg CLK_INFRA_SPI3>; 1340 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1341 status = "disabled"; 1342 }; 1343 1344 i2c9: i2c@11014000 { 1345 compatible = "mediatek,mt8183-i2c"; 1346 reg = <0 0x11014000 0 0x1000>, 1347 <0 0x11000180 0 0x80>; 1348 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1349 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1350 <&infracfg CLK_INFRA_AP_DMA>, 1351 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1352 clock-names = "main", "dma", "arb"; 1353 clock-div = <1>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 i2c10: i2c@11015000 { 1360 compatible = "mediatek,mt8183-i2c"; 1361 reg = <0 0x11015000 0 0x1000>, 1362 <0 0x11000300 0 0x80>; 1363 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1364 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1365 <&infracfg CLK_INFRA_AP_DMA>, 1366 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1367 clock-names = "main", "dma", "arb"; 1368 clock-div = <1>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 i2c5: i2c@11016000 { 1375 compatible = "mediatek,mt8183-i2c"; 1376 reg = <0 0x11016000 0 0x1000>, 1377 <0 0x11000500 0 0x80>; 1378 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1379 clocks = <&infracfg CLK_INFRA_I2C5>, 1380 <&infracfg CLK_INFRA_AP_DMA>, 1381 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1382 clock-names = "main", "dma", "arb"; 1383 clock-div = <1>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 i2c11: i2c@11017000 { 1390 compatible = "mediatek,mt8183-i2c"; 1391 reg = <0 0x11017000 0 0x1000>, 1392 <0 0x11000580 0 0x80>; 1393 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1394 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1395 <&infracfg CLK_INFRA_AP_DMA>, 1396 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1397 clock-names = "main", "dma", "arb"; 1398 clock-div = <1>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 spi4: spi@11018000 { 1405 compatible = "mediatek,mt8183-spi"; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 reg = <0 0x11018000 0 0x1000>; 1409 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1410 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1411 <&topckgen CLK_TOP_MUX_SPI>, 1412 <&infracfg CLK_INFRA_SPI4>; 1413 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1414 status = "disabled"; 1415 }; 1416 1417 spi5: spi@11019000 { 1418 compatible = "mediatek,mt8183-spi"; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 reg = <0 0x11019000 0 0x1000>; 1422 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1423 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1424 <&topckgen CLK_TOP_MUX_SPI>, 1425 <&infracfg CLK_INFRA_SPI5>; 1426 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1427 status = "disabled"; 1428 }; 1429 1430 i2c7: i2c@1101a000 { 1431 compatible = "mediatek,mt8183-i2c"; 1432 reg = <0 0x1101a000 0 0x1000>, 1433 <0 0x11000680 0 0x80>; 1434 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1435 clocks = <&infracfg CLK_INFRA_I2C7>, 1436 <&infracfg CLK_INFRA_AP_DMA>; 1437 clock-names = "main", "dma"; 1438 clock-div = <1>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 i2c8: i2c@1101b000 { 1445 compatible = "mediatek,mt8183-i2c"; 1446 reg = <0 0x1101b000 0 0x1000>, 1447 <0 0x11000700 0 0x80>; 1448 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1449 clocks = <&infracfg CLK_INFRA_I2C8>, 1450 <&infracfg CLK_INFRA_AP_DMA>; 1451 clock-names = "main", "dma"; 1452 clock-div = <1>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 ssusb: usb@11201000 { 1459 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1460 reg = <0 0x11201000 0 0x2e00>, 1461 <0 0x11203e00 0 0x0100>; 1462 reg-names = "mac", "ippc"; 1463 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1464 phys = <&u2port0 PHY_TYPE_USB2>, 1465 <&u3port0 PHY_TYPE_USB3>; 1466 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1467 <&infracfg CLK_INFRA_USB>; 1468 clock-names = "sys_ck", "ref_ck"; 1469 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 ranges; 1473 status = "disabled"; 1474 1475 usb_host: usb@11200000 { 1476 compatible = "mediatek,mt8183-xhci", 1477 "mediatek,mtk-xhci"; 1478 reg = <0 0x11200000 0 0x1000>; 1479 reg-names = "mac"; 1480 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1481 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1482 <&infracfg CLK_INFRA_USB>; 1483 clock-names = "sys_ck", "ref_ck"; 1484 status = "disabled"; 1485 }; 1486 }; 1487 1488 audiosys: audio-controller@11220000 { 1489 compatible = "mediatek,mt8183-audiosys", "syscon"; 1490 reg = <0 0x11220000 0 0x1000>; 1491 #clock-cells = <1>; 1492 afe: mt8183-afe-pcm { 1493 compatible = "mediatek,mt8183-audio"; 1494 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1495 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1496 reset-names = "audiosys"; 1497 power-domains = 1498 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1499 clocks = <&audiosys CLK_AUDIO_AFE>, 1500 <&audiosys CLK_AUDIO_DAC>, 1501 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1502 <&audiosys CLK_AUDIO_ADC>, 1503 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1504 <&audiosys CLK_AUDIO_22M>, 1505 <&audiosys CLK_AUDIO_24M>, 1506 <&audiosys CLK_AUDIO_APLL_TUNER>, 1507 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1508 <&audiosys CLK_AUDIO_I2S1>, 1509 <&audiosys CLK_AUDIO_I2S2>, 1510 <&audiosys CLK_AUDIO_I2S3>, 1511 <&audiosys CLK_AUDIO_I2S4>, 1512 <&audiosys CLK_AUDIO_TDM>, 1513 <&audiosys CLK_AUDIO_TML>, 1514 <&infracfg CLK_INFRA_AUDIO>, 1515 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1516 <&topckgen CLK_TOP_MUX_AUDIO>, 1517 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1518 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1519 <&topckgen CLK_TOP_MUX_AUD_1>, 1520 <&topckgen CLK_TOP_APLL1_CK>, 1521 <&topckgen CLK_TOP_MUX_AUD_2>, 1522 <&topckgen CLK_TOP_APLL2_CK>, 1523 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1524 <&topckgen CLK_TOP_APLL1_D8>, 1525 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1526 <&topckgen CLK_TOP_APLL2_D8>, 1527 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1528 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1529 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1530 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1531 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1532 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1533 <&topckgen CLK_TOP_APLL12_DIV0>, 1534 <&topckgen CLK_TOP_APLL12_DIV1>, 1535 <&topckgen CLK_TOP_APLL12_DIV2>, 1536 <&topckgen CLK_TOP_APLL12_DIV3>, 1537 <&topckgen CLK_TOP_APLL12_DIV4>, 1538 <&topckgen CLK_TOP_APLL12_DIVB>, 1539 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1540 <&clk26m>; 1541 clock-names = "aud_afe_clk", 1542 "aud_dac_clk", 1543 "aud_dac_predis_clk", 1544 "aud_adc_clk", 1545 "aud_adc_adda6_clk", 1546 "aud_apll22m_clk", 1547 "aud_apll24m_clk", 1548 "aud_apll1_tuner_clk", 1549 "aud_apll2_tuner_clk", 1550 "aud_i2s1_bclk_sw", 1551 "aud_i2s2_bclk_sw", 1552 "aud_i2s3_bclk_sw", 1553 "aud_i2s4_bclk_sw", 1554 "aud_tdm_clk", 1555 "aud_tml_clk", 1556 "aud_infra_clk", 1557 "mtkaif_26m_clk", 1558 "top_mux_audio", 1559 "top_mux_aud_intbus", 1560 "top_syspll_d2_d4", 1561 "top_mux_aud_1", 1562 "top_apll1_ck", 1563 "top_mux_aud_2", 1564 "top_apll2_ck", 1565 "top_mux_aud_eng1", 1566 "top_apll1_d8", 1567 "top_mux_aud_eng2", 1568 "top_apll2_d8", 1569 "top_i2s0_m_sel", 1570 "top_i2s1_m_sel", 1571 "top_i2s2_m_sel", 1572 "top_i2s3_m_sel", 1573 "top_i2s4_m_sel", 1574 "top_i2s5_m_sel", 1575 "top_apll12_div0", 1576 "top_apll12_div1", 1577 "top_apll12_div2", 1578 "top_apll12_div3", 1579 "top_apll12_div4", 1580 "top_apll12_divb", 1581 /*"top_apll12_div5",*/ 1582 "top_clk26m_clk"; 1583 }; 1584 }; 1585 1586 mmc0: mmc@11230000 { 1587 compatible = "mediatek,mt8183-mmc"; 1588 reg = <0 0x11230000 0 0x1000>, 1589 <0 0x11f50000 0 0x1000>; 1590 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1591 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1592 <&infracfg CLK_INFRA_MSDC0>, 1593 <&infracfg CLK_INFRA_MSDC0_SCK>; 1594 clock-names = "source", "hclk", "source_cg"; 1595 status = "disabled"; 1596 }; 1597 1598 mmc1: mmc@11240000 { 1599 compatible = "mediatek,mt8183-mmc"; 1600 reg = <0 0x11240000 0 0x1000>, 1601 <0 0x11e10000 0 0x1000>; 1602 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1603 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1604 <&infracfg CLK_INFRA_MSDC1>, 1605 <&infracfg CLK_INFRA_MSDC1_SCK>; 1606 clock-names = "source", "hclk", "source_cg"; 1607 status = "disabled"; 1608 }; 1609 1610 mipi_tx0: dsi-phy@11e50000 { 1611 compatible = "mediatek,mt8183-mipi-tx"; 1612 reg = <0 0x11e50000 0 0x1000>; 1613 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1614 #clock-cells = <0>; 1615 #phy-cells = <0>; 1616 clock-output-names = "mipi_tx0_pll"; 1617 nvmem-cells = <&mipi_tx_calibration>; 1618 nvmem-cell-names = "calibration-data"; 1619 }; 1620 1621 efuse: efuse@11f10000 { 1622 compatible = "mediatek,mt8183-efuse", 1623 "mediatek,efuse"; 1624 reg = <0 0x11f10000 0 0x1000>; 1625 #address-cells = <1>; 1626 #size-cells = <1>; 1627 thermal_calibration: calib@180 { 1628 reg = <0x180 0xc>; 1629 }; 1630 1631 mipi_tx_calibration: calib@190 { 1632 reg = <0x190 0xc>; 1633 }; 1634 1635 svs_calibration: calib@580 { 1636 reg = <0x580 0x64>; 1637 }; 1638 }; 1639 1640 u3phy: t-phy@11f40000 { 1641 compatible = "mediatek,mt8183-tphy", 1642 "mediatek,generic-tphy-v2"; 1643 #address-cells = <1>; 1644 #size-cells = <1>; 1645 ranges = <0 0 0x11f40000 0x1000>; 1646 status = "okay"; 1647 1648 u2port0: usb-phy@0 { 1649 reg = <0x0 0x700>; 1650 clocks = <&clk26m>; 1651 clock-names = "ref"; 1652 #phy-cells = <1>; 1653 mediatek,discth = <15>; 1654 status = "okay"; 1655 }; 1656 1657 u3port0: usb-phy@700 { 1658 reg = <0x0700 0x900>; 1659 clocks = <&clk26m>; 1660 clock-names = "ref"; 1661 #phy-cells = <1>; 1662 status = "okay"; 1663 }; 1664 }; 1665 1666 mfgcfg: syscon@13000000 { 1667 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1668 reg = <0 0x13000000 0 0x1000>; 1669 #clock-cells = <1>; 1670 }; 1671 1672 gpu: gpu@13040000 { 1673 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1674 reg = <0 0x13040000 0 0x4000>; 1675 interrupts = 1676 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1677 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1678 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1679 interrupt-names = "job", "mmu", "gpu"; 1680 1681 clocks = <&mfgcfg CLK_MFG_BG3D>; 1682 1683 power-domains = 1684 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1685 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1686 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1687 power-domain-names = "core0", "core1", "core2"; 1688 1689 operating-points-v2 = <&gpu_opp_table>; 1690 }; 1691 1692 mmsys: syscon@14000000 { 1693 compatible = "mediatek,mt8183-mmsys", "syscon"; 1694 reg = <0 0x14000000 0 0x1000>; 1695 #clock-cells = <1>; 1696 #reset-cells = <1>; 1697 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1698 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1699 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1700 }; 1701 1702 mdp3-rdma0@14001000 { 1703 compatible = "mediatek,mt8183-mdp3-rdma"; 1704 reg = <0 0x14001000 0 0x1000>; 1705 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1706 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1707 <CMDQ_EVENT_MDP_RDMA0_EOF>; 1708 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1709 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1710 <&mmsys CLK_MM_MDP_RSZ1>; 1711 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1712 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, 1713 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; 1714 }; 1715 1716 mdp3-rsz0@14003000 { 1717 compatible = "mediatek,mt8183-mdp3-rsz"; 1718 reg = <0 0x14003000 0 0x1000>; 1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 1720 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 1721 <CMDQ_EVENT_MDP_RSZ0_EOF>; 1722 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1723 }; 1724 1725 mdp3-rsz1@14004000 { 1726 compatible = "mediatek,mt8183-mdp3-rsz"; 1727 reg = <0 0x14004000 0 0x1000>; 1728 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 1729 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 1730 <CMDQ_EVENT_MDP_RSZ1_EOF>; 1731 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1732 }; 1733 1734 mdp3-wrot0@14005000 { 1735 compatible = "mediatek,mt8183-mdp3-wrot"; 1736 reg = <0 0x14005000 0 0x1000>; 1737 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1738 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 1739 <CMDQ_EVENT_MDP_WROT0_EOF>; 1740 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1741 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1742 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1743 }; 1744 1745 mdp3-wdma@14006000 { 1746 compatible = "mediatek,mt8183-mdp3-wdma"; 1747 reg = <0 0x14006000 0 0x1000>; 1748 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1749 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, 1750 <CMDQ_EVENT_MDP_WDMA0_EOF>; 1751 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1752 clocks = <&mmsys CLK_MM_MDP_WDMA0>; 1753 iommus = <&iommu M4U_PORT_MDP_WDMA0>; 1754 }; 1755 1756 ovl0: ovl@14008000 { 1757 compatible = "mediatek,mt8183-disp-ovl"; 1758 reg = <0 0x14008000 0 0x1000>; 1759 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1760 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1761 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1762 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1763 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1764 }; 1765 1766 ovl_2l0: ovl@14009000 { 1767 compatible = "mediatek,mt8183-disp-ovl-2l"; 1768 reg = <0 0x14009000 0 0x1000>; 1769 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1770 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1771 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1772 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1773 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1774 }; 1775 1776 ovl_2l1: ovl@1400a000 { 1777 compatible = "mediatek,mt8183-disp-ovl-2l"; 1778 reg = <0 0x1400a000 0 0x1000>; 1779 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1780 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1781 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1782 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1783 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1784 }; 1785 1786 rdma0: rdma@1400b000 { 1787 compatible = "mediatek,mt8183-disp-rdma"; 1788 reg = <0 0x1400b000 0 0x1000>; 1789 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1790 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1791 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1792 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1793 mediatek,rdma-fifo-size = <5120>; 1794 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1795 }; 1796 1797 rdma1: rdma@1400c000 { 1798 compatible = "mediatek,mt8183-disp-rdma"; 1799 reg = <0 0x1400c000 0 0x1000>; 1800 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1801 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1802 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1803 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1804 mediatek,rdma-fifo-size = <2048>; 1805 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1806 }; 1807 1808 color0: color@1400e000 { 1809 compatible = "mediatek,mt8183-disp-color", 1810 "mediatek,mt8173-disp-color"; 1811 reg = <0 0x1400e000 0 0x1000>; 1812 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1813 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1814 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1815 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1816 }; 1817 1818 ccorr0: ccorr@1400f000 { 1819 compatible = "mediatek,mt8183-disp-ccorr"; 1820 reg = <0 0x1400f000 0 0x1000>; 1821 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1822 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1823 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1824 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1825 }; 1826 1827 aal0: aal@14010000 { 1828 compatible = "mediatek,mt8183-disp-aal"; 1829 reg = <0 0x14010000 0 0x1000>; 1830 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1831 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1832 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1833 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1834 }; 1835 1836 gamma0: gamma@14011000 { 1837 compatible = "mediatek,mt8183-disp-gamma"; 1838 reg = <0 0x14011000 0 0x1000>; 1839 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1840 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1841 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1842 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1843 }; 1844 1845 dither0: dither@14012000 { 1846 compatible = "mediatek,mt8183-disp-dither"; 1847 reg = <0 0x14012000 0 0x1000>; 1848 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1849 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1850 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1851 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1852 }; 1853 1854 dsi0: dsi@14014000 { 1855 compatible = "mediatek,mt8183-dsi"; 1856 reg = <0 0x14014000 0 0x1000>; 1857 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1858 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1859 clocks = <&mmsys CLK_MM_DSI0_MM>, 1860 <&mmsys CLK_MM_DSI0_IF>, 1861 <&mipi_tx0>; 1862 clock-names = "engine", "digital", "hs"; 1863 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1864 phys = <&mipi_tx0>; 1865 phy-names = "dphy"; 1866 }; 1867 1868 mutex: mutex@14016000 { 1869 compatible = "mediatek,mt8183-disp-mutex"; 1870 reg = <0 0x14016000 0 0x1000>; 1871 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1872 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1873 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1874 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1875 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1876 }; 1877 1878 larb0: larb@14017000 { 1879 compatible = "mediatek,mt8183-smi-larb"; 1880 reg = <0 0x14017000 0 0x1000>; 1881 mediatek,smi = <&smi_common>; 1882 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1883 <&mmsys CLK_MM_SMI_LARB0>; 1884 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1885 clock-names = "apb", "smi"; 1886 }; 1887 1888 smi_common: smi@14019000 { 1889 compatible = "mediatek,mt8183-smi-common"; 1890 reg = <0 0x14019000 0 0x1000>; 1891 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1892 <&mmsys CLK_MM_SMI_COMMON>, 1893 <&mmsys CLK_MM_GALS_COMM0>, 1894 <&mmsys CLK_MM_GALS_COMM1>; 1895 clock-names = "apb", "smi", "gals0", "gals1"; 1896 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1897 }; 1898 1899 mdp3-ccorr@1401c000 { 1900 compatible = "mediatek,mt8183-mdp3-ccorr"; 1901 reg = <0 0x1401c000 0 0x1000>; 1902 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; 1903 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, 1904 <CMDQ_EVENT_MDP_CCORR_EOF>; 1905 clocks = <&mmsys CLK_MM_MDP_CCORR>; 1906 }; 1907 1908 imgsys: syscon@15020000 { 1909 compatible = "mediatek,mt8183-imgsys", "syscon"; 1910 reg = <0 0x15020000 0 0x1000>; 1911 #clock-cells = <1>; 1912 }; 1913 1914 larb5: larb@15021000 { 1915 compatible = "mediatek,mt8183-smi-larb"; 1916 reg = <0 0x15021000 0 0x1000>; 1917 mediatek,smi = <&smi_common>; 1918 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1919 <&mmsys CLK_MM_GALS_IMG2MM>; 1920 clock-names = "apb", "smi", "gals"; 1921 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1922 }; 1923 1924 larb2: larb@1502f000 { 1925 compatible = "mediatek,mt8183-smi-larb"; 1926 reg = <0 0x1502f000 0 0x1000>; 1927 mediatek,smi = <&smi_common>; 1928 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1929 <&mmsys CLK_MM_GALS_IPU2MM>; 1930 clock-names = "apb", "smi", "gals"; 1931 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1932 }; 1933 1934 vdecsys: syscon@16000000 { 1935 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1936 reg = <0 0x16000000 0 0x1000>; 1937 #clock-cells = <1>; 1938 }; 1939 1940 larb1: larb@16010000 { 1941 compatible = "mediatek,mt8183-smi-larb"; 1942 reg = <0 0x16010000 0 0x1000>; 1943 mediatek,smi = <&smi_common>; 1944 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1945 clock-names = "apb", "smi"; 1946 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1947 }; 1948 1949 vencsys: syscon@17000000 { 1950 compatible = "mediatek,mt8183-vencsys", "syscon"; 1951 reg = <0 0x17000000 0 0x1000>; 1952 #clock-cells = <1>; 1953 }; 1954 1955 larb4: larb@17010000 { 1956 compatible = "mediatek,mt8183-smi-larb"; 1957 reg = <0 0x17010000 0 0x1000>; 1958 mediatek,smi = <&smi_common>; 1959 clocks = <&vencsys CLK_VENC_LARB>, 1960 <&vencsys CLK_VENC_LARB>; 1961 clock-names = "apb", "smi"; 1962 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1963 }; 1964 1965 venc_jpg: venc_jpg@17030000 { 1966 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 1967 reg = <0 0x17030000 0 0x1000>; 1968 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 1969 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 1970 <&iommu M4U_PORT_JPGENC_BSDMA>; 1971 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1972 clocks = <&vencsys CLK_VENC_JPGENC>; 1973 clock-names = "jpgenc"; 1974 }; 1975 1976 ipu_conn: syscon@19000000 { 1977 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1978 reg = <0 0x19000000 0 0x1000>; 1979 #clock-cells = <1>; 1980 }; 1981 1982 ipu_adl: syscon@19010000 { 1983 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1984 reg = <0 0x19010000 0 0x1000>; 1985 #clock-cells = <1>; 1986 }; 1987 1988 ipu_core0: syscon@19180000 { 1989 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1990 reg = <0 0x19180000 0 0x1000>; 1991 #clock-cells = <1>; 1992 }; 1993 1994 ipu_core1: syscon@19280000 { 1995 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1996 reg = <0 0x19280000 0 0x1000>; 1997 #clock-cells = <1>; 1998 }; 1999 2000 camsys: syscon@1a000000 { 2001 compatible = "mediatek,mt8183-camsys", "syscon"; 2002 reg = <0 0x1a000000 0 0x1000>; 2003 #clock-cells = <1>; 2004 }; 2005 2006 larb6: larb@1a001000 { 2007 compatible = "mediatek,mt8183-smi-larb"; 2008 reg = <0 0x1a001000 0 0x1000>; 2009 mediatek,smi = <&smi_common>; 2010 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 2011 <&mmsys CLK_MM_GALS_CAM2MM>; 2012 clock-names = "apb", "smi", "gals"; 2013 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2014 }; 2015 2016 larb3: larb@1a002000 { 2017 compatible = "mediatek,mt8183-smi-larb"; 2018 reg = <0 0x1a002000 0 0x1000>; 2019 mediatek,smi = <&smi_common>; 2020 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 2021 <&mmsys CLK_MM_GALS_IPU12MM>; 2022 clock-names = "apb", "smi", "gals"; 2023 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2024 }; 2025 }; 2026}; 2027