xref: /linux/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts (revision b7e1e969c887c897947fdc3754fe9b0c24acb155) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021 BayLibre, SAS.
4 * Author: Fabien Parent <fparent@baylibre.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include "mt8183.dtsi"
12#include "mt6358.dtsi"
13
14/ {
15	model = "Pumpkin MT8183";
16	compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
17
18	aliases {
19		serial0 = &uart0;
20	};
21
22	memory@40000000 {
23		device_type = "memory";
24		reg = <0 0x40000000 0 0x80000000>;
25	};
26
27	chosen {
28		stdout-path = "serial0:921600n8";
29	};
30
31	reserved-memory {
32		#address-cells = <2>;
33		#size-cells = <2>;
34		ranges;
35
36		scp_mem_reserved: scp-mem@50000000 {
37			compatible = "shared-dma-pool";
38			reg = <0 0x50000000 0 0x2900000>;
39			no-map;
40		};
41	};
42
43	leds {
44		compatible = "gpio-leds";
45
46		led-red {
47			label = "red";
48			gpios = <&pio 155 GPIO_ACTIVE_HIGH>;
49			default-state = "off";
50		};
51
52		led-green {
53			label = "green";
54			gpios = <&pio 156 GPIO_ACTIVE_HIGH>;
55			default-state = "off";
56		};
57	};
58
59	thermistor {
60		compatible = "murata,ncp03wf104";
61		pullup-uv = <1800000>;
62		pullup-ohm = <390000>;
63		pulldown-ohm = <0>;
64		io-channels = <&auxadc 0>;
65	};
66};
67
68&auxadc {
69	status = "okay";
70};
71
72&gpu {
73	mali-supply = <&mt6358_vgpu_reg>;
74};
75
76&i2c0 {
77	pinctrl-names = "default";
78	pinctrl-0 = <&i2c_pins_0>;
79	status = "okay";
80	clock-frequency = <100000>;
81};
82
83&i2c1 {
84	pinctrl-names = "default";
85	pinctrl-0 = <&i2c_pins_1>;
86	status = "okay";
87	clock-frequency = <100000>;
88};
89
90&i2c2 {
91	pinctrl-names = "default";
92	pinctrl-0 = <&i2c_pins_2>;
93	status = "okay";
94	clock-frequency = <100000>;
95};
96
97&i2c3 {
98	pinctrl-names = "default";
99	pinctrl-0 = <&i2c_pins_3>;
100	status = "okay";
101	clock-frequency = <100000>;
102};
103
104&i2c4 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&i2c_pins_4>;
107	status = "okay";
108	clock-frequency = <100000>;
109};
110
111&i2c5 {
112	pinctrl-names = "default";
113	pinctrl-0 = <&i2c_pins_5>;
114	status = "okay";
115	clock-frequency = <100000>;
116};
117
118&i2c6 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&i2c6_pins>;
121	status = "okay";
122	clock-frequency = <100000>;
123};
124
125&keyboard {
126	pinctrl-names = "default";
127	pinctrl-0 = <&keyboard_pins>;
128	status = "okay";
129	linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN)
130			MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP)>;
131	keypad,num-rows = <2>;
132	keypad,num-columns = <1>;
133	debounce-delay-ms = <32>;
134	mediatek,keys-per-group = <2>;
135};
136
137&mmc0 {
138	status = "okay";
139	pinctrl-names = "default", "state_uhs";
140	pinctrl-0 = <&mmc0_pins_default>;
141	pinctrl-1 = <&mmc0_pins_uhs>;
142	bus-width = <8>;
143	max-frequency = <200000000>;
144	cap-mmc-highspeed;
145	mmc-hs200-1_8v;
146	mmc-hs400-1_8v;
147	cap-mmc-hw-reset;
148	no-sdio;
149	no-sd;
150	hs400-ds-delay = <0x12814>;
151	vmmc-supply = <&mt6358_vemc_reg>;
152	vqmmc-supply = <&mt6358_vio18_reg>;
153	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
154	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
155	non-removable;
156};
157
158&mmc1 {
159	status = "okay";
160	pinctrl-names = "default", "state_uhs";
161	pinctrl-0 = <&mmc1_pins_default>;
162	pinctrl-1 = <&mmc1_pins_uhs>;
163	bus-width = <4>;
164	max-frequency = <200000000>;
165	cap-sd-highspeed;
166	sd-uhs-sdr50;
167	sd-uhs-sdr104;
168	cap-sdio-irq;
169	no-mmc;
170	no-sd;
171	vmmc-supply = <&mt6358_vmch_reg>;
172	vqmmc-supply = <&mt6358_vmc_reg>;
173	keep-power-in-suspend;
174	wakeup-source;
175	non-removable;
176};
177
178&mt6358_vgpu_reg {
179	regulator-min-microvolt = <625000>;
180	regulator-max-microvolt = <900000>;
181
182	regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
183	regulator-coupled-max-spread = <100000>;
184};
185
186&mt6358_vsram_gpu_reg {
187	regulator-min-microvolt = <850000>;
188	regulator-max-microvolt = <1000000>;
189
190	regulator-coupled-with = <&mt6358_vgpu_reg>;
191	regulator-coupled-max-spread = <100000>;
192};
193
194&pio {
195	i2c_pins_0: i2c0 {
196		pins_i2c {
197			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
198				 <PINMUX_GPIO83__FUNC_SCL0>;
199			mediatek,pull-up-adv = <3>;
200			mediatek,drive-strength-adv = <00>;
201		};
202	};
203
204	i2c_pins_1: i2c1 {
205		pins_i2c {
206			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
207				 <PINMUX_GPIO84__FUNC_SCL1>;
208			mediatek,pull-up-adv = <3>;
209			mediatek,drive-strength-adv = <00>;
210		};
211	};
212
213	i2c_pins_2: i2c2 {
214		pins_i2c {
215			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
216				 <PINMUX_GPIO104__FUNC_SDA2>;
217			mediatek,pull-up-adv = <3>;
218			mediatek,drive-strength-adv = <00>;
219		};
220	};
221
222	i2c_pins_3: i2c3 {
223		pins_i2c {
224			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
225				 <PINMUX_GPIO51__FUNC_SDA3>;
226			mediatek,pull-up-adv = <3>;
227			mediatek,drive-strength-adv = <00>;
228		};
229	};
230
231	i2c_pins_4: i2c4 {
232		pins_i2c {
233			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
234				 <PINMUX_GPIO106__FUNC_SDA4>;
235			mediatek,pull-up-adv = <3>;
236			mediatek,drive-strength-adv = <00>;
237		};
238	};
239
240	i2c_pins_5: i2c5 {
241		pins_i2c {
242			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
243				 <PINMUX_GPIO49__FUNC_SDA5>;
244			mediatek,pull-up-adv = <3>;
245			mediatek,drive-strength-adv = <00>;
246		};
247	};
248
249	i2c6_pins: i2c6 {
250		pins_cmd_dat {
251			pinmux = <PINMUX_GPIO113__FUNC_SCL6>,
252				 <PINMUX_GPIO114__FUNC_SDA6>;
253			mediatek,pull-up-adv = <3>;
254		};
255	};
256
257	keyboard_pins: keyboard {
258		pins_keyboard {
259			pinmux = <PINMUX_GPIO91__FUNC_KPROW1>,
260				 <PINMUX_GPIO92__FUNC_KPROW0>,
261				 <PINMUX_GPIO93__FUNC_KPCOL0>;
262		};
263	};
264
265	mmc0_pins_default: mmc0-pins-default {
266		pins_cmd_dat {
267			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
268				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
269				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
270				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
271				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
272				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
273				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
274				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
275				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
276			input-enable;
277			drive-strength = <MTK_DRIVE_14mA>;
278			mediatek,pull-up-adv = <01>;
279		};
280
281		pins_clk {
282			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
283			drive-strength = <MTK_DRIVE_14mA>;
284			mediatek,pull-down-adv = <10>;
285		};
286
287		pins_rst {
288			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
289			drive-strength = <MTK_DRIVE_14mA>;
290			mediatek,pull-down-adv = <01>;
291		};
292	};
293
294	mmc0_pins_uhs: mmc0-pins-uhs {
295		pins_cmd_dat {
296			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
297				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
298				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
299				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
300				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
301				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
302				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
303				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
304				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
305			input-enable;
306			drive-strength = <MTK_DRIVE_14mA>;
307			mediatek,pull-up-adv = <01>;
308		};
309
310		pins_clk {
311			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
312			drive-strength = <MTK_DRIVE_14mA>;
313			mediatek,pull-down-adv = <10>;
314		};
315
316		pins_ds {
317			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
318			drive-strength = <MTK_DRIVE_14mA>;
319			mediatek,pull-down-adv = <10>;
320		};
321
322		pins_rst {
323			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
324			drive-strength = <MTK_DRIVE_14mA>;
325			mediatek,pull-up-adv = <01>;
326		};
327	};
328
329	mmc1_pins_default: mmc1-pins-default {
330		pins_cmd_dat {
331			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
332				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
333				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
334				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
335				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
336			input-enable;
337			mediatek,pull-up-adv = <10>;
338		};
339
340		pins_clk {
341			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
342			input-enable;
343			mediatek,pull-down-adv = <10>;
344		};
345
346		pins_pmu {
347			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>;
348			output-high;
349		};
350	};
351
352	mmc1_pins_uhs: mmc1-pins-uhs {
353		pins_cmd_dat {
354			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
355				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
356				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
357				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
358				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
359			drive-strength = <MTK_DRIVE_6mA>;
360			input-enable;
361			mediatek,pull-up-adv = <10>;
362		};
363
364		pins_clk {
365			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
366			drive-strength = <MTK_DRIVE_8mA>;
367			mediatek,pull-down-adv = <10>;
368			input-enable;
369		};
370	};
371};
372
373&pmic {
374	interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
375};
376
377&mfg {
378	domain-supply = <&mt6358_vgpu_reg>;
379};
380
381&cpu0 {
382	proc-supply = <&mt6358_vproc12_reg>;
383};
384
385&cpu1 {
386	proc-supply = <&mt6358_vproc12_reg>;
387};
388
389&cpu2 {
390	proc-supply = <&mt6358_vproc12_reg>;
391};
392
393&cpu3 {
394	proc-supply = <&mt6358_vproc12_reg>;
395};
396
397&cpu4 {
398	proc-supply = <&mt6358_vproc11_reg>;
399};
400
401&cpu5 {
402	proc-supply = <&mt6358_vproc11_reg>;
403};
404
405&cpu6 {
406	proc-supply = <&mt6358_vproc11_reg>;
407};
408
409&cpu7 {
410	proc-supply = <&mt6358_vproc11_reg>;
411};
412
413&uart0 {
414	status = "okay";
415};
416
417&scp {
418	status = "okay";
419};
420
421&dsi0 {
422	status = "disabled";
423};
424