1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 /* system wide semi-regulated power rail from charger */ 107 reg_vsys: regulator-vsys { 108 compatible = "regulator-fixed"; 109 regulator-name = "vsys"; 110 regulator-always-on; 111 regulator-boot-on; 112 }; 113 114 reserved_memory: reserved-memory { 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 119 scp_mem_reserved: memory@50000000 { 120 compatible = "shared-dma-pool"; 121 reg = <0 0x50000000 0 0x2900000>; 122 no-map; 123 }; 124 }; 125 126 sound: mt8183-sound { 127 mediatek,platform = <&afe>; 128 pinctrl-names = "default", 129 "aud_tdm_out_on", 130 "aud_tdm_out_off"; 131 pinctrl-0 = <&aud_pins_default>; 132 pinctrl-1 = <&aud_pins_tdm_out_on>; 133 pinctrl-2 = <&aud_pins_tdm_out_off>; 134 status = "okay"; 135 }; 136 137 btsco: bt-sco { 138 compatible = "linux,bt-sco"; 139 }; 140 141 wifi_pwrseq: wifi-pwrseq { 142 compatible = "mmc-pwrseq-simple"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&wifi_pins_pwrseq>; 145 146 /* Toggle WIFI_ENABLE to reset the chip. */ 147 reset-gpios = <&pio 119 1>; 148 }; 149 150 wifi_wakeup: wifi-wakeup { 151 compatible = "gpio-keys"; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&wifi_pins_wakeup>; 154 155 button-wowlan { 156 label = "Wake on WiFi"; 157 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 158 linux,code = <KEY_WAKEUP>; 159 wakeup-source; 160 }; 161 }; 162 163 tboard_thermistor1: thermal-sensor1 { 164 compatible = "generic-adc-thermal"; 165 #thermal-sensor-cells = <0>; 166 io-channels = <&auxadc 0>; 167 io-channel-names = "sensor-channel"; 168 temperature-lookup-table = < (-5000) 1553 169 0 1488 170 5000 1412 171 10000 1326 172 15000 1232 173 20000 1132 174 25000 1029 175 30000 925 176 35000 823 177 40000 726 178 45000 635 179 50000 552 180 55000 478 181 60000 411 182 65000 353 183 70000 303 184 75000 260 185 80000 222 186 85000 190 187 90000 163 188 95000 140 189 100000 121 190 105000 104 191 110000 90 192 115000 78 193 120000 67 194 125000 59>; 195 }; 196 197 tboard_thermistor2: thermal-sensor2 { 198 compatible = "generic-adc-thermal"; 199 #thermal-sensor-cells = <0>; 200 io-channels = <&auxadc 1>; 201 io-channel-names = "sensor-channel"; 202 temperature-lookup-table = < (-5000) 1553 203 0 1488 204 5000 1412 205 10000 1326 206 15000 1232 207 20000 1132 208 25000 1029 209 30000 925 210 35000 823 211 40000 726 212 45000 635 213 50000 552 214 55000 478 215 60000 411 216 65000 353 217 70000 303 218 75000 260 219 80000 222 220 85000 190 221 90000 163 222 95000 140 223 100000 121 224 105000 104 225 110000 90 226 115000 78 227 120000 67 228 125000 59>; 229 }; 230}; 231 232&auxadc { 233 status = "okay"; 234}; 235 236&cci { 237 proc-supply = <&mt6358_vproc12_reg>; 238}; 239 240&cpu0 { 241 proc-supply = <&mt6358_vproc12_reg>; 242}; 243 244&cpu1 { 245 proc-supply = <&mt6358_vproc12_reg>; 246}; 247 248&cpu2 { 249 proc-supply = <&mt6358_vproc12_reg>; 250}; 251 252&cpu3 { 253 proc-supply = <&mt6358_vproc12_reg>; 254}; 255 256&cpu4 { 257 proc-supply = <&mt6358_vproc11_reg>; 258}; 259 260&cpu5 { 261 proc-supply = <&mt6358_vproc11_reg>; 262}; 263 264&cpu6 { 265 proc-supply = <&mt6358_vproc11_reg>; 266}; 267 268&cpu7 { 269 proc-supply = <&mt6358_vproc11_reg>; 270}; 271 272&dsi0 { 273 status = "okay"; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 panel: panel@0 { 277 /* compatible will be set in board dts */ 278 reg = <0>; 279 enable-gpios = <&pio 45 0>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&panel_pins_default>; 282 avdd-supply = <&ppvarn_lcd>; 283 avee-supply = <&ppvarp_lcd>; 284 pp1800-supply = <&pp1800_lcd>; 285 backlight = <&backlight_lcd0>; 286 rotation = <270>; 287 port { 288 panel_in: endpoint { 289 remote-endpoint = <&dsi_out>; 290 }; 291 }; 292 }; 293 294 ports { 295 port { 296 dsi_out: endpoint { 297 remote-endpoint = <&panel_in>; 298 }; 299 }; 300 }; 301}; 302 303&gic { 304 mediatek,broken-save-restore-fw; 305}; 306 307&gpu { 308 mali-supply = <&mt6358_vgpu_reg>; 309}; 310 311&i2c0 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c0_pins>; 314 status = "okay"; 315 clock-frequency = <400000>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318}; 319 320&i2c1 { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c1_pins>; 323 status = "okay"; 324 clock-frequency = <100000>; 325}; 326 327&i2c3 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c3_pins>; 330 status = "okay"; 331 clock-frequency = <100000>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334}; 335 336&i2c5 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c5_pins>; 339 status = "okay"; 340 clock-frequency = <100000>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343}; 344 345&i2c6 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&i2c6_pins>; 348 status = "okay"; 349 clock-frequency = <100000>; 350}; 351 352&mipi_tx0 { 353 status = "okay"; 354}; 355 356&mmc0 { 357 status = "okay"; 358 pinctrl-names = "default", "state_uhs"; 359 pinctrl-0 = <&mmc0_pins_default>; 360 pinctrl-1 = <&mmc0_pins_uhs>; 361 bus-width = <8>; 362 max-frequency = <200000000>; 363 cap-mmc-highspeed; 364 mmc-hs200-1_8v; 365 mmc-hs400-1_8v; 366 cap-mmc-hw-reset; 367 no-sdio; 368 no-sd; 369 hs400-ds-delay = <0x12814>; 370 vmmc-supply = <&mt6358_vemc_reg>; 371 vqmmc-supply = <&mt6358_vio18_reg>; 372 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 373 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 374 non-removable; 375}; 376 377&mmc1 { 378 status = "okay"; 379 pinctrl-names = "default", "state_uhs"; 380 pinctrl-0 = <&mmc1_pins_default>; 381 pinctrl-1 = <&mmc1_pins_uhs>; 382 vmmc-supply = <&mmc1_fixed_power>; 383 vqmmc-supply = <&mmc1_fixed_io>; 384 mmc-pwrseq = <&wifi_pwrseq>; 385 bus-width = <4>; 386 max-frequency = <200000000>; 387 cap-sd-highspeed; 388 sd-uhs-sdr50; 389 sd-uhs-sdr104; 390 keep-power-in-suspend; 391 wakeup-source; 392 cap-sdio-irq; 393 non-removable; 394 no-mmc; 395 no-sd; 396 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 397 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 qca_wifi: qca-wifi@1 { 402 compatible = "qcom,ath10k"; 403 reg = <1>; 404 }; 405}; 406 407&mt6358_vdram2_reg { 408 regulator-always-on; 409}; 410 411&mt6358codec { 412 Avdd-supply = <&mt6358_vaud28_reg>; 413}; 414 415&mt6358regulator { 416 vsys-ldo1-supply = <®_vsys>; 417 vsys-ldo2-supply = <®_vsys>; 418 vsys-ldo3-supply = <®_vsys>; 419 vsys-vcore-supply = <®_vsys>; 420 vsys-vdram1-supply = <®_vsys>; 421 vsys-vgpu-supply = <®_vsys>; 422 vsys-vmodem-supply = <®_vsys>; 423 vsys-vpa-supply = <®_vsys>; 424 vsys-vproc11-supply = <®_vsys>; 425 vsys-vproc12-supply = <®_vsys>; 426 vsys-vs1-supply = <®_vsys>; 427 vsys-vs2-supply = <®_vsys>; 428 vs1-ldo1-supply = <&mt6358_vs1_reg>; 429 vs2-ldo1-supply = <&mt6358_vdram1_reg>; 430 vs2-ldo2-supply = <&mt6358_vs2_reg>; 431 vs2-ldo3-supply = <&mt6358_vs2_reg>; 432 vs2-ldo4-supply = <&mt6358_vs2_reg>; 433}; 434 435&mt6358_vgpu_reg { 436 regulator-min-microvolt = <625000>; 437 regulator-max-microvolt = <900000>; 438 439 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 440 regulator-coupled-max-spread = <100000>; 441}; 442 443&mt6358_vsim1_reg { 444 regulator-min-microvolt = <2700000>; 445 regulator-max-microvolt = <2700000>; 446}; 447 448&mt6358_vsim2_reg { 449 regulator-min-microvolt = <2700000>; 450 regulator-max-microvolt = <2700000>; 451}; 452 453&mt6358_vsram_gpu_reg { 454 regulator-min-microvolt = <850000>; 455 regulator-max-microvolt = <1000000>; 456 457 regulator-coupled-with = <&mt6358_vgpu_reg>; 458 regulator-coupled-max-spread = <100000>; 459}; 460 461&pio { 462 aud_pins_default: audiopins { 463 pins-bus { 464 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 465 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 466 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 467 <PINMUX_GPIO102__FUNC_I2S2_DI>, 468 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 469 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 470 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 471 <PINMUX_GPIO91__FUNC_I2S5_DO>, 472 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 473 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 474 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 475 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 476 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 477 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 478 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 479 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 480 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 481 }; 482 }; 483 484 aud_pins_tdm_out_on: audiotdmouton { 485 pins-bus { 486 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 487 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 488 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 489 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 490 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 491 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 492 drive-strength = <MTK_DRIVE_6mA>; 493 }; 494 }; 495 496 aud_pins_tdm_out_off: audiotdmoutoff { 497 pins-bus { 498 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 499 <PINMUX_GPIO170__FUNC_GPIO170>, 500 <PINMUX_GPIO171__FUNC_GPIO171>, 501 <PINMUX_GPIO172__FUNC_GPIO172>, 502 <PINMUX_GPIO173__FUNC_GPIO173>, 503 <PINMUX_GPIO10__FUNC_GPIO10>; 504 input-enable; 505 bias-pull-down; 506 drive-strength = <MTK_DRIVE_2mA>; 507 }; 508 }; 509 510 bt_pins: bt-pins { 511 pins-bt-en { 512 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 513 output-low; 514 }; 515 }; 516 517 ec_ap_int_odl: ec-ap-int-odl { 518 pins1 { 519 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 520 input-enable; 521 bias-pull-up; 522 }; 523 }; 524 525 h1_int_od_l: h1-int-od-l { 526 pins1 { 527 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 528 input-enable; 529 }; 530 }; 531 532 i2c0_pins: i2c0 { 533 pins-bus { 534 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 535 <PINMUX_GPIO83__FUNC_SCL0>; 536 mediatek,pull-up-adv = <3>; 537 mediatek,drive-strength-adv = <00>; 538 }; 539 }; 540 541 i2c1_pins: i2c1 { 542 pins-bus { 543 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 544 <PINMUX_GPIO84__FUNC_SCL1>; 545 mediatek,pull-up-adv = <3>; 546 mediatek,drive-strength-adv = <00>; 547 }; 548 }; 549 550 i2c2_pins: i2c2 { 551 pins-bus { 552 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 553 <PINMUX_GPIO104__FUNC_SDA2>; 554 bias-disable; 555 mediatek,drive-strength-adv = <00>; 556 }; 557 }; 558 559 i2c3_pins: i2c3 { 560 pins-bus { 561 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 562 <PINMUX_GPIO51__FUNC_SDA3>; 563 mediatek,pull-up-adv = <3>; 564 mediatek,drive-strength-adv = <00>; 565 }; 566 }; 567 568 i2c4_pins: i2c4 { 569 pins-bus { 570 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 571 <PINMUX_GPIO106__FUNC_SDA4>; 572 bias-disable; 573 mediatek,drive-strength-adv = <00>; 574 }; 575 }; 576 577 i2c5_pins: i2c5 { 578 pins-bus { 579 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 580 <PINMUX_GPIO49__FUNC_SDA5>; 581 mediatek,pull-up-adv = <3>; 582 mediatek,drive-strength-adv = <00>; 583 }; 584 }; 585 586 i2c6_pins: i2c6 { 587 pins-bus { 588 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 589 <PINMUX_GPIO12__FUNC_SDA6>; 590 bias-disable; 591 }; 592 }; 593 594 mmc0_pins_default: mmc0-pins-default { 595 pins-cmd-dat { 596 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 597 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 598 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 599 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 600 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 601 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 602 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 603 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 604 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 605 input-enable; 606 drive-strength = <MTK_DRIVE_14mA>; 607 mediatek,pull-up-adv = <01>; 608 }; 609 610 pins-clk { 611 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 612 drive-strength = <MTK_DRIVE_14mA>; 613 mediatek,pull-down-adv = <10>; 614 }; 615 616 pins-rst { 617 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 618 drive-strength = <MTK_DRIVE_14mA>; 619 mediatek,pull-down-adv = <01>; 620 }; 621 }; 622 623 mmc0_pins_uhs: mmc0-pins-uhs { 624 pins-cmd-dat { 625 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 626 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 627 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 628 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 629 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 630 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 631 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 632 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 633 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 634 input-enable; 635 drive-strength = <MTK_DRIVE_14mA>; 636 mediatek,pull-up-adv = <01>; 637 }; 638 639 pins-clk { 640 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 641 drive-strength = <MTK_DRIVE_14mA>; 642 mediatek,pull-down-adv = <10>; 643 }; 644 645 pins-ds { 646 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 647 drive-strength = <MTK_DRIVE_14mA>; 648 mediatek,pull-down-adv = <10>; 649 }; 650 651 pins-rst { 652 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 653 drive-strength = <MTK_DRIVE_14mA>; 654 mediatek,pull-up-adv = <01>; 655 }; 656 }; 657 658 mmc1_pins_default: mmc1-pins-default { 659 pins-cmd-dat { 660 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 661 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 662 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 663 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 664 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 665 input-enable; 666 mediatek,pull-up-adv = <10>; 667 }; 668 669 pins-clk { 670 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 671 input-enable; 672 mediatek,pull-down-adv = <10>; 673 }; 674 }; 675 676 mmc1_pins_uhs: mmc1-pins-uhs { 677 pins-cmd-dat { 678 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 679 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 680 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 681 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 682 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 683 drive-strength = <MTK_DRIVE_6mA>; 684 input-enable; 685 mediatek,pull-up-adv = <10>; 686 }; 687 688 pins-clk { 689 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 690 drive-strength = <MTK_DRIVE_8mA>; 691 mediatek,pull-down-adv = <10>; 692 input-enable; 693 }; 694 }; 695 696 panel_pins_default: panel-pins-default { 697 panel-reset { 698 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 699 output-low; 700 bias-pull-up; 701 }; 702 }; 703 704 pwm0_pin_default: pwm0-pin-default { 705 pins1 { 706 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 707 output-high; 708 bias-pull-up; 709 }; 710 pins2 { 711 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 712 }; 713 }; 714 715 scp_pins: scp { 716 pins-scp-uart { 717 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 718 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 719 }; 720 }; 721 722 spi0_pins: spi0 { 723 pins-spi { 724 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 725 <PINMUX_GPIO86__FUNC_GPIO86>, 726 <PINMUX_GPIO87__FUNC_SPI0_MO>, 727 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 728 bias-disable; 729 }; 730 }; 731 732 spi1_pins: spi1 { 733 pins-spi { 734 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 735 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 736 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 737 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 738 bias-disable; 739 }; 740 }; 741 742 spi2_pins: spi2 { 743 pins-spi { 744 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 745 <PINMUX_GPIO1__FUNC_SPI2_MO>, 746 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 747 bias-disable; 748 }; 749 pins-spi-mi { 750 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 751 mediatek,pull-down-adv = <00>; 752 }; 753 }; 754 755 spi3_pins: spi3 { 756 pins-spi { 757 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 758 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 759 <PINMUX_GPIO23__FUNC_SPI3_MO>, 760 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 761 bias-disable; 762 }; 763 }; 764 765 spi4_pins: spi4 { 766 pins-spi { 767 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 768 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 769 <PINMUX_GPIO19__FUNC_SPI4_MO>, 770 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 771 bias-disable; 772 }; 773 }; 774 775 spi5_pins: spi5 { 776 pins-spi { 777 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 778 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 779 <PINMUX_GPIO15__FUNC_SPI5_MO>, 780 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 781 bias-disable; 782 }; 783 }; 784 785 uart0_pins_default: uart0-pins-default { 786 pins-rx { 787 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 788 input-enable; 789 bias-pull-up; 790 }; 791 pins-tx { 792 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 793 }; 794 }; 795 796 uart1_pins_default: uart1-pins-default { 797 pins-rx { 798 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 799 input-enable; 800 bias-pull-up; 801 }; 802 pins-tx { 803 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 804 }; 805 pins-rts { 806 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 807 output-enable; 808 }; 809 pins-cts { 810 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 811 input-enable; 812 }; 813 }; 814 815 uart1_pins_sleep: uart1-pins-sleep { 816 pins-rx { 817 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 818 input-enable; 819 bias-pull-up; 820 }; 821 pins-tx { 822 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 823 }; 824 pins-rts { 825 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 826 output-enable; 827 }; 828 pins-cts { 829 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 830 input-enable; 831 }; 832 }; 833 834 wifi_pins_pwrseq: wifi-pins-pwrseq { 835 pins-wifi-enable { 836 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 837 output-low; 838 }; 839 }; 840 841 wifi_pins_wakeup: wifi-pins-wakeup { 842 pins-wifi-wakeup { 843 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 844 input-enable; 845 }; 846 }; 847}; 848 849&pwm0 { 850 status = "okay"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&pwm0_pin_default>; 853}; 854 855&scp { 856 status = "okay"; 857 858 firmware-name = "mediatek/mt8183/scp.img"; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&scp_pins>; 861 862 cros-ec-rpmsg { 863 compatible = "google,cros-ec-rpmsg"; 864 mediatek,rpmsg-name = "cros-ec-rpmsg"; 865 }; 866}; 867 868&mfg_async { 869 domain-supply = <&mt6358_vsram_gpu_reg>; 870}; 871 872&mfg { 873 domain-supply = <&mt6358_vgpu_reg>; 874}; 875 876&soc_data { 877 status = "okay"; 878}; 879 880&spi0 { 881 pinctrl-names = "default"; 882 pinctrl-0 = <&spi0_pins>; 883 mediatek,pad-select = <0>; 884 status = "okay"; 885 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 886 887 cr50@0 { 888 compatible = "google,cr50"; 889 reg = <0>; 890 spi-max-frequency = <1000000>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&h1_int_od_l>; 893 interrupt-parent = <&pio>; 894 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 895 }; 896}; 897 898&spi1 { 899 pinctrl-names = "default"; 900 pinctrl-0 = <&spi1_pins>; 901 mediatek,pad-select = <0>; 902 status = "okay"; 903 904 w25q64dw: flash@0 { 905 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 906 reg = <0>; 907 spi-max-frequency = <25000000>; 908 }; 909}; 910 911&spi2 { 912 pinctrl-names = "default"; 913 pinctrl-0 = <&spi2_pins>; 914 mediatek,pad-select = <0>; 915 status = "okay"; 916 917 cros_ec: cros-ec@0 { 918 compatible = "google,cros-ec-spi"; 919 reg = <0>; 920 spi-max-frequency = <3000000>; 921 interrupt-parent = <&pio>; 922 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&ec_ap_int_odl>; 925 926 i2c_tunnel: i2c-tunnel { 927 compatible = "google,cros-ec-i2c-tunnel"; 928 google,remote-bus = <1>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 }; 932 933 usbc_extcon: extcon0 { 934 compatible = "google,extcon-usbc-cros-ec"; 935 google,usb-port-id = <0>; 936 }; 937 938 cbas { 939 compatible = "google,cros-cbas"; 940 }; 941 942 typec { 943 compatible = "google,cros-ec-typec"; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 usb_c0: connector@0 { 948 compatible = "usb-c-connector"; 949 reg = <0>; 950 power-role = "dual"; 951 data-role = "host"; 952 try-power-role = "sink"; 953 }; 954 }; 955 }; 956}; 957 958&spi3 { 959 pinctrl-names = "default"; 960 pinctrl-0 = <&spi3_pins>; 961 mediatek,pad-select = <0>; 962 status = "disabled"; 963}; 964 965&spi4 { 966 pinctrl-names = "default"; 967 pinctrl-0 = <&spi4_pins>; 968 mediatek,pad-select = <0>; 969 status = "disabled"; 970}; 971 972&spi5 { 973 pinctrl-names = "default"; 974 pinctrl-0 = <&spi5_pins>; 975 mediatek,pad-select = <0>; 976 status = "disabled"; 977}; 978 979&ssusb { 980 dr_mode = "host"; 981 wakeup-source; 982 vusb33-supply = <&mt6358_vusb_reg>; 983 status = "okay"; 984}; 985 986&thermal_zones { 987 tboard1 { 988 polling-delay = <1000>; /* milliseconds */ 989 polling-delay-passive = <0>; /* milliseconds */ 990 thermal-sensors = <&tboard_thermistor1>; 991 }; 992 993 tboard2 { 994 polling-delay = <1000>; /* milliseconds */ 995 polling-delay-passive = <0>; /* milliseconds */ 996 thermal-sensors = <&tboard_thermistor2>; 997 }; 998}; 999 1000&u3phy { 1001 status = "okay"; 1002}; 1003 1004&uart0 { 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&uart0_pins_default>; 1007 status = "okay"; 1008}; 1009 1010&uart1 { 1011 pinctrl-names = "default", "sleep"; 1012 pinctrl-0 = <&uart1_pins_default>; 1013 pinctrl-1 = <&uart1_pins_sleep>; 1014 status = "okay"; 1015 /delete-property/ interrupts; 1016 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 1017 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 1018 1019 bluetooth: bluetooth { 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&bt_pins>; 1022 status = "okay"; 1023 compatible = "qcom,qca6174-bt"; 1024 enable-gpios = <&pio 120 0>; 1025 clocks = <&clk32k>; 1026 firmware-name = "nvm_00440302_i2s.bin"; 1027 }; 1028}; 1029 1030&usb_host { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 vusb33-supply = <&mt6358_vusb_reg>; 1034 status = "okay"; 1035 1036 hub@1 { 1037 compatible = "usb5e3,610"; 1038 reg = <1>; 1039 }; 1040}; 1041 1042#include <arm/cros-ec-sbs.dtsi> 1043