1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <®_vsys>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 vin-supply = <&pp1800_alw>; 53 }; 54 55 pp1800_alw: regulator5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "pp1800_alw"; 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 vin-supply = <®_vsys>; 63 }; 64 65 pp3300_alw: regulator6 { 66 compatible = "regulator-fixed"; 67 regulator-name = "pp3300_alw"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <®_vsys>; 73 }; 74 75 /* system wide semi-regulated power rail from charger */ 76 reg_vsys: regulator-vsys { 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys"; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 reserved_memory: reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 afe_dma_mem: audio-dma-pool { 89 compatible = "shared-dma-pool"; 90 size = <0 0x100000>; 91 alignment = <0 0x10>; 92 no-map; 93 }; 94 95 scp_mem_reserved: memory@50000000 { 96 compatible = "shared-dma-pool"; 97 reg = <0 0x50000000 0 0x2900000>; 98 no-map; 99 }; 100 }; 101 102 sound: mt8183-sound { 103 mediatek,platform = <&afe>; 104 pinctrl-names = "default", 105 "aud_tdm_out_on", 106 "aud_tdm_out_off"; 107 pinctrl-0 = <&aud_pins_default>; 108 pinctrl-1 = <&aud_pins_tdm_out_on>; 109 pinctrl-2 = <&aud_pins_tdm_out_off>; 110 status = "okay"; 111 }; 112 113 btsco: bt-sco { 114 compatible = "linux,bt-sco"; 115 #sound-dai-cells = <0>; 116 }; 117 118 wifi_pwrseq: wifi-pwrseq { 119 compatible = "mmc-pwrseq-simple"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&wifi_pins_pwrseq>; 122 123 /* Toggle WIFI_ENABLE to reset the chip. */ 124 reset-gpios = <&pio 119 1>; 125 }; 126 127 wifi_wakeup: wifi-wakeup { 128 compatible = "gpio-keys"; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&wifi_pins_wakeup>; 131 132 wifi_wakeup_event: event-wowlan { 133 label = "Wake on WiFi"; 134 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 135 linux,code = <KEY_WAKEUP>; 136 wakeup-source; 137 }; 138 }; 139 140 tboard_thermistor1: thermal-sensor1 { 141 compatible = "generic-adc-thermal"; 142 #thermal-sensor-cells = <0>; 143 io-channels = <&auxadc 0>; 144 io-channel-names = "sensor-channel"; 145 temperature-lookup-table = < (-5000) 1553 146 0 1488 147 5000 1412 148 10000 1326 149 15000 1232 150 20000 1132 151 25000 1029 152 30000 925 153 35000 823 154 40000 726 155 45000 635 156 50000 552 157 55000 478 158 60000 411 159 65000 353 160 70000 303 161 75000 260 162 80000 222 163 85000 190 164 90000 163 165 95000 140 166 100000 121 167 105000 104 168 110000 90 169 115000 78 170 120000 67 171 125000 59>; 172 }; 173 174 tboard_thermistor2: thermal-sensor2 { 175 compatible = "generic-adc-thermal"; 176 #thermal-sensor-cells = <0>; 177 io-channels = <&auxadc 1>; 178 io-channel-names = "sensor-channel"; 179 temperature-lookup-table = < (-5000) 1553 180 0 1488 181 5000 1412 182 10000 1326 183 15000 1232 184 20000 1132 185 25000 1029 186 30000 925 187 35000 823 188 40000 726 189 45000 635 190 50000 552 191 55000 478 192 60000 411 193 65000 353 194 70000 303 195 75000 260 196 80000 222 197 85000 190 198 90000 163 199 95000 140 200 100000 121 201 105000 104 202 110000 90 203 115000 78 204 120000 67 205 125000 59>; 206 }; 207}; 208 209&afe { 210 memory-region = <&afe_dma_mem>; 211}; 212 213&auxadc { 214 status = "okay"; 215}; 216 217&cci { 218 proc-supply = <&mt6358_vproc12_reg>; 219}; 220 221&cpu0 { 222 proc-supply = <&mt6358_vproc12_reg>; 223}; 224 225&cpu1 { 226 proc-supply = <&mt6358_vproc12_reg>; 227}; 228 229&cpu2 { 230 proc-supply = <&mt6358_vproc12_reg>; 231}; 232 233&cpu3 { 234 proc-supply = <&mt6358_vproc12_reg>; 235}; 236 237&cpu4 { 238 proc-supply = <&mt6358_vproc11_reg>; 239}; 240 241&cpu5 { 242 proc-supply = <&mt6358_vproc11_reg>; 243}; 244 245&cpu6 { 246 proc-supply = <&mt6358_vproc11_reg>; 247}; 248 249&cpu7 { 250 proc-supply = <&mt6358_vproc11_reg>; 251}; 252 253&dsi0 { 254 status = "okay"; 255}; 256 257&gic { 258 mediatek,broken-save-restore-fw; 259}; 260 261&gpu { 262 mali-supply = <&mt6358_vgpu_reg>; 263}; 264 265&i2c0 { 266 pinctrl-names = "default"; 267 pinctrl-0 = <&i2c0_pins>; 268 status = "okay"; 269 clock-frequency = <400000>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272}; 273 274&i2c1 { 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c1_pins>; 277 status = "okay"; 278 clock-frequency = <100000>; 279}; 280 281&i2c3 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c3_pins>; 284 status = "okay"; 285 clock-frequency = <100000>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288}; 289 290&i2c5 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&i2c5_pins>; 293 status = "okay"; 294 clock-frequency = <100000>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297}; 298 299&i2c6 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c6_pins>; 302 status = "okay"; 303 clock-frequency = <100000>; 304}; 305 306&mipi_tx0 { 307 status = "okay"; 308}; 309 310&mmc0 { 311 status = "okay"; 312 pinctrl-names = "default", "state_uhs"; 313 pinctrl-0 = <&mmc0_pins_default>; 314 pinctrl-1 = <&mmc0_pins_uhs>; 315 bus-width = <8>; 316 max-frequency = <200000000>; 317 cap-mmc-highspeed; 318 mmc-hs200-1_8v; 319 mmc-hs400-1_8v; 320 cap-mmc-hw-reset; 321 no-sdio; 322 no-sd; 323 hs400-ds-delay = <0x12814>; 324 vmmc-supply = <&mt6358_vemc_reg>; 325 vqmmc-supply = <&mt6358_vio18_reg>; 326 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 327 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 328 non-removable; 329}; 330 331&mmc1 { 332 status = "okay"; 333 pinctrl-names = "default", "state_uhs"; 334 pinctrl-0 = <&mmc1_pins_default>; 335 pinctrl-1 = <&mmc1_pins_uhs>; 336 vmmc-supply = <&pp3300_alw>; 337 vqmmc-supply = <&pp1800_alw>; 338 mmc-pwrseq = <&wifi_pwrseq>; 339 bus-width = <4>; 340 max-frequency = <200000000>; 341 cap-sd-highspeed; 342 sd-uhs-sdr50; 343 sd-uhs-sdr104; 344 keep-power-in-suspend; 345 wakeup-source; 346 cap-sdio-irq; 347 non-removable; 348 no-mmc; 349 no-sd; 350 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 351 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 355 qca_wifi: qca-wifi@1 { 356 compatible = "qcom,ath10k"; 357 reg = <1>; 358 }; 359}; 360 361&mt6358_vdram2_reg { 362 regulator-always-on; 363}; 364 365&mt6358codec { 366 Avdd-supply = <&mt6358_vaud28_reg>; 367}; 368 369&mt6358regulator { 370 vsys-ldo1-supply = <®_vsys>; 371 vsys-ldo2-supply = <®_vsys>; 372 vsys-ldo3-supply = <®_vsys>; 373 vsys-vcore-supply = <®_vsys>; 374 vsys-vdram1-supply = <®_vsys>; 375 vsys-vgpu-supply = <®_vsys>; 376 vsys-vmodem-supply = <®_vsys>; 377 vsys-vpa-supply = <®_vsys>; 378 vsys-vproc11-supply = <®_vsys>; 379 vsys-vproc12-supply = <®_vsys>; 380 vsys-vs1-supply = <®_vsys>; 381 vsys-vs2-supply = <®_vsys>; 382 vs1-ldo1-supply = <&mt6358_vs1_reg>; 383 vs2-ldo1-supply = <&mt6358_vdram1_reg>; 384 vs2-ldo2-supply = <&mt6358_vs2_reg>; 385 vs2-ldo3-supply = <&mt6358_vs2_reg>; 386 vs2-ldo4-supply = <&mt6358_vs2_reg>; 387}; 388 389&mt6358_vgpu_reg { 390 regulator-max-microvolt = <900000>; 391 392 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 393 regulator-coupled-max-spread = <100000>; 394}; 395 396&mt6358_vsim1_reg { 397 regulator-min-microvolt = <2700000>; 398 regulator-max-microvolt = <2700000>; 399}; 400 401&mt6358_vsim2_reg { 402 regulator-min-microvolt = <2700000>; 403 regulator-max-microvolt = <2700000>; 404}; 405 406&mt6358_vsram_gpu_reg { 407 regulator-min-microvolt = <850000>; 408 regulator-max-microvolt = <1000000>; 409 410 regulator-coupled-with = <&mt6358_vgpu_reg>; 411 regulator-coupled-max-spread = <100000>; 412}; 413 414&pio { 415 aud_pins_default: audio-pins { 416 pins-bus { 417 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 418 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 419 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 420 <PINMUX_GPIO102__FUNC_I2S2_DI>, 421 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 422 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 423 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 424 <PINMUX_GPIO91__FUNC_I2S5_DO>, 425 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 426 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 427 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 428 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 429 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 430 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 431 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 432 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 433 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 434 }; 435 }; 436 437 aud_pins_tdm_out_on: audio-tdmout-on-pins { 438 pins-bus { 439 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 440 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 441 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 442 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 443 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 444 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 445 drive-strength = <6>; 446 }; 447 }; 448 449 aud_pins_tdm_out_off: audio-tdmout-off-pins { 450 pins-bus { 451 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 452 <PINMUX_GPIO170__FUNC_GPIO170>, 453 <PINMUX_GPIO171__FUNC_GPIO171>, 454 <PINMUX_GPIO172__FUNC_GPIO172>, 455 <PINMUX_GPIO173__FUNC_GPIO173>, 456 <PINMUX_GPIO10__FUNC_GPIO10>; 457 input-enable; 458 bias-pull-down; 459 drive-strength = <2>; 460 }; 461 }; 462 463 bt_pins: bt-pins { 464 pins-bt-en { 465 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 466 output-low; 467 }; 468 }; 469 470 ec_ap_int_odl: ec-ap-int-odl-pins { 471 pins-intn { 472 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 473 input-enable; 474 bias-pull-up; 475 }; 476 }; 477 478 h1_int_od_l: h1-int-od-l-pins { 479 pins-intn { 480 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 481 input-enable; 482 }; 483 }; 484 485 i2c0_pins: i2c0-pins { 486 pins-bus { 487 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 488 <PINMUX_GPIO83__FUNC_SCL0>; 489 mediatek,pull-up-adv = <3>; 490 }; 491 }; 492 493 i2c1_pins: i2c1-pins { 494 pins-bus { 495 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 496 <PINMUX_GPIO84__FUNC_SCL1>; 497 mediatek,pull-up-adv = <3>; 498 }; 499 }; 500 501 i2c2_pins: i2c2-pins { 502 pins-bus { 503 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 504 <PINMUX_GPIO104__FUNC_SDA2>; 505 bias-disable; 506 }; 507 }; 508 509 i2c3_pins: i2c3-pins { 510 pins-bus { 511 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 512 <PINMUX_GPIO51__FUNC_SDA3>; 513 mediatek,pull-up-adv = <3>; 514 }; 515 }; 516 517 i2c4_pins: i2c4-pins { 518 pins-bus { 519 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 520 <PINMUX_GPIO106__FUNC_SDA4>; 521 bias-disable; 522 }; 523 }; 524 525 i2c5_pins: i2c5-pins { 526 pins-bus { 527 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 528 <PINMUX_GPIO49__FUNC_SDA5>; 529 mediatek,pull-up-adv = <3>; 530 }; 531 }; 532 533 i2c6_pins: i2c6-pins { 534 pins-bus { 535 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 536 <PINMUX_GPIO12__FUNC_SDA6>; 537 bias-disable; 538 }; 539 }; 540 541 mmc0_pins_default: mmc0-default-pins { 542 pins-cmd-dat { 543 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 544 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 545 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 546 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 547 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 548 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 549 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 550 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 551 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 552 input-enable; 553 drive-strength = <MTK_DRIVE_14mA>; 554 mediatek,pull-up-adv = <01>; 555 }; 556 557 pins-clk { 558 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 559 drive-strength = <MTK_DRIVE_14mA>; 560 mediatek,pull-down-adv = <2>; 561 }; 562 563 pins-rst { 564 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 565 drive-strength = <MTK_DRIVE_14mA>; 566 mediatek,pull-down-adv = <01>; 567 }; 568 }; 569 570 mmc0_pins_uhs: mmc0-pins-uhs { 571 pins-cmd-dat { 572 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 573 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 574 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 575 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 576 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 577 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 578 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 579 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 580 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 581 input-enable; 582 drive-strength = <MTK_DRIVE_14mA>; 583 mediatek,pull-up-adv = <01>; 584 }; 585 586 pins-clk { 587 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 588 drive-strength = <MTK_DRIVE_14mA>; 589 mediatek,pull-down-adv = <2>; 590 }; 591 592 pins-ds { 593 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 594 drive-strength = <MTK_DRIVE_14mA>; 595 mediatek,pull-down-adv = <2>; 596 }; 597 598 pins-rst { 599 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 600 drive-strength = <MTK_DRIVE_14mA>; 601 mediatek,pull-up-adv = <01>; 602 }; 603 }; 604 605 mmc1_pins_default: mmc1-default-pins { 606 pins-cmd-dat { 607 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 608 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 609 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 610 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 611 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 612 input-enable; 613 mediatek,pull-up-adv = <2>; 614 }; 615 616 pins-clk { 617 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 618 input-enable; 619 mediatek,pull-down-adv = <2>; 620 }; 621 }; 622 623 mmc1_pins_uhs: mmc1-uhs-pins { 624 pins-cmd-dat { 625 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 626 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 627 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 628 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 629 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 630 drive-strength = <6>; 631 input-enable; 632 mediatek,pull-up-adv = <2>; 633 }; 634 635 pins-clk { 636 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 637 drive-strength = <8>; 638 mediatek,pull-down-adv = <2>; 639 input-enable; 640 }; 641 }; 642 643 panel_pins_default: panel-pins { 644 pins-panel-reset { 645 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 646 output-low; 647 bias-pull-up; 648 }; 649 }; 650 651 pwm0_pin_default: pwm0-pins { 652 pins1 { 653 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 654 output-high; 655 bias-pull-up; 656 }; 657 pins2 { 658 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 659 }; 660 }; 661 662 scp_pins: scp-pins { 663 pins-scp-uart { 664 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 665 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 666 }; 667 }; 668 669 spi0_pins: spi0-pins { 670 pins-bus { 671 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 672 <PINMUX_GPIO86__FUNC_GPIO86>, 673 <PINMUX_GPIO87__FUNC_SPI0_MO>, 674 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 675 bias-disable; 676 }; 677 }; 678 679 spi1_pins: spi1-pins { 680 pins-bus { 681 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 682 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 683 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 684 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 685 bias-disable; 686 }; 687 }; 688 689 spi2_pins: spi2-pins { 690 pins-bus { 691 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 692 <PINMUX_GPIO1__FUNC_SPI2_MO>, 693 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 694 bias-disable; 695 }; 696 pins-miso { 697 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 698 mediatek,pull-down-adv = <00>; 699 }; 700 }; 701 702 spi3_pins: spi3-pins { 703 pins-bus { 704 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 705 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 706 <PINMUX_GPIO23__FUNC_SPI3_MO>, 707 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 708 bias-disable; 709 }; 710 }; 711 712 spi4_pins: spi4-pins { 713 pins-bus { 714 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 715 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 716 <PINMUX_GPIO19__FUNC_SPI4_MO>, 717 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 718 bias-disable; 719 }; 720 }; 721 722 spi5_pins: spi5-pins { 723 pins-bus { 724 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 725 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 726 <PINMUX_GPIO15__FUNC_SPI5_MO>, 727 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 728 bias-disable; 729 }; 730 }; 731 732 uart0_pins_default: uart0-pins { 733 pins-rx { 734 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 735 input-enable; 736 bias-pull-up; 737 }; 738 pins-tx { 739 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 740 }; 741 }; 742 743 uart1_pins_default: uart1-pins { 744 pins-rx { 745 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 746 input-enable; 747 bias-pull-up; 748 }; 749 pins-tx { 750 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 751 }; 752 pins-rts { 753 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 754 }; 755 pins-cts { 756 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 757 input-enable; 758 }; 759 }; 760 761 uart1_pins_sleep: uart1-sleep-pins { 762 pins-rx { 763 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 764 input-enable; 765 bias-pull-up; 766 }; 767 pins-tx { 768 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 769 }; 770 pins-rts { 771 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 772 }; 773 pins-cts { 774 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 775 input-enable; 776 }; 777 }; 778 779 wifi_pins_pwrseq: wifi-pwr-pins { 780 pins-wifi-enable { 781 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 782 output-low; 783 }; 784 }; 785 786 wifi_pins_wakeup: wifi-wake-pins { 787 pins-wifi-wakeup { 788 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 789 input-enable; 790 }; 791 }; 792}; 793 794&pmic { 795 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>; 796}; 797 798&pwm0 { 799 status = "okay"; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pwm0_pin_default>; 802}; 803 804&scp { 805 status = "okay"; 806 807 firmware-name = "mediatek/mt8183/scp.img"; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&scp_pins>; 810 811 cros-ec-rpmsg { 812 compatible = "google,cros-ec-rpmsg"; 813 mediatek,rpmsg-name = "cros-ec-rpmsg"; 814 }; 815}; 816 817&mfg_async { 818 domain-supply = <&mt6358_vsram_gpu_reg>; 819}; 820 821&mfg { 822 domain-supply = <&mt6358_vgpu_reg>; 823}; 824 825&spi0 { 826 pinctrl-names = "default"; 827 pinctrl-0 = <&spi0_pins>; 828 mediatek,pad-select = <0>; 829 status = "okay"; 830 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 831 832 tpm@0 { 833 compatible = "google,cr50"; 834 reg = <0>; 835 spi-max-frequency = <1000000>; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&h1_int_od_l>; 838 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>; 839 }; 840}; 841 842&spi1 { 843 pinctrl-names = "default"; 844 pinctrl-0 = <&spi1_pins>; 845 mediatek,pad-select = <0>; 846 status = "okay"; 847 848 w25q64dw: flash@0 { 849 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 850 reg = <0>; 851 spi-max-frequency = <25000000>; 852 }; 853}; 854 855&spi2 { 856 pinctrl-names = "default"; 857 pinctrl-0 = <&spi2_pins>; 858 mediatek,pad-select = <0>; 859 status = "okay"; 860 861 cros_ec: cros-ec@0 { 862 compatible = "google,cros-ec-spi"; 863 reg = <0>; 864 spi-max-frequency = <3000000>; 865 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&ec_ap_int_odl>; 868 wakeup-source; 869 870 i2c_tunnel: i2c-tunnel { 871 compatible = "google,cros-ec-i2c-tunnel"; 872 google,remote-bus = <1>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 }; 876 877 usbc_extcon: extcon0 { 878 compatible = "google,extcon-usbc-cros-ec"; 879 google,usb-port-id = <0>; 880 }; 881 882 typec { 883 compatible = "google,cros-ec-typec"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 usb_c0: connector@0 { 888 compatible = "usb-c-connector"; 889 reg = <0>; 890 power-role = "dual"; 891 data-role = "host"; 892 try-power-role = "sink"; 893 }; 894 }; 895 }; 896}; 897 898&spi3 { 899 pinctrl-names = "default"; 900 pinctrl-0 = <&spi3_pins>; 901 mediatek,pad-select = <0>; 902 status = "disabled"; 903}; 904 905&spi4 { 906 pinctrl-names = "default"; 907 pinctrl-0 = <&spi4_pins>; 908 mediatek,pad-select = <0>; 909 status = "disabled"; 910}; 911 912&spi5 { 913 pinctrl-names = "default"; 914 pinctrl-0 = <&spi5_pins>; 915 mediatek,pad-select = <0>; 916 status = "disabled"; 917}; 918 919&ssusb { 920 dr_mode = "host"; 921 wakeup-source; 922 vusb33-supply = <&mt6358_vusb_reg>; 923 status = "okay"; 924}; 925 926&thermal_zones { 927 tboard1-thermal { 928 polling-delay = <1000>; /* milliseconds */ 929 polling-delay-passive = <0>; /* milliseconds */ 930 thermal-sensors = <&tboard_thermistor1>; 931 }; 932 933 tboard2-thermal { 934 polling-delay = <1000>; /* milliseconds */ 935 polling-delay-passive = <0>; /* milliseconds */ 936 thermal-sensors = <&tboard_thermistor2>; 937 }; 938}; 939 940&u3phy { 941 status = "okay"; 942}; 943 944&uart0 { 945 pinctrl-names = "default"; 946 pinctrl-0 = <&uart0_pins_default>; 947 status = "okay"; 948}; 949 950&uart1 { 951 pinctrl-names = "default", "sleep"; 952 pinctrl-0 = <&uart1_pins_default>; 953 pinctrl-1 = <&uart1_pins_sleep>; 954 status = "okay"; 955 /delete-property/ interrupts; 956 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 957 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 958 959 bluetooth: bluetooth { 960 pinctrl-names = "default"; 961 pinctrl-0 = <&bt_pins>; 962 status = "okay"; 963 compatible = "qcom,qca6174-bt"; 964 enable-gpios = <&pio 120 0>; 965 clocks = <&clk32k>; 966 firmware-name = "nvm_00440302_i2s.bin"; 967 }; 968}; 969 970&usb_host { 971 #address-cells = <1>; 972 #size-cells = <0>; 973 vusb33-supply = <&mt6358_vusb_reg>; 974 status = "okay"; 975 976 hub@1 { 977 compatible = "usb5e3,610"; 978 reg = <1>; 979 }; 980}; 981 982#include <arm/cros-ec-sbs.dtsi> 983