1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <®_vsys>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 vin-supply = <&pp1800_alw>; 53 }; 54 55 pp1800_alw: regulator5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "pp1800_alw"; 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 vin-supply = <®_vsys>; 63 }; 64 65 pp3300_alw: regulator6 { 66 compatible = "regulator-fixed"; 67 regulator-name = "pp3300_alw"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <®_vsys>; 73 }; 74 75 /* system wide semi-regulated power rail from charger */ 76 reg_vsys: regulator-vsys { 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys"; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 reserved_memory: reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 scp_mem_reserved: memory@50000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0 0x50000000 0 0x2900000>; 91 no-map; 92 }; 93 }; 94 95 sound: mt8183-sound { 96 mediatek,platform = <&afe>; 97 pinctrl-names = "default", 98 "aud_tdm_out_on", 99 "aud_tdm_out_off"; 100 pinctrl-0 = <&aud_pins_default>; 101 pinctrl-1 = <&aud_pins_tdm_out_on>; 102 pinctrl-2 = <&aud_pins_tdm_out_off>; 103 status = "okay"; 104 }; 105 106 btsco: bt-sco { 107 compatible = "linux,bt-sco"; 108 }; 109 110 wifi_pwrseq: wifi-pwrseq { 111 compatible = "mmc-pwrseq-simple"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&wifi_pins_pwrseq>; 114 115 /* Toggle WIFI_ENABLE to reset the chip. */ 116 reset-gpios = <&pio 119 1>; 117 }; 118 119 wifi_wakeup: wifi-wakeup { 120 compatible = "gpio-keys"; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&wifi_pins_wakeup>; 123 124 wifi_wakeup_event: event-wowlan { 125 label = "Wake on WiFi"; 126 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 127 linux,code = <KEY_WAKEUP>; 128 wakeup-source; 129 }; 130 }; 131 132 tboard_thermistor1: thermal-sensor1 { 133 compatible = "generic-adc-thermal"; 134 #thermal-sensor-cells = <0>; 135 io-channels = <&auxadc 0>; 136 io-channel-names = "sensor-channel"; 137 temperature-lookup-table = < (-5000) 1553 138 0 1488 139 5000 1412 140 10000 1326 141 15000 1232 142 20000 1132 143 25000 1029 144 30000 925 145 35000 823 146 40000 726 147 45000 635 148 50000 552 149 55000 478 150 60000 411 151 65000 353 152 70000 303 153 75000 260 154 80000 222 155 85000 190 156 90000 163 157 95000 140 158 100000 121 159 105000 104 160 110000 90 161 115000 78 162 120000 67 163 125000 59>; 164 }; 165 166 tboard_thermistor2: thermal-sensor2 { 167 compatible = "generic-adc-thermal"; 168 #thermal-sensor-cells = <0>; 169 io-channels = <&auxadc 1>; 170 io-channel-names = "sensor-channel"; 171 temperature-lookup-table = < (-5000) 1553 172 0 1488 173 5000 1412 174 10000 1326 175 15000 1232 176 20000 1132 177 25000 1029 178 30000 925 179 35000 823 180 40000 726 181 45000 635 182 50000 552 183 55000 478 184 60000 411 185 65000 353 186 70000 303 187 75000 260 188 80000 222 189 85000 190 190 90000 163 191 95000 140 192 100000 121 193 105000 104 194 110000 90 195 115000 78 196 120000 67 197 125000 59>; 198 }; 199}; 200 201&auxadc { 202 status = "okay"; 203}; 204 205&cci { 206 proc-supply = <&mt6358_vproc12_reg>; 207}; 208 209&cpu0 { 210 proc-supply = <&mt6358_vproc12_reg>; 211}; 212 213&cpu1 { 214 proc-supply = <&mt6358_vproc12_reg>; 215}; 216 217&cpu2 { 218 proc-supply = <&mt6358_vproc12_reg>; 219}; 220 221&cpu3 { 222 proc-supply = <&mt6358_vproc12_reg>; 223}; 224 225&cpu4 { 226 proc-supply = <&mt6358_vproc11_reg>; 227}; 228 229&cpu5 { 230 proc-supply = <&mt6358_vproc11_reg>; 231}; 232 233&cpu6 { 234 proc-supply = <&mt6358_vproc11_reg>; 235}; 236 237&cpu7 { 238 proc-supply = <&mt6358_vproc11_reg>; 239}; 240 241&dsi0 { 242 status = "okay"; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 panel: panel@0 { 246 /* compatible will be set in board dts */ 247 reg = <0>; 248 enable-gpios = <&pio 45 0>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&panel_pins_default>; 251 avdd-supply = <&ppvarn_lcd>; 252 avee-supply = <&ppvarp_lcd>; 253 pp1800-supply = <&pp1800_lcd>; 254 backlight = <&backlight_lcd0>; 255 rotation = <270>; 256 port { 257 panel_in: endpoint { 258 remote-endpoint = <&dsi_out>; 259 }; 260 }; 261 }; 262 263 ports { 264 port { 265 dsi_out: endpoint { 266 remote-endpoint = <&panel_in>; 267 }; 268 }; 269 }; 270}; 271 272&dpi0 { 273 /* TODO Re-enable after DP to Type-C port muxing can be described */ 274 status = "disabled"; 275}; 276 277&gic { 278 mediatek,broken-save-restore-fw; 279}; 280 281&gpu { 282 mali-supply = <&mt6358_vgpu_reg>; 283}; 284 285&i2c0 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c0_pins>; 288 status = "okay"; 289 clock-frequency = <400000>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292}; 293 294&i2c1 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c1_pins>; 297 status = "okay"; 298 clock-frequency = <100000>; 299}; 300 301&i2c3 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c3_pins>; 304 status = "okay"; 305 clock-frequency = <100000>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308}; 309 310&i2c5 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c5_pins>; 313 status = "okay"; 314 clock-frequency = <100000>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317}; 318 319&i2c6 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c6_pins>; 322 status = "okay"; 323 clock-frequency = <100000>; 324}; 325 326&mipi_tx0 { 327 status = "okay"; 328}; 329 330&mmc0 { 331 status = "okay"; 332 pinctrl-names = "default", "state_uhs"; 333 pinctrl-0 = <&mmc0_pins_default>; 334 pinctrl-1 = <&mmc0_pins_uhs>; 335 bus-width = <8>; 336 max-frequency = <200000000>; 337 cap-mmc-highspeed; 338 mmc-hs200-1_8v; 339 mmc-hs400-1_8v; 340 cap-mmc-hw-reset; 341 no-sdio; 342 no-sd; 343 hs400-ds-delay = <0x12814>; 344 vmmc-supply = <&mt6358_vemc_reg>; 345 vqmmc-supply = <&mt6358_vio18_reg>; 346 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 347 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 348 non-removable; 349}; 350 351&mmc1 { 352 status = "okay"; 353 pinctrl-names = "default", "state_uhs"; 354 pinctrl-0 = <&mmc1_pins_default>; 355 pinctrl-1 = <&mmc1_pins_uhs>; 356 vmmc-supply = <&pp3300_alw>; 357 vqmmc-supply = <&pp1800_alw>; 358 mmc-pwrseq = <&wifi_pwrseq>; 359 bus-width = <4>; 360 max-frequency = <200000000>; 361 cap-sd-highspeed; 362 sd-uhs-sdr50; 363 sd-uhs-sdr104; 364 keep-power-in-suspend; 365 wakeup-source; 366 cap-sdio-irq; 367 non-removable; 368 no-mmc; 369 no-sd; 370 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 371 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 qca_wifi: qca-wifi@1 { 376 compatible = "qcom,ath10k"; 377 reg = <1>; 378 }; 379}; 380 381&mt6358_vdram2_reg { 382 regulator-always-on; 383}; 384 385&mt6358codec { 386 Avdd-supply = <&mt6358_vaud28_reg>; 387}; 388 389&mt6358regulator { 390 vsys-ldo1-supply = <®_vsys>; 391 vsys-ldo2-supply = <®_vsys>; 392 vsys-ldo3-supply = <®_vsys>; 393 vsys-vcore-supply = <®_vsys>; 394 vsys-vdram1-supply = <®_vsys>; 395 vsys-vgpu-supply = <®_vsys>; 396 vsys-vmodem-supply = <®_vsys>; 397 vsys-vpa-supply = <®_vsys>; 398 vsys-vproc11-supply = <®_vsys>; 399 vsys-vproc12-supply = <®_vsys>; 400 vsys-vs1-supply = <®_vsys>; 401 vsys-vs2-supply = <®_vsys>; 402 vs1-ldo1-supply = <&mt6358_vs1_reg>; 403 vs2-ldo1-supply = <&mt6358_vdram1_reg>; 404 vs2-ldo2-supply = <&mt6358_vs2_reg>; 405 vs2-ldo3-supply = <&mt6358_vs2_reg>; 406 vs2-ldo4-supply = <&mt6358_vs2_reg>; 407}; 408 409&mt6358_vgpu_reg { 410 regulator-max-microvolt = <900000>; 411 412 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 413 regulator-coupled-max-spread = <100000>; 414}; 415 416&mt6358_vsim1_reg { 417 regulator-min-microvolt = <2700000>; 418 regulator-max-microvolt = <2700000>; 419}; 420 421&mt6358_vsim2_reg { 422 regulator-min-microvolt = <2700000>; 423 regulator-max-microvolt = <2700000>; 424}; 425 426&mt6358_vsram_gpu_reg { 427 regulator-min-microvolt = <850000>; 428 regulator-max-microvolt = <1000000>; 429 430 regulator-coupled-with = <&mt6358_vgpu_reg>; 431 regulator-coupled-max-spread = <100000>; 432}; 433 434&pio { 435 aud_pins_default: audiopins { 436 pins-bus { 437 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 438 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 439 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 440 <PINMUX_GPIO102__FUNC_I2S2_DI>, 441 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 442 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 443 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 444 <PINMUX_GPIO91__FUNC_I2S5_DO>, 445 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 446 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 447 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 448 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 449 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 450 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 451 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 452 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 453 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 454 }; 455 }; 456 457 aud_pins_tdm_out_on: audiotdmouton { 458 pins-bus { 459 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 460 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 461 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 462 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 463 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 464 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 465 drive-strength = <6>; 466 }; 467 }; 468 469 aud_pins_tdm_out_off: audiotdmoutoff { 470 pins-bus { 471 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 472 <PINMUX_GPIO170__FUNC_GPIO170>, 473 <PINMUX_GPIO171__FUNC_GPIO171>, 474 <PINMUX_GPIO172__FUNC_GPIO172>, 475 <PINMUX_GPIO173__FUNC_GPIO173>, 476 <PINMUX_GPIO10__FUNC_GPIO10>; 477 input-enable; 478 bias-pull-down; 479 drive-strength = <2>; 480 }; 481 }; 482 483 bt_pins: bt-pins { 484 pins-bt-en { 485 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 486 output-low; 487 }; 488 }; 489 490 ec_ap_int_odl: ec-ap-int-odl { 491 pins1 { 492 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 493 input-enable; 494 bias-pull-up; 495 }; 496 }; 497 498 h1_int_od_l: h1-int-od-l { 499 pins1 { 500 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 501 input-enable; 502 }; 503 }; 504 505 i2c0_pins: i2c0 { 506 pins-bus { 507 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 508 <PINMUX_GPIO83__FUNC_SCL0>; 509 mediatek,pull-up-adv = <3>; 510 }; 511 }; 512 513 i2c1_pins: i2c1 { 514 pins-bus { 515 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 516 <PINMUX_GPIO84__FUNC_SCL1>; 517 mediatek,pull-up-adv = <3>; 518 }; 519 }; 520 521 i2c2_pins: i2c2 { 522 pins-bus { 523 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 524 <PINMUX_GPIO104__FUNC_SDA2>; 525 bias-disable; 526 }; 527 }; 528 529 i2c3_pins: i2c3 { 530 pins-bus { 531 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 532 <PINMUX_GPIO51__FUNC_SDA3>; 533 mediatek,pull-up-adv = <3>; 534 }; 535 }; 536 537 i2c4_pins: i2c4 { 538 pins-bus { 539 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 540 <PINMUX_GPIO106__FUNC_SDA4>; 541 bias-disable; 542 }; 543 }; 544 545 i2c5_pins: i2c5 { 546 pins-bus { 547 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 548 <PINMUX_GPIO49__FUNC_SDA5>; 549 mediatek,pull-up-adv = <3>; 550 }; 551 }; 552 553 i2c6_pins: i2c6 { 554 pins-bus { 555 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 556 <PINMUX_GPIO12__FUNC_SDA6>; 557 bias-disable; 558 }; 559 }; 560 561 mmc0_pins_default: mmc0-pins-default { 562 pins-cmd-dat { 563 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 564 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 565 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 566 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 567 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 568 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 569 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 570 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 571 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 572 input-enable; 573 drive-strength = <MTK_DRIVE_14mA>; 574 mediatek,pull-up-adv = <01>; 575 }; 576 577 pins-clk { 578 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 579 drive-strength = <MTK_DRIVE_14mA>; 580 mediatek,pull-down-adv = <10>; 581 }; 582 583 pins-rst { 584 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 585 drive-strength = <MTK_DRIVE_14mA>; 586 mediatek,pull-down-adv = <01>; 587 }; 588 }; 589 590 mmc0_pins_uhs: mmc0-pins-uhs { 591 pins-cmd-dat { 592 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 593 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 594 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 595 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 596 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 597 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 598 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 599 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 600 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 601 input-enable; 602 drive-strength = <MTK_DRIVE_14mA>; 603 mediatek,pull-up-adv = <01>; 604 }; 605 606 pins-clk { 607 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 608 drive-strength = <MTK_DRIVE_14mA>; 609 mediatek,pull-down-adv = <10>; 610 }; 611 612 pins-ds { 613 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 614 drive-strength = <MTK_DRIVE_14mA>; 615 mediatek,pull-down-adv = <10>; 616 }; 617 618 pins-rst { 619 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 620 drive-strength = <MTK_DRIVE_14mA>; 621 mediatek,pull-up-adv = <01>; 622 }; 623 }; 624 625 mmc1_pins_default: mmc1-pins-default { 626 pins-cmd-dat { 627 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 628 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 629 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 630 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 631 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 632 input-enable; 633 mediatek,pull-up-adv = <10>; 634 }; 635 636 pins-clk { 637 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 638 input-enable; 639 mediatek,pull-down-adv = <10>; 640 }; 641 }; 642 643 mmc1_pins_uhs: mmc1-pins-uhs { 644 pins-cmd-dat { 645 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 646 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 647 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 648 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 649 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 650 drive-strength = <6>; 651 input-enable; 652 mediatek,pull-up-adv = <10>; 653 }; 654 655 pins-clk { 656 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 657 drive-strength = <8>; 658 mediatek,pull-down-adv = <10>; 659 input-enable; 660 }; 661 }; 662 663 panel_pins_default: panel-pins-default { 664 panel-reset { 665 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 666 output-low; 667 bias-pull-up; 668 }; 669 }; 670 671 pwm0_pin_default: pwm0-pin-default { 672 pins1 { 673 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 674 output-high; 675 bias-pull-up; 676 }; 677 pins2 { 678 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 679 }; 680 }; 681 682 scp_pins: scp { 683 pins-scp-uart { 684 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 685 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 686 }; 687 }; 688 689 spi0_pins: spi0 { 690 pins-spi { 691 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 692 <PINMUX_GPIO86__FUNC_GPIO86>, 693 <PINMUX_GPIO87__FUNC_SPI0_MO>, 694 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 695 bias-disable; 696 }; 697 }; 698 699 spi1_pins: spi1 { 700 pins-spi { 701 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 702 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 703 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 704 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 705 bias-disable; 706 }; 707 }; 708 709 spi2_pins: spi2 { 710 pins-spi { 711 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 712 <PINMUX_GPIO1__FUNC_SPI2_MO>, 713 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 714 bias-disable; 715 }; 716 pins-spi-mi { 717 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 718 mediatek,pull-down-adv = <00>; 719 }; 720 }; 721 722 spi3_pins: spi3 { 723 pins-spi { 724 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 725 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 726 <PINMUX_GPIO23__FUNC_SPI3_MO>, 727 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 728 bias-disable; 729 }; 730 }; 731 732 spi4_pins: spi4 { 733 pins-spi { 734 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 735 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 736 <PINMUX_GPIO19__FUNC_SPI4_MO>, 737 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 738 bias-disable; 739 }; 740 }; 741 742 spi5_pins: spi5 { 743 pins-spi { 744 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 745 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 746 <PINMUX_GPIO15__FUNC_SPI5_MO>, 747 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 748 bias-disable; 749 }; 750 }; 751 752 uart0_pins_default: uart0-pins-default { 753 pins-rx { 754 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 755 input-enable; 756 bias-pull-up; 757 }; 758 pins-tx { 759 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 760 }; 761 }; 762 763 uart1_pins_default: uart1-pins-default { 764 pins-rx { 765 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 766 input-enable; 767 bias-pull-up; 768 }; 769 pins-tx { 770 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 771 }; 772 pins-rts { 773 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 774 }; 775 pins-cts { 776 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 777 input-enable; 778 }; 779 }; 780 781 uart1_pins_sleep: uart1-pins-sleep { 782 pins-rx { 783 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 784 input-enable; 785 bias-pull-up; 786 }; 787 pins-tx { 788 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 789 }; 790 pins-rts { 791 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 792 }; 793 pins-cts { 794 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 795 input-enable; 796 }; 797 }; 798 799 wifi_pins_pwrseq: wifi-pins-pwrseq { 800 pins-wifi-enable { 801 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 802 output-low; 803 }; 804 }; 805 806 wifi_pins_wakeup: wifi-pins-wakeup { 807 pins-wifi-wakeup { 808 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 809 input-enable; 810 }; 811 }; 812}; 813 814&pmic { 815 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>; 816}; 817 818&pwm0 { 819 status = "okay"; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&pwm0_pin_default>; 822}; 823 824&scp { 825 status = "okay"; 826 827 firmware-name = "mediatek/mt8183/scp.img"; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&scp_pins>; 830 831 cros-ec-rpmsg { 832 compatible = "google,cros-ec-rpmsg"; 833 mediatek,rpmsg-name = "cros-ec-rpmsg"; 834 }; 835}; 836 837&mfg_async { 838 domain-supply = <&mt6358_vsram_gpu_reg>; 839}; 840 841&mfg { 842 domain-supply = <&mt6358_vgpu_reg>; 843}; 844 845&spi0 { 846 pinctrl-names = "default"; 847 pinctrl-0 = <&spi0_pins>; 848 mediatek,pad-select = <0>; 849 status = "okay"; 850 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 851 852 tpm@0 { 853 compatible = "google,cr50"; 854 reg = <0>; 855 spi-max-frequency = <1000000>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&h1_int_od_l>; 858 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>; 859 }; 860}; 861 862&spi1 { 863 pinctrl-names = "default"; 864 pinctrl-0 = <&spi1_pins>; 865 mediatek,pad-select = <0>; 866 status = "okay"; 867 868 w25q64dw: flash@0 { 869 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 870 reg = <0>; 871 spi-max-frequency = <25000000>; 872 }; 873}; 874 875&spi2 { 876 pinctrl-names = "default"; 877 pinctrl-0 = <&spi2_pins>; 878 mediatek,pad-select = <0>; 879 status = "okay"; 880 881 cros_ec: cros-ec@0 { 882 compatible = "google,cros-ec-spi"; 883 reg = <0>; 884 spi-max-frequency = <3000000>; 885 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&ec_ap_int_odl>; 888 wakeup-source; 889 890 i2c_tunnel: i2c-tunnel { 891 compatible = "google,cros-ec-i2c-tunnel"; 892 google,remote-bus = <1>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 }; 896 897 usbc_extcon: extcon0 { 898 compatible = "google,extcon-usbc-cros-ec"; 899 google,usb-port-id = <0>; 900 }; 901 902 typec { 903 compatible = "google,cros-ec-typec"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 usb_c0: connector@0 { 908 compatible = "usb-c-connector"; 909 reg = <0>; 910 power-role = "dual"; 911 data-role = "host"; 912 try-power-role = "sink"; 913 }; 914 }; 915 }; 916}; 917 918&spi3 { 919 pinctrl-names = "default"; 920 pinctrl-0 = <&spi3_pins>; 921 mediatek,pad-select = <0>; 922 status = "disabled"; 923}; 924 925&spi4 { 926 pinctrl-names = "default"; 927 pinctrl-0 = <&spi4_pins>; 928 mediatek,pad-select = <0>; 929 status = "disabled"; 930}; 931 932&spi5 { 933 pinctrl-names = "default"; 934 pinctrl-0 = <&spi5_pins>; 935 mediatek,pad-select = <0>; 936 status = "disabled"; 937}; 938 939&ssusb { 940 dr_mode = "host"; 941 wakeup-source; 942 vusb33-supply = <&mt6358_vusb_reg>; 943 status = "okay"; 944}; 945 946&thermal_zones { 947 tboard1 { 948 polling-delay = <1000>; /* milliseconds */ 949 polling-delay-passive = <0>; /* milliseconds */ 950 thermal-sensors = <&tboard_thermistor1>; 951 }; 952 953 tboard2 { 954 polling-delay = <1000>; /* milliseconds */ 955 polling-delay-passive = <0>; /* milliseconds */ 956 thermal-sensors = <&tboard_thermistor2>; 957 }; 958}; 959 960&u3phy { 961 status = "okay"; 962}; 963 964&uart0 { 965 pinctrl-names = "default"; 966 pinctrl-0 = <&uart0_pins_default>; 967 status = "okay"; 968}; 969 970&uart1 { 971 pinctrl-names = "default", "sleep"; 972 pinctrl-0 = <&uart1_pins_default>; 973 pinctrl-1 = <&uart1_pins_sleep>; 974 status = "okay"; 975 /delete-property/ interrupts; 976 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 977 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 978 979 bluetooth: bluetooth { 980 pinctrl-names = "default"; 981 pinctrl-0 = <&bt_pins>; 982 status = "okay"; 983 compatible = "qcom,qca6174-bt"; 984 enable-gpios = <&pio 120 0>; 985 clocks = <&clk32k>; 986 firmware-name = "nvm_00440302_i2s.bin"; 987 }; 988}; 989 990&usb_host { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 vusb33-supply = <&mt6358_vusb_reg>; 994 status = "okay"; 995 996 hub@1 { 997 compatible = "usb5e3,610"; 998 reg = <1>; 999 }; 1000}; 1001 1002#include <arm/cros-ec-sbs.dtsi> 1003