1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <®_vsys>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 vin-supply = <&pp1800_alw>; 53 }; 54 55 pp1800_alw: regulator5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "pp1800_alw"; 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 vin-supply = <®_vsys>; 63 }; 64 65 pp3300_alw: regulator6 { 66 compatible = "regulator-fixed"; 67 regulator-name = "pp3300_alw"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <®_vsys>; 73 }; 74 75 /* system wide semi-regulated power rail from charger */ 76 reg_vsys: regulator-vsys { 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys"; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 reserved_memory: reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 afe_dma_mem: audio-dma-pool { 89 compatible = "shared-dma-pool"; 90 size = <0 0x100000>; 91 alignment = <0 0x10>; 92 no-map; 93 }; 94 95 scp_mem_reserved: memory@50000000 { 96 compatible = "shared-dma-pool"; 97 reg = <0 0x50000000 0 0x2900000>; 98 no-map; 99 }; 100 }; 101 102 sound: mt8183-sound { 103 mediatek,platform = <&afe>; 104 pinctrl-names = "default", 105 "aud_tdm_out_on", 106 "aud_tdm_out_off"; 107 pinctrl-0 = <&aud_pins_default>; 108 pinctrl-1 = <&aud_pins_tdm_out_on>; 109 pinctrl-2 = <&aud_pins_tdm_out_off>; 110 status = "okay"; 111 }; 112 113 btsco: bt-sco { 114 compatible = "linux,bt-sco"; 115 #sound-dai-cells = <0>; 116 }; 117 118 wifi_pwrseq: wifi-pwrseq { 119 compatible = "mmc-pwrseq-simple"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&wifi_pins_pwrseq>; 122 123 /* Toggle WIFI_ENABLE to reset the chip. */ 124 reset-gpios = <&pio 119 1>; 125 }; 126 127 wifi_wakeup: wifi-wakeup { 128 compatible = "gpio-keys"; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&wifi_pins_wakeup>; 131 132 wifi_wakeup_event: event-wowlan { 133 label = "Wake on WiFi"; 134 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 135 linux,code = <KEY_WAKEUP>; 136 wakeup-source; 137 }; 138 }; 139 140 tboard_thermistor1: thermal-sensor1 { 141 compatible = "generic-adc-thermal"; 142 #thermal-sensor-cells = <0>; 143 io-channels = <&auxadc 0>; 144 io-channel-names = "sensor-channel"; 145 temperature-lookup-table = < (-5000) 1553 146 0 1488 147 5000 1412 148 10000 1326 149 15000 1232 150 20000 1132 151 25000 1029 152 30000 925 153 35000 823 154 40000 726 155 45000 635 156 50000 552 157 55000 478 158 60000 411 159 65000 353 160 70000 303 161 75000 260 162 80000 222 163 85000 190 164 90000 163 165 95000 140 166 100000 121 167 105000 104 168 110000 90 169 115000 78 170 120000 67 171 125000 59>; 172 }; 173 174 tboard_thermistor2: thermal-sensor2 { 175 compatible = "generic-adc-thermal"; 176 #thermal-sensor-cells = <0>; 177 io-channels = <&auxadc 1>; 178 io-channel-names = "sensor-channel"; 179 temperature-lookup-table = < (-5000) 1553 180 0 1488 181 5000 1412 182 10000 1326 183 15000 1232 184 20000 1132 185 25000 1029 186 30000 925 187 35000 823 188 40000 726 189 45000 635 190 50000 552 191 55000 478 192 60000 411 193 65000 353 194 70000 303 195 75000 260 196 80000 222 197 85000 190 198 90000 163 199 95000 140 200 100000 121 201 105000 104 202 110000 90 203 115000 78 204 120000 67 205 125000 59>; 206 }; 207}; 208 209&afe { 210 memory-region = <&afe_dma_mem>; 211}; 212 213&auxadc { 214 status = "okay"; 215}; 216 217&cci { 218 proc-supply = <&mt6358_vproc12_reg>; 219}; 220 221&cpu0 { 222 proc-supply = <&mt6358_vproc12_reg>; 223}; 224 225&cpu1 { 226 proc-supply = <&mt6358_vproc12_reg>; 227}; 228 229&cpu2 { 230 proc-supply = <&mt6358_vproc12_reg>; 231}; 232 233&cpu3 { 234 proc-supply = <&mt6358_vproc12_reg>; 235}; 236 237&cpu4 { 238 proc-supply = <&mt6358_vproc11_reg>; 239}; 240 241&cpu5 { 242 proc-supply = <&mt6358_vproc11_reg>; 243}; 244 245&cpu6 { 246 proc-supply = <&mt6358_vproc11_reg>; 247}; 248 249&cpu7 { 250 proc-supply = <&mt6358_vproc11_reg>; 251}; 252 253&dsi0 { 254 status = "okay"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 panel: panel@0 { 258 /* compatible will be set in board dts */ 259 reg = <0>; 260 enable-gpios = <&pio 45 0>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&panel_pins_default>; 263 avdd-supply = <&ppvarn_lcd>; 264 avee-supply = <&ppvarp_lcd>; 265 pp1800-supply = <&pp1800_lcd>; 266 backlight = <&backlight_lcd0>; 267 rotation = <270>; 268 port { 269 panel_in: endpoint { 270 remote-endpoint = <&dsi_out>; 271 }; 272 }; 273 }; 274}; 275 276&dsi_out { 277 remote-endpoint = <&panel_in>; 278}; 279 280&gic { 281 mediatek,broken-save-restore-fw; 282}; 283 284&gpu { 285 mali-supply = <&mt6358_vgpu_reg>; 286}; 287 288&i2c0 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&i2c0_pins>; 291 status = "okay"; 292 clock-frequency = <400000>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295}; 296 297&i2c1 { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c1_pins>; 300 status = "okay"; 301 clock-frequency = <100000>; 302}; 303 304&i2c3 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c3_pins>; 307 status = "okay"; 308 clock-frequency = <100000>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311}; 312 313&i2c5 { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&i2c5_pins>; 316 status = "okay"; 317 clock-frequency = <100000>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320}; 321 322&i2c6 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&i2c6_pins>; 325 status = "okay"; 326 clock-frequency = <100000>; 327}; 328 329&mipi_tx0 { 330 status = "okay"; 331}; 332 333&mmc0 { 334 status = "okay"; 335 pinctrl-names = "default", "state_uhs"; 336 pinctrl-0 = <&mmc0_pins_default>; 337 pinctrl-1 = <&mmc0_pins_uhs>; 338 bus-width = <8>; 339 max-frequency = <200000000>; 340 cap-mmc-highspeed; 341 mmc-hs200-1_8v; 342 mmc-hs400-1_8v; 343 cap-mmc-hw-reset; 344 no-sdio; 345 no-sd; 346 hs400-ds-delay = <0x12814>; 347 vmmc-supply = <&mt6358_vemc_reg>; 348 vqmmc-supply = <&mt6358_vio18_reg>; 349 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 350 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 351 non-removable; 352}; 353 354&mmc1 { 355 status = "okay"; 356 pinctrl-names = "default", "state_uhs"; 357 pinctrl-0 = <&mmc1_pins_default>; 358 pinctrl-1 = <&mmc1_pins_uhs>; 359 vmmc-supply = <&pp3300_alw>; 360 vqmmc-supply = <&pp1800_alw>; 361 mmc-pwrseq = <&wifi_pwrseq>; 362 bus-width = <4>; 363 max-frequency = <200000000>; 364 cap-sd-highspeed; 365 sd-uhs-sdr50; 366 sd-uhs-sdr104; 367 keep-power-in-suspend; 368 wakeup-source; 369 cap-sdio-irq; 370 non-removable; 371 no-mmc; 372 no-sd; 373 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 374 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 qca_wifi: qca-wifi@1 { 379 compatible = "qcom,ath10k"; 380 reg = <1>; 381 }; 382}; 383 384&mt6358_vdram2_reg { 385 regulator-always-on; 386}; 387 388&mt6358codec { 389 Avdd-supply = <&mt6358_vaud28_reg>; 390}; 391 392&mt6358regulator { 393 vsys-ldo1-supply = <®_vsys>; 394 vsys-ldo2-supply = <®_vsys>; 395 vsys-ldo3-supply = <®_vsys>; 396 vsys-vcore-supply = <®_vsys>; 397 vsys-vdram1-supply = <®_vsys>; 398 vsys-vgpu-supply = <®_vsys>; 399 vsys-vmodem-supply = <®_vsys>; 400 vsys-vpa-supply = <®_vsys>; 401 vsys-vproc11-supply = <®_vsys>; 402 vsys-vproc12-supply = <®_vsys>; 403 vsys-vs1-supply = <®_vsys>; 404 vsys-vs2-supply = <®_vsys>; 405 vs1-ldo1-supply = <&mt6358_vs1_reg>; 406 vs2-ldo1-supply = <&mt6358_vdram1_reg>; 407 vs2-ldo2-supply = <&mt6358_vs2_reg>; 408 vs2-ldo3-supply = <&mt6358_vs2_reg>; 409 vs2-ldo4-supply = <&mt6358_vs2_reg>; 410}; 411 412&mt6358_vgpu_reg { 413 regulator-max-microvolt = <900000>; 414 415 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 416 regulator-coupled-max-spread = <100000>; 417}; 418 419&mt6358_vsim1_reg { 420 regulator-min-microvolt = <2700000>; 421 regulator-max-microvolt = <2700000>; 422}; 423 424&mt6358_vsim2_reg { 425 regulator-min-microvolt = <2700000>; 426 regulator-max-microvolt = <2700000>; 427}; 428 429&mt6358_vsram_gpu_reg { 430 regulator-min-microvolt = <850000>; 431 regulator-max-microvolt = <1000000>; 432 433 regulator-coupled-with = <&mt6358_vgpu_reg>; 434 regulator-coupled-max-spread = <100000>; 435}; 436 437&pio { 438 aud_pins_default: audiopins { 439 pins-bus { 440 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 441 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 442 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 443 <PINMUX_GPIO102__FUNC_I2S2_DI>, 444 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 445 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 446 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 447 <PINMUX_GPIO91__FUNC_I2S5_DO>, 448 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 449 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 450 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 451 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 452 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 453 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 454 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 455 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 456 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 457 }; 458 }; 459 460 aud_pins_tdm_out_on: audiotdmouton { 461 pins-bus { 462 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 463 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 464 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 465 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 466 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 467 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 468 drive-strength = <6>; 469 }; 470 }; 471 472 aud_pins_tdm_out_off: audiotdmoutoff { 473 pins-bus { 474 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 475 <PINMUX_GPIO170__FUNC_GPIO170>, 476 <PINMUX_GPIO171__FUNC_GPIO171>, 477 <PINMUX_GPIO172__FUNC_GPIO172>, 478 <PINMUX_GPIO173__FUNC_GPIO173>, 479 <PINMUX_GPIO10__FUNC_GPIO10>; 480 input-enable; 481 bias-pull-down; 482 drive-strength = <2>; 483 }; 484 }; 485 486 bt_pins: bt-pins { 487 pins-bt-en { 488 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 489 output-low; 490 }; 491 }; 492 493 ec_ap_int_odl: ec-ap-int-odl { 494 pins1 { 495 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 496 input-enable; 497 bias-pull-up; 498 }; 499 }; 500 501 h1_int_od_l: h1-int-od-l { 502 pins1 { 503 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 504 input-enable; 505 }; 506 }; 507 508 i2c0_pins: i2c0 { 509 pins-bus { 510 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 511 <PINMUX_GPIO83__FUNC_SCL0>; 512 mediatek,pull-up-adv = <3>; 513 }; 514 }; 515 516 i2c1_pins: i2c1 { 517 pins-bus { 518 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 519 <PINMUX_GPIO84__FUNC_SCL1>; 520 mediatek,pull-up-adv = <3>; 521 }; 522 }; 523 524 i2c2_pins: i2c2 { 525 pins-bus { 526 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 527 <PINMUX_GPIO104__FUNC_SDA2>; 528 bias-disable; 529 }; 530 }; 531 532 i2c3_pins: i2c3 { 533 pins-bus { 534 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 535 <PINMUX_GPIO51__FUNC_SDA3>; 536 mediatek,pull-up-adv = <3>; 537 }; 538 }; 539 540 i2c4_pins: i2c4 { 541 pins-bus { 542 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 543 <PINMUX_GPIO106__FUNC_SDA4>; 544 bias-disable; 545 }; 546 }; 547 548 i2c5_pins: i2c5 { 549 pins-bus { 550 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 551 <PINMUX_GPIO49__FUNC_SDA5>; 552 mediatek,pull-up-adv = <3>; 553 }; 554 }; 555 556 i2c6_pins: i2c6 { 557 pins-bus { 558 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 559 <PINMUX_GPIO12__FUNC_SDA6>; 560 bias-disable; 561 }; 562 }; 563 564 mmc0_pins_default: mmc0-pins-default { 565 pins-cmd-dat { 566 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 567 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 568 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 569 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 570 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 571 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 572 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 573 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 574 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 575 input-enable; 576 drive-strength = <MTK_DRIVE_14mA>; 577 mediatek,pull-up-adv = <01>; 578 }; 579 580 pins-clk { 581 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 582 drive-strength = <MTK_DRIVE_14mA>; 583 mediatek,pull-down-adv = <10>; 584 }; 585 586 pins-rst { 587 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 588 drive-strength = <MTK_DRIVE_14mA>; 589 mediatek,pull-down-adv = <01>; 590 }; 591 }; 592 593 mmc0_pins_uhs: mmc0-pins-uhs { 594 pins-cmd-dat { 595 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 596 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 597 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 598 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 599 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 600 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 601 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 602 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 603 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 604 input-enable; 605 drive-strength = <MTK_DRIVE_14mA>; 606 mediatek,pull-up-adv = <01>; 607 }; 608 609 pins-clk { 610 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 611 drive-strength = <MTK_DRIVE_14mA>; 612 mediatek,pull-down-adv = <10>; 613 }; 614 615 pins-ds { 616 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 617 drive-strength = <MTK_DRIVE_14mA>; 618 mediatek,pull-down-adv = <10>; 619 }; 620 621 pins-rst { 622 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 623 drive-strength = <MTK_DRIVE_14mA>; 624 mediatek,pull-up-adv = <01>; 625 }; 626 }; 627 628 mmc1_pins_default: mmc1-pins-default { 629 pins-cmd-dat { 630 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 631 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 632 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 633 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 634 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 635 input-enable; 636 mediatek,pull-up-adv = <10>; 637 }; 638 639 pins-clk { 640 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 641 input-enable; 642 mediatek,pull-down-adv = <10>; 643 }; 644 }; 645 646 mmc1_pins_uhs: mmc1-pins-uhs { 647 pins-cmd-dat { 648 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 649 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 650 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 651 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 652 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 653 drive-strength = <6>; 654 input-enable; 655 mediatek,pull-up-adv = <10>; 656 }; 657 658 pins-clk { 659 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 660 drive-strength = <8>; 661 mediatek,pull-down-adv = <10>; 662 input-enable; 663 }; 664 }; 665 666 panel_pins_default: panel-pins-default { 667 panel-reset { 668 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 669 output-low; 670 bias-pull-up; 671 }; 672 }; 673 674 pwm0_pin_default: pwm0-pin-default { 675 pins1 { 676 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 677 output-high; 678 bias-pull-up; 679 }; 680 pins2 { 681 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 682 }; 683 }; 684 685 scp_pins: scp { 686 pins-scp-uart { 687 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 688 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 689 }; 690 }; 691 692 spi0_pins: spi0 { 693 pins-spi { 694 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 695 <PINMUX_GPIO86__FUNC_GPIO86>, 696 <PINMUX_GPIO87__FUNC_SPI0_MO>, 697 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 698 bias-disable; 699 }; 700 }; 701 702 spi1_pins: spi1 { 703 pins-spi { 704 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 705 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 706 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 707 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 708 bias-disable; 709 }; 710 }; 711 712 spi2_pins: spi2 { 713 pins-spi { 714 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 715 <PINMUX_GPIO1__FUNC_SPI2_MO>, 716 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 717 bias-disable; 718 }; 719 pins-spi-mi { 720 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 721 mediatek,pull-down-adv = <00>; 722 }; 723 }; 724 725 spi3_pins: spi3 { 726 pins-spi { 727 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 728 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 729 <PINMUX_GPIO23__FUNC_SPI3_MO>, 730 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 731 bias-disable; 732 }; 733 }; 734 735 spi4_pins: spi4 { 736 pins-spi { 737 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 738 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 739 <PINMUX_GPIO19__FUNC_SPI4_MO>, 740 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 741 bias-disable; 742 }; 743 }; 744 745 spi5_pins: spi5 { 746 pins-spi { 747 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 748 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 749 <PINMUX_GPIO15__FUNC_SPI5_MO>, 750 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 751 bias-disable; 752 }; 753 }; 754 755 uart0_pins_default: uart0-pins-default { 756 pins-rx { 757 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 758 input-enable; 759 bias-pull-up; 760 }; 761 pins-tx { 762 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 763 }; 764 }; 765 766 uart1_pins_default: uart1-pins-default { 767 pins-rx { 768 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 769 input-enable; 770 bias-pull-up; 771 }; 772 pins-tx { 773 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 774 }; 775 pins-rts { 776 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 777 }; 778 pins-cts { 779 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 780 input-enable; 781 }; 782 }; 783 784 uart1_pins_sleep: uart1-pins-sleep { 785 pins-rx { 786 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 787 input-enable; 788 bias-pull-up; 789 }; 790 pins-tx { 791 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 792 }; 793 pins-rts { 794 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 795 }; 796 pins-cts { 797 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 798 input-enable; 799 }; 800 }; 801 802 wifi_pins_pwrseq: wifi-pins-pwrseq { 803 pins-wifi-enable { 804 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 805 output-low; 806 }; 807 }; 808 809 wifi_pins_wakeup: wifi-pins-wakeup { 810 pins-wifi-wakeup { 811 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 812 input-enable; 813 }; 814 }; 815}; 816 817&pmic { 818 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>; 819}; 820 821&pwm0 { 822 status = "okay"; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&pwm0_pin_default>; 825}; 826 827&scp { 828 status = "okay"; 829 830 firmware-name = "mediatek/mt8183/scp.img"; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&scp_pins>; 833 834 cros-ec-rpmsg { 835 compatible = "google,cros-ec-rpmsg"; 836 mediatek,rpmsg-name = "cros-ec-rpmsg"; 837 }; 838}; 839 840&mfg_async { 841 domain-supply = <&mt6358_vsram_gpu_reg>; 842}; 843 844&mfg { 845 domain-supply = <&mt6358_vgpu_reg>; 846}; 847 848&spi0 { 849 pinctrl-names = "default"; 850 pinctrl-0 = <&spi0_pins>; 851 mediatek,pad-select = <0>; 852 status = "okay"; 853 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 854 855 tpm@0 { 856 compatible = "google,cr50"; 857 reg = <0>; 858 spi-max-frequency = <1000000>; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&h1_int_od_l>; 861 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>; 862 }; 863}; 864 865&spi1 { 866 pinctrl-names = "default"; 867 pinctrl-0 = <&spi1_pins>; 868 mediatek,pad-select = <0>; 869 status = "okay"; 870 871 w25q64dw: flash@0 { 872 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 873 reg = <0>; 874 spi-max-frequency = <25000000>; 875 }; 876}; 877 878&spi2 { 879 pinctrl-names = "default"; 880 pinctrl-0 = <&spi2_pins>; 881 mediatek,pad-select = <0>; 882 status = "okay"; 883 884 cros_ec: cros-ec@0 { 885 compatible = "google,cros-ec-spi"; 886 reg = <0>; 887 spi-max-frequency = <3000000>; 888 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&ec_ap_int_odl>; 891 wakeup-source; 892 893 i2c_tunnel: i2c-tunnel { 894 compatible = "google,cros-ec-i2c-tunnel"; 895 google,remote-bus = <1>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 }; 899 900 usbc_extcon: extcon0 { 901 compatible = "google,extcon-usbc-cros-ec"; 902 google,usb-port-id = <0>; 903 }; 904 905 typec { 906 compatible = "google,cros-ec-typec"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 910 usb_c0: connector@0 { 911 compatible = "usb-c-connector"; 912 reg = <0>; 913 power-role = "dual"; 914 data-role = "host"; 915 try-power-role = "sink"; 916 }; 917 }; 918 }; 919}; 920 921&spi3 { 922 pinctrl-names = "default"; 923 pinctrl-0 = <&spi3_pins>; 924 mediatek,pad-select = <0>; 925 status = "disabled"; 926}; 927 928&spi4 { 929 pinctrl-names = "default"; 930 pinctrl-0 = <&spi4_pins>; 931 mediatek,pad-select = <0>; 932 status = "disabled"; 933}; 934 935&spi5 { 936 pinctrl-names = "default"; 937 pinctrl-0 = <&spi5_pins>; 938 mediatek,pad-select = <0>; 939 status = "disabled"; 940}; 941 942&ssusb { 943 dr_mode = "host"; 944 wakeup-source; 945 vusb33-supply = <&mt6358_vusb_reg>; 946 status = "okay"; 947}; 948 949&thermal_zones { 950 tboard1-thermal { 951 polling-delay = <1000>; /* milliseconds */ 952 polling-delay-passive = <0>; /* milliseconds */ 953 thermal-sensors = <&tboard_thermistor1>; 954 }; 955 956 tboard2-thermal { 957 polling-delay = <1000>; /* milliseconds */ 958 polling-delay-passive = <0>; /* milliseconds */ 959 thermal-sensors = <&tboard_thermistor2>; 960 }; 961}; 962 963&u3phy { 964 status = "okay"; 965}; 966 967&uart0 { 968 pinctrl-names = "default"; 969 pinctrl-0 = <&uart0_pins_default>; 970 status = "okay"; 971}; 972 973&uart1 { 974 pinctrl-names = "default", "sleep"; 975 pinctrl-0 = <&uart1_pins_default>; 976 pinctrl-1 = <&uart1_pins_sleep>; 977 status = "okay"; 978 /delete-property/ interrupts; 979 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 980 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 981 982 bluetooth: bluetooth { 983 pinctrl-names = "default"; 984 pinctrl-0 = <&bt_pins>; 985 status = "okay"; 986 compatible = "qcom,qca6174-bt"; 987 enable-gpios = <&pio 120 0>; 988 clocks = <&clk32k>; 989 firmware-name = "nvm_00440302_i2s.bin"; 990 }; 991}; 992 993&usb_host { 994 #address-cells = <1>; 995 #size-cells = <0>; 996 vusb33-supply = <&mt6358_vusb_reg>; 997 status = "okay"; 998 999 hub@1 { 1000 compatible = "usb5e3,610"; 1001 reg = <1>; 1002 }; 1003}; 1004 1005#include <arm/cros-ec-sbs.dtsi> 1006