1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 }; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 backlight_lcd0: backlight_lcd0 { 23 compatible = "pwm-backlight"; 24 pwms = <&pwm0 0 500000>; 25 power-supply = <&bl_pp5000>; 26 enable-gpios = <&pio 176 0>; 27 brightness-levels = <0 1023>; 28 num-interpolated-steps = <1023>; 29 default-brightness-level = <576>; 30 status = "okay"; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0 0x40000000 0 0x80000000>; 36 }; 37 38 clk32k: oscillator1 { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32768>; 42 clock-output-names = "clk32k"; 43 }; 44 45 it6505_pp18_reg: regulator0 { 46 compatible = "regulator-fixed"; 47 regulator-name = "it6505_pp18"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 }; 53 54 lcd_pp3300: regulator1 { 55 compatible = "regulator-fixed"; 56 regulator-name = "lcd_pp3300"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 regulator-always-on; 60 regulator-boot-on; 61 }; 62 63 bl_pp5000: regulator2 { 64 compatible = "regulator-fixed"; 65 regulator-name = "bl_pp5000"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 regulator-always-on; 69 regulator-boot-on; 70 }; 71 72 mmc1_fixed_power: regulator3 { 73 compatible = "regulator-fixed"; 74 regulator-name = "mmc1_power"; 75 regulator-min-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>; 77 }; 78 79 mmc1_fixed_io: regulator4 { 80 compatible = "regulator-fixed"; 81 regulator-name = "mmc1_io"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <1800000>; 84 }; 85 86 pp1800_alw: regulator5 { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp1800_alw"; 89 regulator-always-on; 90 regulator-boot-on; 91 regulator-min-microvolt = <1800000>; 92 regulator-max-microvolt = <1800000>; 93 }; 94 95 pp3300_alw: regulator6 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_alw"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 }; 103 104 reserved_memory: reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 scp_mem_reserved: scp_mem_region { 110 compatible = "shared-dma-pool"; 111 reg = <0 0x50000000 0 0x2900000>; 112 no-map; 113 }; 114 }; 115 116 max98357a: codec0 { 117 compatible = "maxim,max98357a"; 118 sdmode-gpios = <&pio 175 0>; 119 }; 120 121 btsco: codec1 { 122 compatible = "linux,bt-sco"; 123 }; 124 125 wifi_pwrseq: wifi-pwrseq { 126 compatible = "mmc-pwrseq-simple"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&wifi_pins_pwrseq>; 129 130 /* Toggle WIFI_ENABLE to reset the chip. */ 131 reset-gpios = <&pio 119 1>; 132 }; 133 134 wifi_wakeup: wifi-wakeup { 135 compatible = "gpio-keys"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&wifi_pins_wakeup>; 138 139 wowlan { 140 label = "Wake on WiFi"; 141 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 142 linux,code = <KEY_WAKEUP>; 143 wakeup-source; 144 }; 145 }; 146 147 tboard_thermistor1: thermal-sensor1 { 148 compatible = "generic-adc-thermal"; 149 #thermal-sensor-cells = <0>; 150 io-channels = <&auxadc 0>; 151 io-channel-names = "sensor-channel"; 152 temperature-lookup-table = < (-5000) 4241 153 0 4063 154 5000 3856 155 10000 3621 156 15000 3364 157 20000 3091 158 25000 2810 159 30000 2526 160 35000 2247 161 40000 1982 162 45000 1734 163 50000 1507 164 55000 1305 165 60000 1122 166 65000 964 167 70000 827 168 75000 710 169 80000 606 170 85000 519 171 90000 445 172 95000 382 173 100000 330 174 105000 284 175 110000 245 176 115000 213 177 120000 183 178 125000 161>; 179 }; 180 181 tboard_thermistor2: thermal-sensor2 { 182 compatible = "generic-adc-thermal"; 183 #thermal-sensor-cells = <0>; 184 io-channels = <&auxadc 1>; 185 io-channel-names = "sensor-channel"; 186 temperature-lookup-table = < (-5000) 4241 187 0 4063 188 5000 3856 189 10000 3621 190 15000 3364 191 20000 3091 192 25000 2810 193 30000 2526 194 35000 2247 195 40000 1982 196 45000 1734 197 50000 1507 198 55000 1305 199 60000 1122 200 65000 964 201 70000 827 202 75000 710 203 80000 606 204 85000 519 205 90000 445 206 95000 382 207 100000 330 208 105000 284 209 110000 245 210 115000 213 211 120000 183 212 125000 161>; 213 }; 214}; 215 216&auxadc { 217 status = "okay"; 218}; 219 220&cpu0 { 221 proc-supply = <&mt6358_vproc12_reg>; 222}; 223 224&cpu1 { 225 proc-supply = <&mt6358_vproc12_reg>; 226}; 227 228&cpu2 { 229 proc-supply = <&mt6358_vproc12_reg>; 230}; 231 232&cpu3 { 233 proc-supply = <&mt6358_vproc12_reg>; 234}; 235 236&cpu4 { 237 proc-supply = <&mt6358_vproc11_reg>; 238}; 239 240&cpu5 { 241 proc-supply = <&mt6358_vproc11_reg>; 242}; 243 244&cpu6 { 245 proc-supply = <&mt6358_vproc11_reg>; 246}; 247 248&cpu7 { 249 proc-supply = <&mt6358_vproc11_reg>; 250}; 251 252&dsi0 { 253 status = "okay"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 panel: panel@0 { 257 /* compatible will be set in board dts */ 258 reg = <0>; 259 enable-gpios = <&pio 45 0>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&panel_pins_default>; 262 avdd-supply = <&ppvarn_lcd>; 263 avee-supply = <&ppvarp_lcd>; 264 pp1800-supply = <&pp1800_lcd>; 265 backlight = <&backlight_lcd0>; 266 port { 267 panel_in: endpoint { 268 remote-endpoint = <&dsi_out>; 269 }; 270 }; 271 }; 272 273 ports { 274 port { 275 dsi_out: endpoint { 276 remote-endpoint = <&panel_in>; 277 }; 278 }; 279 }; 280}; 281 282&gpu { 283 mali-supply = <&mt6358_vgpu_reg>; 284 sram-supply = <&mt6358_vsram_gpu_reg>; 285}; 286 287&i2c0 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&i2c0_pins>; 290 status = "okay"; 291 clock-frequency = <400000>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294}; 295 296&i2c1 { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c1_pins>; 299 status = "okay"; 300 clock-frequency = <100000>; 301}; 302 303&i2c3 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&i2c3_pins>; 306 status = "okay"; 307 clock-frequency = <100000>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310}; 311 312&i2c5 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c5_pins>; 315 status = "okay"; 316 clock-frequency = <100000>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319}; 320 321&i2c6 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&i2c6_pins>; 324 status = "okay"; 325 clock-frequency = <100000>; 326}; 327 328&mipi_tx0 { 329 status = "okay"; 330}; 331 332&mmc0 { 333 status = "okay"; 334 pinctrl-names = "default", "state_uhs"; 335 pinctrl-0 = <&mmc0_pins_default>; 336 pinctrl-1 = <&mmc0_pins_uhs>; 337 bus-width = <8>; 338 max-frequency = <200000000>; 339 cap-mmc-highspeed; 340 mmc-hs200-1_8v; 341 mmc-hs400-1_8v; 342 cap-mmc-hw-reset; 343 no-sdio; 344 no-sd; 345 hs400-ds-delay = <0x12814>; 346 vmmc-supply = <&mt6358_vemc_reg>; 347 vqmmc-supply = <&mt6358_vio18_reg>; 348 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 349 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 350 non-removable; 351}; 352 353&mmc1 { 354 status = "okay"; 355 pinctrl-names = "default", "state_uhs"; 356 pinctrl-0 = <&mmc1_pins_default>; 357 pinctrl-1 = <&mmc1_pins_uhs>; 358 vmmc-supply = <&mmc1_fixed_power>; 359 vqmmc-supply = <&mmc1_fixed_io>; 360 mmc-pwrseq = <&wifi_pwrseq>; 361 bus-width = <4>; 362 max-frequency = <200000000>; 363 drv-type = <2>; 364 cap-sd-highspeed; 365 sd-uhs-sdr50; 366 sd-uhs-sdr104; 367 keep-power-in-suspend; 368 enable-sdio-wakeup; 369 cap-sdio-irq; 370 non-removable; 371 no-mmc; 372 no-sd; 373 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 374 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 qca_wifi: qca-wifi@1 { 379 compatible = "qcom,ath10k"; 380 reg = <1>; 381 }; 382}; 383 384&mt6358_vdram2_reg { 385 regulator-always-on; 386}; 387 388&mt6358codec { 389 Avdd-supply = <&mt6358_vaud28_reg>; 390}; 391 392&mt6358_vsim1_reg { 393 regulator-min-microvolt = <2700000>; 394 regulator-max-microvolt = <2700000>; 395}; 396 397&mt6358_vsim2_reg { 398 regulator-min-microvolt = <2700000>; 399 regulator-max-microvolt = <2700000>; 400}; 401 402&pio { 403 bt_pins: bt-pins { 404 pins_bt_en { 405 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 406 output-low; 407 }; 408 }; 409 410 ec_ap_int_odl: ec_ap_int_odl { 411 pins1 { 412 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 413 input-enable; 414 bias-pull-up; 415 }; 416 }; 417 418 h1_int_od_l: h1_int_od_l { 419 pins1 { 420 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 421 input-enable; 422 }; 423 }; 424 425 i2c0_pins: i2c0 { 426 pins_bus { 427 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 428 <PINMUX_GPIO83__FUNC_SCL0>; 429 mediatek,pull-up-adv = <3>; 430 mediatek,drive-strength-adv = <00>; 431 }; 432 }; 433 434 i2c1_pins: i2c1 { 435 pins_bus { 436 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 437 <PINMUX_GPIO84__FUNC_SCL1>; 438 mediatek,pull-up-adv = <3>; 439 mediatek,drive-strength-adv = <00>; 440 }; 441 }; 442 443 i2c2_pins: i2c2 { 444 pins_bus { 445 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 446 <PINMUX_GPIO104__FUNC_SDA2>; 447 bias-disable; 448 mediatek,drive-strength-adv = <00>; 449 }; 450 }; 451 452 i2c3_pins: i2c3 { 453 pins_bus { 454 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 455 <PINMUX_GPIO51__FUNC_SDA3>; 456 mediatek,pull-up-adv = <3>; 457 mediatek,drive-strength-adv = <00>; 458 }; 459 }; 460 461 i2c4_pins: i2c4 { 462 pins_bus { 463 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 464 <PINMUX_GPIO106__FUNC_SDA4>; 465 bias-disable; 466 mediatek,drive-strength-adv = <00>; 467 }; 468 }; 469 470 i2c5_pins: i2c5 { 471 pins_bus { 472 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 473 <PINMUX_GPIO49__FUNC_SDA5>; 474 mediatek,pull-up-adv = <3>; 475 mediatek,drive-strength-adv = <00>; 476 }; 477 }; 478 479 i2c6_pins: i2c6 { 480 pins_bus { 481 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 482 <PINMUX_GPIO12__FUNC_SDA6>; 483 bias-disable; 484 }; 485 }; 486 487 mmc0_pins_default: mmc0-pins-default { 488 pins_cmd_dat { 489 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 490 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 491 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 492 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 493 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 494 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 495 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 496 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 497 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 498 input-enable; 499 drive-strength = <MTK_DRIVE_14mA>; 500 mediatek,pull-up-adv = <01>; 501 }; 502 503 pins_clk { 504 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 505 drive-strength = <MTK_DRIVE_14mA>; 506 mediatek,pull-down-adv = <10>; 507 }; 508 509 pins_rst { 510 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 511 drive-strength = <MTK_DRIVE_14mA>; 512 mediatek,pull-down-adv = <01>; 513 }; 514 }; 515 516 mmc0_pins_uhs: mmc0-pins-uhs { 517 pins_cmd_dat { 518 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 519 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 520 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 521 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 522 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 523 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 524 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 525 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 526 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 527 input-enable; 528 drive-strength = <MTK_DRIVE_14mA>; 529 mediatek,pull-up-adv = <01>; 530 }; 531 532 pins_clk { 533 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 534 drive-strength = <MTK_DRIVE_14mA>; 535 mediatek,pull-down-adv = <10>; 536 }; 537 538 pins_ds { 539 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 540 drive-strength = <MTK_DRIVE_14mA>; 541 mediatek,pull-down-adv = <10>; 542 }; 543 544 pins_rst { 545 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 546 drive-strength = <MTK_DRIVE_14mA>; 547 mediatek,pull-up-adv = <01>; 548 }; 549 }; 550 551 mmc1_pins_default: mmc1-pins-default { 552 pins_cmd_dat { 553 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 554 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 555 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 556 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 557 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 558 input-enable; 559 mediatek,pull-up-adv = <10>; 560 }; 561 562 pins_clk { 563 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 564 input-enable; 565 mediatek,pull-down-adv = <10>; 566 }; 567 }; 568 569 mmc1_pins_uhs: mmc1-pins-uhs { 570 pins_cmd_dat { 571 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 572 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 573 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 574 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 575 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 576 drive-strength = <MTK_DRIVE_6mA>; 577 input-enable; 578 mediatek,pull-up-adv = <10>; 579 }; 580 581 pins_clk { 582 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 583 drive-strength = <MTK_DRIVE_8mA>; 584 mediatek,pull-down-adv = <10>; 585 input-enable; 586 }; 587 }; 588 589 panel_pins_default: panel_pins_default { 590 panel_reset { 591 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 592 output-low; 593 bias-pull-up; 594 }; 595 }; 596 597 pwm0_pin_default: pwm0_pin_default { 598 pins1 { 599 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 600 output-high; 601 bias-pull-up; 602 }; 603 pins2 { 604 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 605 }; 606 }; 607 608 scp_pins: scp { 609 pins_scp_uart { 610 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 611 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 612 }; 613 }; 614 615 spi0_pins: spi0 { 616 pins_spi{ 617 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 618 <PINMUX_GPIO86__FUNC_GPIO86>, 619 <PINMUX_GPIO87__FUNC_SPI0_MO>, 620 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 621 bias-disable; 622 }; 623 }; 624 625 spi1_pins: spi1 { 626 pins_spi{ 627 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 628 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 629 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 630 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 631 bias-disable; 632 }; 633 }; 634 635 spi2_pins: spi2 { 636 pins_spi{ 637 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 638 <PINMUX_GPIO1__FUNC_SPI2_MO>, 639 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 640 bias-disable; 641 }; 642 pins_spi_mi { 643 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 644 mediatek,pull-down-adv = <00>; 645 }; 646 }; 647 648 spi3_pins: spi3 { 649 pins_spi{ 650 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 651 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 652 <PINMUX_GPIO23__FUNC_SPI3_MO>, 653 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 654 bias-disable; 655 }; 656 }; 657 658 spi4_pins: spi4 { 659 pins_spi{ 660 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 661 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 662 <PINMUX_GPIO19__FUNC_SPI4_MO>, 663 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 664 bias-disable; 665 }; 666 }; 667 668 spi5_pins: spi5 { 669 pins_spi{ 670 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 671 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 672 <PINMUX_GPIO15__FUNC_SPI5_MO>, 673 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 674 bias-disable; 675 }; 676 }; 677 678 uart0_pins_default: uart0-pins-default { 679 pins_rx { 680 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 681 input-enable; 682 bias-pull-up; 683 }; 684 pins_tx { 685 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 686 }; 687 }; 688 689 uart1_pins_default: uart1-pins-default { 690 pins_rx { 691 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 692 input-enable; 693 bias-pull-up; 694 }; 695 pins_tx { 696 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 697 }; 698 pins_rts { 699 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 700 output-enable; 701 }; 702 pins_cts { 703 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 704 input-enable; 705 }; 706 }; 707 708 uart1_pins_sleep: uart1-pins-sleep { 709 pins_rx { 710 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 711 input-enable; 712 bias-pull-up; 713 }; 714 pins_tx { 715 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 716 }; 717 pins_rts { 718 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 719 output-enable; 720 }; 721 pins_cts { 722 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 723 input-enable; 724 }; 725 }; 726 727 wifi_pins_pwrseq: wifi-pins-pwrseq { 728 pins_wifi_enable { 729 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 730 output-low; 731 }; 732 }; 733 734 wifi_pins_wakeup: wifi-pins-wakeup { 735 pins_wifi_wakeup { 736 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 737 input-enable; 738 }; 739 }; 740}; 741 742&pwm0 { 743 status = "okay"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&pwm0_pin_default>; 746}; 747 748&scp { 749 status = "okay"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&scp_pins>; 752 753 cros_ec { 754 compatible = "google,cros-ec-rpmsg"; 755 mtk,rpmsg-name = "cros-ec-rpmsg"; 756 }; 757}; 758 759&mfg { 760 domain-supply = <&mt6358_vgpu_reg>; 761}; 762 763&soc_data { 764 status = "okay"; 765}; 766 767&spi0 { 768 pinctrl-names = "default"; 769 pinctrl-0 = <&spi0_pins>; 770 mediatek,pad-select = <0>; 771 status = "okay"; 772 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 773 774 cr50@0 { 775 compatible = "google,cr50"; 776 reg = <0>; 777 spi-max-frequency = <1000000>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&h1_int_od_l>; 780 interrupt-parent = <&pio>; 781 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 782 }; 783}; 784 785&spi1 { 786 pinctrl-names = "default"; 787 pinctrl-0 = <&spi1_pins>; 788 mediatek,pad-select = <0>; 789 status = "okay"; 790 791 w25q64dw: spi-flash@0 { 792 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 793 reg = <0>; 794 spi-max-frequency = <25000000>; 795 }; 796}; 797 798&spi2 { 799 pinctrl-names = "default"; 800 pinctrl-0 = <&spi2_pins>; 801 mediatek,pad-select = <0>; 802 status = "okay"; 803 804 cros_ec: cros-ec@0 { 805 compatible = "google,cros-ec-spi"; 806 reg = <0>; 807 spi-max-frequency = <3000000>; 808 interrupt-parent = <&pio>; 809 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&ec_ap_int_odl>; 812 813 i2c_tunnel: i2c-tunnel { 814 compatible = "google,cros-ec-i2c-tunnel"; 815 google,remote-bus = <1>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 }; 819 820 usbc_extcon: extcon0 { 821 compatible = "google,extcon-usbc-cros-ec"; 822 google,usb-port-id = <0>; 823 }; 824 825 cbas { 826 compatible = "google,cros-cbas"; 827 }; 828 }; 829}; 830 831&spi3 { 832 pinctrl-names = "default"; 833 pinctrl-0 = <&spi3_pins>; 834 mediatek,pad-select = <0>; 835 status = "disabled"; 836}; 837 838&spi4 { 839 pinctrl-names = "default"; 840 pinctrl-0 = <&spi4_pins>; 841 mediatek,pad-select = <0>; 842 status = "disabled"; 843}; 844 845&spi5 { 846 pinctrl-names = "default"; 847 pinctrl-0 = <&spi5_pins>; 848 mediatek,pad-select = <0>; 849 status = "disabled"; 850}; 851 852&ssusb { 853 dr_mode = "host"; 854 wakeup-source; 855 vusb33-supply = <&mt6358_vusb_reg>; 856 status = "okay"; 857}; 858 859&thermal_zones { 860 tboard1 { 861 polling-delay = <1000>; /* milliseconds */ 862 polling-delay-passive = <0>; /* milliseconds */ 863 thermal-sensors = <&tboard_thermistor1>; 864 }; 865 866 tboard2 { 867 polling-delay = <1000>; /* milliseconds */ 868 polling-delay-passive = <0>; /* milliseconds */ 869 thermal-sensors = <&tboard_thermistor2>; 870 }; 871}; 872 873&u3phy { 874 status = "okay"; 875}; 876 877&uart0 { 878 pinctrl-names = "default"; 879 pinctrl-0 = <&uart0_pins_default>; 880 status = "okay"; 881}; 882 883&uart1 { 884 pinctrl-names = "default", "sleep"; 885 pinctrl-0 = <&uart1_pins_default>; 886 pinctrl-1 = <&uart1_pins_sleep>; 887 status = "okay"; 888 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 889 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 890 891 bluetooth: bluetooth { 892 pinctrl-names = "default"; 893 pinctrl-0 = <&bt_pins>; 894 status = "okay"; 895 compatible = "qcom,qca6174-bt"; 896 enable-gpios = <&pio 120 0>; 897 clocks = <&clk32k>; 898 firmware-name = "nvm_00440302_i2s.bin"; 899 }; 900}; 901 902&usb_host { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 vusb33-supply = <&mt6358_vusb_reg>; 906 status = "okay"; 907 908 hub@1 { 909 compatible = "usb5e3,610"; 910 reg = <1>; 911 }; 912}; 913 914#include <arm/cros-ec-keyboard.dtsi> 915#include <arm/cros-ec-sbs.dtsi> 916