1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include "mt8173-pinfunc.h" 17 18/ { 19 compatible = "mediatek,mt8173"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 core1 { 34 cpu = <&cpu1>; 35 }; 36 }; 37 38 cluster1 { 39 core0 { 40 cpu = <&cpu2>; 41 }; 42 core1 { 43 cpu = <&cpu3>; 44 }; 45 }; 46 }; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x000>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x001>; 58 enable-method = "psci"; 59 }; 60 61 cpu2: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a57"; 64 reg = <0x100>; 65 enable-method = "psci"; 66 }; 67 68 cpu3: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a57"; 71 reg = <0x101>; 72 enable-method = "psci"; 73 }; 74 }; 75 76 psci { 77 compatible = "arm,psci"; 78 method = "smc"; 79 cpu_suspend = <0x84000001>; 80 cpu_off = <0x84000002>; 81 cpu_on = <0x84000003>; 82 }; 83 84 uart_clk: dummy26m { 85 compatible = "fixed-clock"; 86 clock-frequency = <26000000>; 87 #clock-cells = <0>; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupt-parent = <&gic>; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 101 }; 102 103 soc { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 compatible = "simple-bus"; 107 ranges; 108 109 /* 110 * Pinctrl access register at 0x10005000 through regmap. 111 * Register 0x1000b000 is used by EINT. 112 */ 113 pio: pinctrl@10005000 { 114 compatible = "mediatek,mt8173-pinctrl"; 115 reg = <0 0x1000b000 0 0x1000>; 116 mediatek,pctl-regmap = <&syscfg_pctl_a>; 117 pins-are-numbered; 118 gpio-controller; 119 #gpio-cells = <2>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 syscfg_pctl_a: syscfg_pctl_a@10005000 { 128 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 129 reg = <0 0x10005000 0 0x1000>; 130 }; 131 132 sysirq: intpol-controller@10200620 { 133 compatible = "mediatek,mt8173-sysirq", 134 "mediatek,mt6577-sysirq"; 135 interrupt-controller; 136 #interrupt-cells = <3>; 137 interrupt-parent = <&gic>; 138 reg = <0 0x10200620 0 0x20>; 139 }; 140 141 gic: interrupt-controller@10220000 { 142 compatible = "arm,gic-400"; 143 #interrupt-cells = <3>; 144 interrupt-parent = <&gic>; 145 interrupt-controller; 146 reg = <0 0x10221000 0 0x1000>, 147 <0 0x10222000 0 0x2000>, 148 <0 0x10224000 0 0x2000>, 149 <0 0x10226000 0 0x2000>; 150 interrupts = <GIC_PPI 9 151 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 152 }; 153 154 uart0: serial@11002000 { 155 compatible = "mediatek,mt8173-uart", 156 "mediatek,mt6577-uart"; 157 reg = <0 0x11002000 0 0x400>; 158 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 159 clocks = <&uart_clk>; 160 status = "disabled"; 161 }; 162 163 uart1: serial@11003000 { 164 compatible = "mediatek,mt8173-uart", 165 "mediatek,mt6577-uart"; 166 reg = <0 0x11003000 0 0x400>; 167 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 168 clocks = <&uart_clk>; 169 status = "disabled"; 170 }; 171 172 uart2: serial@11004000 { 173 compatible = "mediatek,mt8173-uart", 174 "mediatek,mt6577-uart"; 175 reg = <0 0x11004000 0 0x400>; 176 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 177 clocks = <&uart_clk>; 178 status = "disabled"; 179 }; 180 181 uart3: serial@11005000 { 182 compatible = "mediatek,mt8173-uart", 183 "mediatek,mt6577-uart"; 184 reg = <0 0x11005000 0 0x400>; 185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 186 clocks = <&uart_clk>; 187 status = "disabled"; 188 }; 189 }; 190}; 191 192