1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS. 5 * Author: Fabien Parent <fparent@baylibre.com> 6 */ 7 8#include <dt-bindings/clock/mt8167-clk.h> 9#include <dt-bindings/memory/mt8167-larb-port.h> 10#include <dt-bindings/power/mt8167-power.h> 11 12#include "mt8167-pinfunc.h" 13 14#include "mt8516.dtsi" 15 16/ { 17 compatible = "mediatek,mt8167"; 18 19 soc { 20 topckgen: topckgen@10000000 { 21 compatible = "mediatek,mt8167-topckgen", "syscon"; 22 reg = <0 0x10000000 0 0x1000>; 23 #clock-cells = <1>; 24 }; 25 26 infracfg: infracfg@10001000 { 27 compatible = "mediatek,mt8167-infracfg", "syscon"; 28 reg = <0 0x10001000 0 0x1000>; 29 #clock-cells = <1>; 30 }; 31 32 apmixedsys: apmixedsys@10018000 { 33 compatible = "mediatek,mt8167-apmixedsys", "syscon"; 34 reg = <0 0x10018000 0 0x710>; 35 #clock-cells = <1>; 36 }; 37 38 scpsys: syscon@10006000 { 39 compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; 40 reg = <0 0x10006000 0 0x1000>; 41 42 spm: power-controller { 43 compatible = "mediatek,mt8167-power-controller"; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 #power-domain-cells = <1>; 47 48 /* power domains of the SoC */ 49 power-domain@MT8167_POWER_DOMAIN_MM { 50 reg = <MT8167_POWER_DOMAIN_MM>; 51 clocks = <&topckgen CLK_TOP_SMI_MM>; 52 clock-names = "mm"; 53 #power-domain-cells = <0>; 54 mediatek,infracfg = <&infracfg>; 55 }; 56 57 power-domain@MT8167_POWER_DOMAIN_VDEC { 58 reg = <MT8167_POWER_DOMAIN_VDEC>; 59 clocks = <&topckgen CLK_TOP_SMI_MM>, 60 <&topckgen CLK_TOP_RG_VDEC>; 61 clock-names = "mm", "vdec"; 62 #power-domain-cells = <0>; 63 }; 64 65 power-domain@MT8167_POWER_DOMAIN_ISP { 66 reg = <MT8167_POWER_DOMAIN_ISP>; 67 clocks = <&topckgen CLK_TOP_SMI_MM>; 68 clock-names = "mm"; 69 #power-domain-cells = <0>; 70 }; 71 72 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { 73 reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; 74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, 75 <&topckgen CLK_TOP_RG_SLOW_MFG>; 76 clock-names = "axi_mfg", "mfg"; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 #power-domain-cells = <1>; 80 mediatek,infracfg = <&infracfg>; 81 82 power-domain@MT8167_POWER_DOMAIN_MFG_2D { 83 reg = <MT8167_POWER_DOMAIN_MFG_2D>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 #power-domain-cells = <1>; 87 88 power-domain@MT8167_POWER_DOMAIN_MFG { 89 reg = <MT8167_POWER_DOMAIN_MFG>; 90 #power-domain-cells = <0>; 91 mediatek,infracfg = <&infracfg>; 92 }; 93 }; 94 }; 95 96 power-domain@MT8167_POWER_DOMAIN_CONN { 97 reg = <MT8167_POWER_DOMAIN_CONN>; 98 #power-domain-cells = <0>; 99 mediatek,infracfg = <&infracfg>; 100 }; 101 }; 102 }; 103 104 imgsys: syscon@15000000 { 105 compatible = "mediatek,mt8167-imgsys", "syscon"; 106 reg = <0 0x15000000 0 0x1000>; 107 #clock-cells = <1>; 108 }; 109 110 vdecsys: syscon@16000000 { 111 compatible = "mediatek,mt8167-vdecsys", "syscon"; 112 reg = <0 0x16000000 0 0x1000>; 113 #clock-cells = <1>; 114 }; 115 116 pio: pinctrl@1000b000 { 117 compatible = "mediatek,mt8167-pinctrl"; 118 reg = <0 0x1000b000 0 0x1000>; 119 mediatek,pctl-regmap = <&syscfg_pctl>; 120 pins-are-numbered; 121 gpio-controller; 122 #gpio-cells = <2>; 123 interrupt-controller; 124 #interrupt-cells = <2>; 125 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 mmsys: mmsys@14000000 { 129 compatible = "mediatek,mt8167-mmsys", "syscon"; 130 reg = <0 0x14000000 0 0x1000>; 131 #clock-cells = <1>; 132 }; 133 134 smi_common: smi@14017000 { 135 compatible = "mediatek,mt8167-smi-common"; 136 reg = <0 0x14017000 0 0x1000>; 137 clocks = <&mmsys CLK_MM_SMI_COMMON>, 138 <&mmsys CLK_MM_SMI_COMMON>; 139 clock-names = "apb", "smi"; 140 power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 141 }; 142 143 larb0: larb@14016000 { 144 compatible = "mediatek,mt8167-smi-larb"; 145 reg = <0 0x14016000 0 0x1000>; 146 mediatek,smi = <&smi_common>; 147 clocks = <&mmsys CLK_MM_SMI_LARB0>, 148 <&mmsys CLK_MM_SMI_LARB0>; 149 clock-names = "apb", "smi"; 150 power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 151 }; 152 153 larb1: larb@15001000 { 154 compatible = "mediatek,mt8167-smi-larb"; 155 reg = <0 0x15001000 0 0x1000>; 156 mediatek,smi = <&smi_common>; 157 clocks = <&imgsys CLK_IMG_LARB1_SMI>, 158 <&imgsys CLK_IMG_LARB1_SMI>; 159 clock-names = "apb", "smi"; 160 power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; 161 }; 162 163 larb2: larb@16010000 { 164 compatible = "mediatek,mt8167-smi-larb"; 165 reg = <0 0x16010000 0 0x1000>; 166 mediatek,smi = <&smi_common>; 167 clocks = <&vdecsys CLK_VDEC_CKEN>, 168 <&vdecsys CLK_VDEC_LARB1_CKEN>; 169 clock-names = "apb", "smi"; 170 power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; 171 }; 172 173 iommu: m4u@10203000 { 174 compatible = "mediatek,mt8167-m4u"; 175 reg = <0 0x10203000 0 0x1000>; 176 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; 177 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; 178 #iommu-cells = <1>; 179 }; 180 }; 181}; 182