1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS. 5 * Author: Fabien Parent <fparent@baylibre.com> 6 */ 7 8#include <dt-bindings/clock/mt8167-clk.h> 9#include <dt-bindings/memory/mt8167-larb-port.h> 10#include <dt-bindings/power/mt8167-power.h> 11 12#include "mt8167-pinfunc.h" 13 14#include "mt8516.dtsi" 15 16/ { 17 compatible = "mediatek,mt8167"; 18 19 soc { 20 topckgen: topckgen@10000000 { 21 compatible = "mediatek,mt8167-topckgen", "syscon"; 22 reg = <0 0x10000000 0 0x1000>; 23 #clock-cells = <1>; 24 }; 25 26 infracfg: infracfg@10001000 { 27 compatible = "mediatek,mt8167-infracfg", "syscon"; 28 reg = <0 0x10001000 0 0x1000>; 29 #clock-cells = <1>; 30 }; 31 32 scpsys: syscon@10006000 { 33 compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; 34 reg = <0 0x10006000 0 0x1000>; 35 36 spm: power-controller { 37 compatible = "mediatek,mt8167-power-controller"; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 #power-domain-cells = <1>; 41 42 /* power domains of the SoC */ 43 power-domain@MT8167_POWER_DOMAIN_MM { 44 reg = <MT8167_POWER_DOMAIN_MM>; 45 clocks = <&topckgen CLK_TOP_SMI_MM>; 46 clock-names = "mm"; 47 #power-domain-cells = <0>; 48 mediatek,infracfg = <&infracfg>; 49 }; 50 51 power-domain@MT8167_POWER_DOMAIN_VDEC { 52 reg = <MT8167_POWER_DOMAIN_VDEC>; 53 clocks = <&topckgen CLK_TOP_SMI_MM>, 54 <&topckgen CLK_TOP_RG_VDEC>; 55 clock-names = "mm", "vdec"; 56 #power-domain-cells = <0>; 57 }; 58 59 power-domain@MT8167_POWER_DOMAIN_ISP { 60 reg = <MT8167_POWER_DOMAIN_ISP>; 61 clocks = <&topckgen CLK_TOP_SMI_MM>; 62 clock-names = "mm"; 63 #power-domain-cells = <0>; 64 }; 65 66 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { 67 reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; 68 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, 69 <&topckgen CLK_TOP_RG_SLOW_MFG>; 70 clock-names = "axi_mfg", "mfg"; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 #power-domain-cells = <1>; 74 mediatek,infracfg = <&infracfg>; 75 76 power-domain@MT8167_POWER_DOMAIN_MFG_2D { 77 reg = <MT8167_POWER_DOMAIN_MFG_2D>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 #power-domain-cells = <1>; 81 82 power-domain@MT8167_POWER_DOMAIN_MFG { 83 reg = <MT8167_POWER_DOMAIN_MFG>; 84 #power-domain-cells = <0>; 85 mediatek,infracfg = <&infracfg>; 86 }; 87 }; 88 }; 89 90 power-domain@MT8167_POWER_DOMAIN_CONN { 91 reg = <MT8167_POWER_DOMAIN_CONN>; 92 #power-domain-cells = <0>; 93 mediatek,infracfg = <&infracfg>; 94 }; 95 }; 96 }; 97 98 pio: pinctrl@1000b000 { 99 compatible = "mediatek,mt8167-pinctrl"; 100 reg = <0 0x1000b000 0 0x1000>; 101 mediatek,pctl-regmap = <&syscfg_pctl>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 interrupt-controller; 105 #interrupt-cells = <2>; 106 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 109 apmixedsys: apmixedsys@10018000 { 110 compatible = "mediatek,mt8167-apmixedsys", "syscon"; 111 reg = <0 0x10018000 0 0x710>; 112 #clock-cells = <1>; 113 }; 114 115 iommu: m4u@10203000 { 116 compatible = "mediatek,mt8167-m4u"; 117 reg = <0 0x10203000 0 0x1000>; 118 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; 119 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; 120 #iommu-cells = <1>; 121 }; 122 123 mmsys: syscon@14000000 { 124 compatible = "mediatek,mt8167-mmsys", "syscon"; 125 reg = <0 0x14000000 0 0x1000>; 126 #clock-cells = <1>; 127 }; 128 129 larb0: larb@14016000 { 130 compatible = "mediatek,mt8167-smi-larb"; 131 reg = <0 0x14016000 0 0x1000>; 132 mediatek,smi = <&smi_common>; 133 clocks = <&mmsys CLK_MM_SMI_LARB0>, 134 <&mmsys CLK_MM_SMI_LARB0>; 135 clock-names = "apb", "smi"; 136 power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 137 }; 138 139 smi_common: smi@14017000 { 140 compatible = "mediatek,mt8167-smi-common"; 141 reg = <0 0x14017000 0 0x1000>; 142 clocks = <&mmsys CLK_MM_SMI_COMMON>, 143 <&mmsys CLK_MM_SMI_COMMON>; 144 clock-names = "apb", "smi"; 145 power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 146 }; 147 148 imgsys: syscon@15000000 { 149 compatible = "mediatek,mt8167-imgsys", "syscon"; 150 reg = <0 0x15000000 0 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 larb1: larb@15001000 { 155 compatible = "mediatek,mt8167-smi-larb"; 156 reg = <0 0x15001000 0 0x1000>; 157 mediatek,smi = <&smi_common>; 158 clocks = <&imgsys CLK_IMG_LARB1_SMI>, 159 <&imgsys CLK_IMG_LARB1_SMI>; 160 clock-names = "apb", "smi"; 161 power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; 162 }; 163 164 vdecsys: syscon@16000000 { 165 compatible = "mediatek,mt8167-vdecsys", "syscon"; 166 reg = <0 0x16000000 0 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 larb2: larb@16010000 { 171 compatible = "mediatek,mt8167-smi-larb"; 172 reg = <0 0x16010000 0 0x1000>; 173 mediatek,smi = <&smi_common>; 174 clocks = <&vdecsys CLK_VDEC_CKEN>, 175 <&vdecsys CLK_VDEC_LARB1_CKEN>; 176 clock-names = "apb", "smi"; 177 power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; 178 }; 179 }; 180}; 181