1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7988-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6 7/ { 8 compatible = "mediatek,mt7988a"; 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "arm,cortex-a73"; 19 reg = <0x0>; 20 device_type = "cpu"; 21 enable-method = "psci"; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a73"; 26 reg = <0x1>; 27 device_type = "cpu"; 28 enable-method = "psci"; 29 }; 30 31 cpu@2 { 32 compatible = "arm,cortex-a73"; 33 reg = <0x2>; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 }; 37 38 cpu@3 { 39 compatible = "arm,cortex-a73"; 40 reg = <0x3>; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 }; 44 }; 45 46 oscillator-40m { 47 compatible = "fixed-clock"; 48 clock-frequency = <40000000>; 49 #clock-cells = <0>; 50 clock-output-names = "clkxtal"; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a73-pmu"; 55 interrupt-parent = <&gic>; 56 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 57 }; 58 59 psci { 60 compatible = "arm,psci-0.2"; 61 method = "smc"; 62 }; 63 64 soc { 65 compatible = "simple-bus"; 66 ranges; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 70 gic: interrupt-controller@c000000 { 71 compatible = "arm,gic-v3"; 72 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 73 <0 0x0c080000 0 0x200000>, /* GICR */ 74 <0 0x0c400000 0 0x2000>, /* GICC */ 75 <0 0x0c410000 0 0x1000>, /* GICH */ 76 <0 0x0c420000 0 0x2000>; /* GICV */ 77 interrupt-parent = <&gic>; 78 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-controller; 80 #interrupt-cells = <3>; 81 }; 82 83 infracfg: clock-controller@10001000 { 84 compatible = "mediatek,mt7988-infracfg", "syscon"; 85 reg = <0 0x10001000 0 0x1000>; 86 #clock-cells = <1>; 87 }; 88 89 topckgen: clock-controller@1001b000 { 90 compatible = "mediatek,mt7988-topckgen", "syscon"; 91 reg = <0 0x1001b000 0 0x1000>; 92 #clock-cells = <1>; 93 }; 94 95 watchdog: watchdog@1001c000 { 96 compatible = "mediatek,mt7988-wdt"; 97 reg = <0 0x1001c000 0 0x1000>; 98 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 99 #reset-cells = <1>; 100 }; 101 102 clock-controller@1001e000 { 103 compatible = "mediatek,mt7988-apmixedsys"; 104 reg = <0 0x1001e000 0 0x1000>; 105 #clock-cells = <1>; 106 }; 107 108 pwm@10048000 { 109 compatible = "mediatek,mt7988-pwm"; 110 reg = <0 0x10048000 0 0x1000>; 111 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, 112 <&infracfg CLK_INFRA_66M_PWM_HCK>, 113 <&infracfg CLK_INFRA_66M_PWM_CK1>, 114 <&infracfg CLK_INFRA_66M_PWM_CK2>, 115 <&infracfg CLK_INFRA_66M_PWM_CK3>, 116 <&infracfg CLK_INFRA_66M_PWM_CK4>, 117 <&infracfg CLK_INFRA_66M_PWM_CK5>, 118 <&infracfg CLK_INFRA_66M_PWM_CK6>, 119 <&infracfg CLK_INFRA_66M_PWM_CK7>, 120 <&infracfg CLK_INFRA_66M_PWM_CK8>; 121 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 122 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; 123 #pwm-cells = <2>; 124 status = "disabled"; 125 }; 126 127 serial@11000000 { 128 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 129 reg = <0 0x11000000 0 0x100>; 130 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "uart", "wakeup"; 132 clocks = <&topckgen CLK_TOP_UART_SEL>, 133 <&infracfg CLK_INFRA_52M_UART0_CK>; 134 clock-names = "baud", "bus"; 135 status = "disabled"; 136 }; 137 138 serial@11000100 { 139 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 140 reg = <0 0x11000100 0 0x100>; 141 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "uart", "wakeup"; 143 clocks = <&topckgen CLK_TOP_UART_SEL>, 144 <&infracfg CLK_INFRA_52M_UART1_CK>; 145 clock-names = "baud", "bus"; 146 status = "disabled"; 147 }; 148 149 serial@11000200 { 150 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 151 reg = <0 0x11000200 0 0x100>; 152 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 153 interrupt-names = "uart", "wakeup"; 154 clocks = <&topckgen CLK_TOP_UART_SEL>, 155 <&infracfg CLK_INFRA_52M_UART2_CK>; 156 clock-names = "baud", "bus"; 157 status = "disabled"; 158 }; 159 160 i2c@11003000 { 161 compatible = "mediatek,mt7981-i2c"; 162 reg = <0 0x11003000 0 0x1000>, 163 <0 0x10217080 0 0x80>; 164 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 166 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 167 clock-names = "main", "dma"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 status = "disabled"; 171 }; 172 173 i2c@11004000 { 174 compatible = "mediatek,mt7981-i2c"; 175 reg = <0 0x11004000 0 0x1000>, 176 <0 0x10217100 0 0x80>; 177 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 179 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 180 clock-names = "main", "dma"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 status = "disabled"; 184 }; 185 186 i2c@11005000 { 187 compatible = "mediatek,mt7981-i2c"; 188 reg = <0 0x11005000 0 0x1000>, 189 <0 0x10217180 0 0x80>; 190 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 192 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 193 clock-names = "main", "dma"; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 status = "disabled"; 197 }; 198 199 usb@11190000 { 200 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 201 reg = <0 0x11190000 0 0x2e00>, 202 <0 0x11193e00 0 0x0100>; 203 reg-names = "mac", "ippc"; 204 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&infracfg CLK_INFRA_USB_SYS>, 206 <&infracfg CLK_INFRA_USB_REF>, 207 <&infracfg CLK_INFRA_66M_USB_HCK>, 208 <&infracfg CLK_INFRA_133M_USB_HCK>, 209 <&infracfg CLK_INFRA_USB_XHCI>; 210 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 211 }; 212 213 usb@11200000 { 214 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 215 reg = <0 0x11200000 0 0x2e00>, 216 <0 0x11203e00 0 0x0100>; 217 reg-names = "mac", "ippc"; 218 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, 220 <&infracfg CLK_INFRA_USB_CK_P1>, 221 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, 222 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, 223 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; 224 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 225 }; 226 227 clock-controller@11f40000 { 228 compatible = "mediatek,mt7988-xfi-pll"; 229 reg = <0 0x11f40000 0 0x1000>; 230 resets = <&watchdog 16>; 231 #clock-cells = <1>; 232 }; 233 234 efuse@11f50000 { 235 compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; 236 reg = <0 0x11f50000 0 0x1000>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 }; 240 241 clock-controller@15000000 { 242 compatible = "mediatek,mt7988-ethsys", "syscon"; 243 reg = <0 0x15000000 0 0x1000>; 244 #clock-cells = <1>; 245 #reset-cells = <1>; 246 }; 247 248 clock-controller@15031000 { 249 compatible = "mediatek,mt7988-ethwarp"; 250 reg = <0 0x15031000 0 0x1000>; 251 #clock-cells = <1>; 252 #reset-cells = <1>; 253 }; 254 }; 255 256 timer { 257 compatible = "arm,armv8-timer"; 258 interrupt-parent = <&gic>; 259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 263 }; 264}; 265