1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7988-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6 7/ { 8 compatible = "mediatek,mt7988a"; 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "arm,cortex-a73"; 19 reg = <0x0>; 20 device_type = "cpu"; 21 enable-method = "psci"; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a73"; 26 reg = <0x1>; 27 device_type = "cpu"; 28 enable-method = "psci"; 29 }; 30 31 cpu@2 { 32 compatible = "arm,cortex-a73"; 33 reg = <0x2>; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 }; 37 38 cpu@3 { 39 compatible = "arm,cortex-a73"; 40 reg = <0x3>; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 }; 44 }; 45 46 oscillator-40m { 47 compatible = "fixed-clock"; 48 clock-frequency = <40000000>; 49 #clock-cells = <0>; 50 clock-output-names = "clkxtal"; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a73-pmu"; 55 interrupt-parent = <&gic>; 56 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 57 }; 58 59 psci { 60 compatible = "arm,psci-0.2"; 61 method = "smc"; 62 }; 63 64 soc { 65 compatible = "simple-bus"; 66 ranges; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 70 gic: interrupt-controller@c000000 { 71 compatible = "arm,gic-v3"; 72 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 73 <0 0x0c080000 0 0x200000>, /* GICR */ 74 <0 0x0c400000 0 0x2000>, /* GICC */ 75 <0 0x0c410000 0 0x1000>, /* GICH */ 76 <0 0x0c420000 0 0x2000>; /* GICV */ 77 interrupt-parent = <&gic>; 78 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-controller; 80 #interrupt-cells = <3>; 81 }; 82 83 infracfg: clock-controller@10001000 { 84 compatible = "mediatek,mt7988-infracfg", "syscon"; 85 reg = <0 0x10001000 0 0x1000>; 86 #clock-cells = <1>; 87 }; 88 89 clock-controller@1001b000 { 90 compatible = "mediatek,mt7988-topckgen", "syscon"; 91 reg = <0 0x1001b000 0 0x1000>; 92 #clock-cells = <1>; 93 }; 94 95 watchdog: watchdog@1001c000 { 96 compatible = "mediatek,mt7988-wdt"; 97 reg = <0 0x1001c000 0 0x1000>; 98 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 99 #reset-cells = <1>; 100 }; 101 102 clock-controller@1001e000 { 103 compatible = "mediatek,mt7988-apmixedsys"; 104 reg = <0 0x1001e000 0 0x1000>; 105 #clock-cells = <1>; 106 }; 107 108 pwm@10048000 { 109 compatible = "mediatek,mt7988-pwm"; 110 reg = <0 0x10048000 0 0x1000>; 111 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, 112 <&infracfg CLK_INFRA_66M_PWM_HCK>, 113 <&infracfg CLK_INFRA_66M_PWM_CK1>, 114 <&infracfg CLK_INFRA_66M_PWM_CK2>, 115 <&infracfg CLK_INFRA_66M_PWM_CK3>, 116 <&infracfg CLK_INFRA_66M_PWM_CK4>, 117 <&infracfg CLK_INFRA_66M_PWM_CK5>, 118 <&infracfg CLK_INFRA_66M_PWM_CK6>, 119 <&infracfg CLK_INFRA_66M_PWM_CK7>, 120 <&infracfg CLK_INFRA_66M_PWM_CK8>; 121 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 122 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; 123 #pwm-cells = <2>; 124 status = "disabled"; 125 }; 126 127 i2c@11003000 { 128 compatible = "mediatek,mt7981-i2c"; 129 reg = <0 0x11003000 0 0x1000>, 130 <0 0x10217080 0 0x80>; 131 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 133 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 134 clock-names = "main", "dma"; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 status = "disabled"; 138 }; 139 140 i2c@11004000 { 141 compatible = "mediatek,mt7981-i2c"; 142 reg = <0 0x11004000 0 0x1000>, 143 <0 0x10217100 0 0x80>; 144 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 146 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 147 clock-names = "main", "dma"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 status = "disabled"; 151 }; 152 153 i2c@11005000 { 154 compatible = "mediatek,mt7981-i2c"; 155 reg = <0 0x11005000 0 0x1000>, 156 <0 0x10217180 0 0x80>; 157 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 159 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 160 clock-names = "main", "dma"; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 status = "disabled"; 164 }; 165 166 usb@11190000 { 167 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 168 reg = <0 0x11190000 0 0x2e00>, 169 <0 0x11193e00 0 0x0100>; 170 reg-names = "mac", "ippc"; 171 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&infracfg CLK_INFRA_USB_SYS>, 173 <&infracfg CLK_INFRA_USB_REF>, 174 <&infracfg CLK_INFRA_66M_USB_HCK>, 175 <&infracfg CLK_INFRA_133M_USB_HCK>, 176 <&infracfg CLK_INFRA_USB_XHCI>; 177 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 178 }; 179 180 usb@11200000 { 181 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 182 reg = <0 0x11200000 0 0x2e00>, 183 <0 0x11203e00 0 0x0100>; 184 reg-names = "mac", "ippc"; 185 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, 187 <&infracfg CLK_INFRA_USB_CK_P1>, 188 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, 189 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, 190 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; 191 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 192 }; 193 194 clock-controller@11f40000 { 195 compatible = "mediatek,mt7988-xfi-pll"; 196 reg = <0 0x11f40000 0 0x1000>; 197 resets = <&watchdog 16>; 198 #clock-cells = <1>; 199 }; 200 201 clock-controller@15000000 { 202 compatible = "mediatek,mt7988-ethsys", "syscon"; 203 reg = <0 0x15000000 0 0x1000>; 204 #clock-cells = <1>; 205 #reset-cells = <1>; 206 }; 207 208 clock-controller@15031000 { 209 compatible = "mediatek,mt7988-ethwarp"; 210 reg = <0 0x15031000 0 0x1000>; 211 #clock-cells = <1>; 212 #reset-cells = <1>; 213 }; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupt-parent = <&gic>; 219 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 220 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 221 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 222 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 223 }; 224}; 225