xref: /linux/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/pinctrl/mt65xx.h>
9
10#include "mt7986a.dtsi"
11
12/ {
13	model = "MediaTek MT7986a RFB";
14	chassis-type = "embedded";
15	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
16
17	aliases {
18		serial0 = &uart0;
19	};
20
21	chosen {
22		stdout-path = "serial0:115200n8";
23	};
24
25	memory@40000000 {
26		device_type = "memory";
27		reg = <0 0x40000000 0 0x40000000>;
28	};
29
30	reg_1p8v: regulator-1p8v {
31		compatible = "regulator-fixed";
32		regulator-name = "fixed-1.8V";
33		regulator-min-microvolt = <1800000>;
34		regulator-max-microvolt = <1800000>;
35		regulator-boot-on;
36		regulator-always-on;
37	};
38
39	reg_3p3v: regulator-3p3v {
40		compatible = "regulator-fixed";
41		regulator-name = "fixed-3.3V";
42		regulator-min-microvolt = <3300000>;
43		regulator-max-microvolt = <3300000>;
44		regulator-boot-on;
45		regulator-always-on;
46	};
47};
48
49&crypto {
50	status = "okay";
51};
52
53&eth {
54	status = "okay";
55
56	gmac0: mac@0 {
57		compatible = "mediatek,eth-mac";
58		reg = <0>;
59		phy-mode = "2500base-x";
60
61		fixed-link {
62			speed = <2500>;
63			full-duplex;
64			pause;
65		};
66	};
67
68	mdio: mdio-bus {
69		#address-cells = <1>;
70		#size-cells = <0>;
71	};
72};
73
74&mdio {
75	switch: switch@0 {
76		compatible = "mediatek,mt7531";
77		reg = <31>;
78		reset-gpios = <&pio 5 0>;
79	};
80};
81
82&mmc0 {
83	pinctrl-names = "default", "state_uhs";
84	pinctrl-0 = <&mmc0_pins_default>;
85	pinctrl-1 = <&mmc0_pins_uhs>;
86	bus-width = <8>;
87	max-frequency = <200000000>;
88	cap-mmc-highspeed;
89	mmc-hs200-1_8v;
90	mmc-hs400-1_8v;
91	hs400-ds-delay = <0x14014>;
92	vmmc-supply = <&reg_3p3v>;
93	vqmmc-supply = <&reg_1p8v>;
94	non-removable;
95	no-sd;
96	no-sdio;
97};
98
99&pcie {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pcie_pins>;
102	status = "okay";
103};
104
105&pcie_phy {
106	status = "okay";
107};
108
109&pio {
110	mmc0_pins_default: mmc0-pins {
111		mux {
112			function = "emmc";
113			groups = "emmc_51";
114		};
115		conf-cmd-dat {
116			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
117			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
118			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
119			input-enable;
120			drive-strength = <4>;
121			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
122		};
123		conf-clk {
124			pins = "EMMC_CK";
125			drive-strength = <6>;
126			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
127		};
128		conf-ds {
129			pins = "EMMC_DSL";
130			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
131		};
132		conf-rst {
133			pins = "EMMC_RSTB";
134			drive-strength = <4>;
135			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
136		};
137	};
138
139	mmc0_pins_uhs: mmc0-uhs-pins {
140		mux {
141			function = "emmc";
142			groups = "emmc_51";
143		};
144		conf-cmd-dat {
145			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
146			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
147			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
148			input-enable;
149			drive-strength = <4>;
150			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
151		};
152		conf-clk {
153			pins = "EMMC_CK";
154			drive-strength = <6>;
155			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
156		};
157		conf-ds {
158			pins = "EMMC_DSL";
159			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
160		};
161		conf-rst {
162			pins = "EMMC_RSTB";
163			drive-strength = <4>;
164			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
165		};
166	};
167
168	pcie_pins: pcie-pins {
169		mux {
170			function = "pcie";
171			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
172		};
173	};
174
175	spi_flash_pins: spi-flash-pins {
176		mux {
177			function = "spi";
178			groups = "spi0", "spi0_wp_hold";
179		};
180	};
181
182	spic_pins: spic-pins {
183		mux {
184			function = "spi";
185			groups = "spi1_2";
186		};
187	};
188
189	uart1_pins: uart1-pins {
190		mux {
191			function = "uart";
192			groups = "uart1";
193		};
194	};
195
196	uart2_pins: uart2-pins {
197		mux {
198			function = "uart";
199			groups = "uart2";
200		};
201	};
202
203	wf_2g_5g_pins: wf-2g-5g-pins {
204		mux {
205			function = "wifi";
206			groups = "wf_2g", "wf_5g";
207		};
208		conf {
209			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
210			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
211			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
212			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
213			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
214			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
215			       "WF1_TOP_CLK", "WF1_TOP_DATA";
216			drive-strength = <4>;
217		};
218	};
219
220	wf_dbdc_pins: wf-dbdc-pins {
221		mux {
222			function = "wifi";
223			groups = "wf_dbdc";
224		};
225		conf {
226			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
227			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
228			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
229			       "WF0_TOP_CLK", "WF0_TOP_DATA";
230			drive-strength = <4>;
231		};
232	};
233};
234
235&spi0 {
236	pinctrl-names = "default";
237	pinctrl-0 = <&spi_flash_pins>;
238	cs-gpios = <0>, <0>;
239	status = "okay";
240	spi_nand: spi_nand@0 {
241		compatible = "spi-nand";
242		reg = <0>;
243		spi-max-frequency = <10000000>;
244		spi-tx-buswidth = <4>;
245		spi-rx-buswidth = <4>;
246	};
247};
248
249&spi1 {
250	pinctrl-names = "default";
251	pinctrl-0 = <&spic_pins>;
252	cs-gpios = <0>, <0>;
253	status = "okay";
254};
255
256&ssusb {
257	status = "okay";
258};
259
260&switch {
261	ports {
262		#address-cells = <1>;
263		#size-cells = <0>;
264
265		port@0 {
266			reg = <0>;
267			label = "lan0";
268		};
269
270		port@1 {
271			reg = <1>;
272			label = "lan1";
273		};
274
275		port@2 {
276			reg = <2>;
277			label = "lan2";
278		};
279
280		port@3 {
281			reg = <3>;
282			label = "lan3";
283		};
284
285		port@4 {
286			reg = <4>;
287			label = "lan4";
288		};
289
290		port@6 {
291			reg = <6>;
292			label = "cpu";
293			ethernet = <&gmac0>;
294			phy-mode = "2500base-x";
295
296			fixed-link {
297				speed = <2500>;
298				full-duplex;
299				pause;
300			};
301		};
302	};
303};
304
305&uart0 {
306	status = "okay";
307};
308
309&uart1 {
310	pinctrl-names = "default";
311	pinctrl-0 = <&uart1_pins>;
312	status = "okay";
313};
314
315&uart2 {
316	pinctrl-names = "default";
317	pinctrl-0 = <&uart2_pins>;
318	status = "okay";
319};
320
321&usb_phy {
322	status = "okay";
323};
324
325&wifi {
326	status = "okay";
327	pinctrl-names = "default", "dbdc";
328	pinctrl-0 = <&wf_2g_5g_pins>;
329	pinctrl-1 = <&wf_dbdc_pins>;
330};
331