1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7981-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/leds/common.h> 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/reset/mt7986-resets.h> 8 9/ { 10 compatible = "mediatek,mt7981b"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 compatible = "arm,cortex-a53"; 21 reg = <0x0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 }; 25 26 cpu@1 { 27 compatible = "arm,cortex-a53"; 28 reg = <0x1>; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 }; 32 }; 33 34 oscillator-40m { 35 compatible = "fixed-clock"; 36 clock-frequency = <40000000>; 37 clock-output-names = "clkxtal"; 38 #clock-cells = <0>; 39 }; 40 41 psci { 42 compatible = "arm,psci-1.0"; 43 method = "smc"; 44 }; 45 46 reserved-memory { 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 51 wo_boot: wo-boot@15194000 { 52 reg = <0 0x15194000 0 0x1000>; 53 no-map; 54 }; 55 56 wo_ilm0: wo-ilm@151e0000 { 57 reg = <0 0x151e0000 0 0x8000>; 58 no-map; 59 }; 60 61 wo_dlm0: wo-dlm@151e8000 { 62 reg = <0 0x151e8000 0 0x2000>; 63 no-map; 64 }; 65 66 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 67 secmon_reserved: secmon@43000000 { 68 reg = <0 0x43000000 0 0x30000>; 69 no-map; 70 }; 71 72 wmcpu_emi: wmcpu-reserved@47c80000 { 73 reg = <0 0x47c80000 0 0x100000>; 74 no-map; 75 }; 76 77 wo_emi0: wo-emi@47d80000 { 78 reg = <0 0x47d80000 0 0x40000>; 79 no-map; 80 }; 81 82 wo_data: wo-data@47dc0000 { 83 reg = <0 0x47dc0000 0 0x240000>; 84 no-map; 85 }; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 ranges; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 94 gic: interrupt-controller@c000000 { 95 compatible = "arm,gic-v3"; 96 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 97 <0 0x0c080000 0 0x200000>; /* GICR */ 98 interrupt-parent = <&gic>; 99 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-controller; 101 #interrupt-cells = <3>; 102 }; 103 104 infracfg: clock-controller@10001000 { 105 compatible = "mediatek,mt7981-infracfg", "syscon"; 106 reg = <0 0x10001000 0 0x1000>; 107 #clock-cells = <1>; 108 }; 109 110 topckgen: clock-controller@1001b000 { 111 compatible = "mediatek,mt7981-topckgen", "syscon"; 112 reg = <0 0x1001b000 0 0x1000>; 113 #clock-cells = <1>; 114 }; 115 116 watchdog: watchdog@1001c000 { 117 compatible = "mediatek,mt7986-wdt"; 118 reg = <0 0x1001c000 0 0x1000>; 119 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 120 #reset-cells = <1>; 121 }; 122 123 apmixedsys: clock-controller@1001e000 { 124 compatible = "mediatek,mt7981-apmixedsys"; 125 reg = <0 0x1001e000 0 0x1000>; 126 #clock-cells = <1>; 127 }; 128 129 pwm: pwm@10048000 { 130 compatible = "mediatek,mt7981-pwm"; 131 reg = <0 0x10048000 0 0x1000>; 132 clocks = <&infracfg CLK_INFRA_PWM_STA>, 133 <&infracfg CLK_INFRA_PWM_HCK>, 134 <&infracfg CLK_INFRA_PWM1_CK>, 135 <&infracfg CLK_INFRA_PWM2_CK>, 136 <&infracfg CLK_INFRA_PWM3_CK>; 137 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 138 #pwm-cells = <2>; 139 }; 140 141 sgmiisys0: syscon@10060000 { 142 compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; 143 reg = <0 0x10060000 0 0x1000>; 144 #clock-cells = <1>; 145 }; 146 147 sgmiisys1: syscon@10070000 { 148 compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; 149 reg = <0 0x10070000 0 0x1000>; 150 #clock-cells = <1>; 151 }; 152 153 uart0: serial@11002000 { 154 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 155 reg = <0 0x11002000 0 0x100>; 156 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "uart", "wakeup"; 158 clocks = <&infracfg CLK_INFRA_UART0_SEL>, 159 <&infracfg CLK_INFRA_UART0_CK>; 160 clock-names = "baud", "bus"; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&uart0_pins>; 163 status = "disabled"; 164 }; 165 166 uart1: serial@11003000 { 167 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 168 reg = <0 0x11003000 0 0x100>; 169 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "uart", "wakeup"; 171 clocks = <&infracfg CLK_INFRA_UART1_SEL>, 172 <&infracfg CLK_INFRA_UART1_CK>; 173 clock-names = "baud", "bus"; 174 status = "disabled"; 175 }; 176 177 uart2: serial@11004000 { 178 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; 179 reg = <0 0x11004000 0 0x100>; 180 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "uart", "wakeup"; 182 clocks = <&infracfg CLK_INFRA_UART2_SEL>, 183 <&infracfg CLK_INFRA_UART2_CK>; 184 clock-names = "baud", "bus"; 185 status = "disabled"; 186 }; 187 188 i2c@11007000 { 189 compatible = "mediatek,mt7981-i2c"; 190 reg = <0 0x11007000 0 0x1000>, 191 <0 0x10217080 0 0x80>; 192 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 194 <&infracfg CLK_INFRA_AP_DMA_CK>, 195 <&infracfg CLK_INFRA_I2C_MCK_CK>, 196 <&infracfg CLK_INFRA_I2C_PCK_CK>; 197 clock-names = "main", "dma", "arb", "pmic"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi2: spi@11009000 { 204 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 205 reg = <0 0x11009000 0 0x1000>; 206 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&topckgen CLK_TOP_CB_M_D2>, 208 <&topckgen CLK_TOP_SPI_SEL>, 209 <&infracfg CLK_INFRA_SPI2_CK>, 210 <&infracfg CLK_INFRA_SPI2_HCK_CK>; 211 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 status = "disabled"; 215 }; 216 217 spi@1100a000 { 218 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 219 reg = <0 0x1100a000 0 0x1000>; 220 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&topckgen CLK_TOP_CB_M_D2>, 222 <&topckgen CLK_TOP_SPI_SEL>, 223 <&infracfg CLK_INFRA_SPI0_CK>, 224 <&infracfg CLK_INFRA_SPI0_HCK_CK>; 225 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 spi@1100b000 { 232 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 233 reg = <0 0x1100b000 0 0x1000>; 234 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&topckgen CLK_TOP_CB_M_D2>, 236 <&topckgen CLK_TOP_SPI_SEL>, 237 <&infracfg CLK_INFRA_SPI1_CK>, 238 <&infracfg CLK_INFRA_SPI1_HCK_CK>; 239 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 status = "disabled"; 243 }; 244 245 thermal@1100c800 { 246 compatible = "mediatek,mt7981-thermal", 247 "mediatek,mt7986-thermal"; 248 reg = <0 0x1100c800 0 0x800>; 249 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&infracfg CLK_INFRA_THERM_CK>, 251 <&infracfg CLK_INFRA_ADC_26M_CK>; 252 clock-names = "therm", "auxadc"; 253 nvmem-cells = <&thermal_calibration>; 254 nvmem-cell-names = "calibration-data"; 255 #thermal-sensor-cells = <1>; 256 mediatek,auxadc = <&auxadc>; 257 mediatek,apmixedsys = <&apmixedsys>; 258 }; 259 260 auxadc: adc@1100d000 { 261 compatible = "mediatek,mt7981-auxadc", 262 "mediatek,mt7986-auxadc"; 263 reg = <0 0x1100d000 0 0x1000>; 264 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; 265 clock-names = "main"; 266 #io-channel-cells = <1>; 267 status = "disabled"; 268 }; 269 270 xhci: usb@11200000 { 271 compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; 272 reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 273 reg-names = "mac", "ippc"; 274 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, 275 <&infracfg CLK_INFRA_IUSB_CK>, 276 <&infracfg CLK_INFRA_IUSB_133_CK>, 277 <&infracfg CLK_INFRA_IUSB_66M_CK>, 278 <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 279 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 280 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 281 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 282 status = "disabled"; 283 }; 284 285 pcie: pcie@11280000 { 286 compatible = "mediatek,mt7981-pcie", 287 "mediatek,mt8192-pcie"; 288 reg = <0 0x11280000 0 0x4000>; 289 reg-names = "pcie-mac"; 290 ranges = <0x82000000 0 0x20000000 291 0x0 0x20000000 0 0x10000000>; 292 bus-range = <0x00 0xff>; 293 clocks = <&infracfg CLK_INFRA_IPCIE_CK>, 294 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, 295 <&infracfg CLK_INFRA_IPCIER_CK>, 296 <&infracfg CLK_INFRA_IPCIEB_CK>; 297 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; 298 device_type = "pci"; 299 phys = <&u3port0 PHY_TYPE_PCIE>; 300 phy-names = "pcie-phy"; 301 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-map-mask = <0 0 0 7>; 303 interrupt-map = <0 0 0 1 &pcie_intc 0>, 304 <0 0 0 2 &pcie_intc 1>, 305 <0 0 0 3 &pcie_intc 2>, 306 <0 0 0 4 &pcie_intc 3>; 307 #address-cells = <3>; 308 #interrupt-cells = <1>; 309 #size-cells = <2>; 310 status = "disabled"; 311 312 pcie_intc: interrupt-controller { 313 interrupt-controller; 314 #address-cells = <0>; 315 #interrupt-cells = <1>; 316 }; 317 }; 318 319 pio: pinctrl@11d00000 { 320 compatible = "mediatek,mt7981-pinctrl"; 321 reg = <0 0x11d00000 0 0x1000>, 322 <0 0x11c00000 0 0x1000>, 323 <0 0x11c10000 0 0x1000>, 324 <0 0x11d20000 0 0x1000>, 325 <0 0x11e00000 0 0x1000>, 326 <0 0x11e20000 0 0x1000>, 327 <0 0x11f00000 0 0x1000>, 328 <0 0x11f10000 0 0x1000>, 329 <0 0x1000b000 0 0x1000>; 330 reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", 331 "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; 332 interrupt-controller; 333 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-parent = <&gic>; 335 gpio-ranges = <&pio 0 0 57>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 #interrupt-cells = <2>; 339 340 uart0_pins: uart0-pins { 341 mux { 342 function = "uart"; 343 groups = "uart0"; 344 }; 345 }; 346 }; 347 348 topmisc: topmisc@11d10000 { 349 compatible = "mediatek,mt7981-topmisc", "syscon"; 350 reg = <0 0x11d10000 0 0x10000>; 351 #clock-cells = <1>; 352 }; 353 354 usb_phy: t-phy@11e10000 { 355 compatible = "mediatek,mt7981-tphy", 356 "mediatek,generic-tphy-v2"; 357 ranges = <0 0 0x11e10000 0x1700>; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 status = "disabled"; 361 362 u2port0: usb-phy@0 { 363 reg = <0x0 0x700>; 364 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; 365 clock-names = "ref"; 366 #phy-cells = <1>; 367 }; 368 369 u3port0: usb-phy@700 { 370 reg = <0x700 0x900>; 371 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; 372 clock-names = "ref"; 373 #phy-cells = <1>; 374 mediatek,syscon-type = <&topmisc 0x218 0>; 375 }; 376 }; 377 378 efuse@11f20000 { 379 compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; 380 reg = <0 0x11f20000 0 0x1000>; 381 #address-cells = <1>; 382 #size-cells = <1>; 383 384 soc-uuid@140 { 385 reg = <0x140 0x10>; 386 }; 387 388 thermal_calibration: thermal-calib@274 { 389 reg = <0x274 0xc>; 390 }; 391 392 phy_calibration: phy-calib@8dc { 393 reg = <0x8dc 0x10>; 394 }; 395 }; 396 397 ethsys: clock-controller@15000000 { 398 compatible = "mediatek,mt7981-ethsys", "syscon"; 399 reg = <0 0x15000000 0 0x1000>; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 }; 403 404 wed: wed@15010000 { 405 compatible = "mediatek,mt7981-wed", 406 "syscon"; 407 reg = <0 0x15010000 0 0x1000>; 408 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 409 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, 410 <&wo_data>, <&wo_boot>; 411 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 412 "wo-data", "wo-boot"; 413 mediatek,wo-ccif = <&wo_ccif0>; 414 }; 415 416 eth: ethernet@15100000 { 417 compatible = "mediatek,mt7981-eth"; 418 reg = <0 0x15100000 0 0x40000>; 419 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 420 <&topckgen CLK_TOP_SGM_325M_SEL>; 421 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, 422 <&topckgen CLK_TOP_CB_SGM_325M>; 423 clocks = <ðsys CLK_ETH_FE_EN>, 424 <ðsys CLK_ETH_GP2_EN>, 425 <ðsys CLK_ETH_GP1_EN>, 426 <ðsys CLK_ETH_WOCPU0_EN>, 427 <&topckgen CLK_TOP_SGM_REG>, 428 <&sgmiisys0 CLK_SGM0_TX_EN>, 429 <&sgmiisys0 CLK_SGM0_RX_EN>, 430 <&sgmiisys0 CLK_SGM0_CK0_EN>, 431 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, 432 <&sgmiisys1 CLK_SGM1_TX_EN>, 433 <&sgmiisys1 CLK_SGM1_RX_EN>, 434 <&sgmiisys1 CLK_SGM1_CK1_EN>, 435 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, 436 <&topckgen CLK_TOP_NETSYS_SEL>, 437 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 438 clock-names = "fe", "gp2", "gp1", "wocpu0", 439 "sgmii_ck", 440 "sgmii_tx250m", "sgmii_rx250m", 441 "sgmii_cdr_ref", "sgmii_cdr_fb", 442 "sgmii2_tx250m", "sgmii2_rx250m", 443 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 444 "netsys0", "netsys1"; 445 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", 454 "pdma1", "pdma2", "pdma3"; 455 sram = <ð_sram>; 456 mediatek,ethsys = <ðsys>; 457 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 458 mediatek,infracfg = <&topmisc>; 459 mediatek,wed = <&wed>; 460 status = "disabled"; 461 462 mdio_bus: mdio-bus { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 int_gbe_phy: ethernet-phy@0 { 467 compatible = "ethernet-phy-ieee802.3-c22"; 468 reg = <0>; 469 phy-mode = "gmii"; 470 phy-is-integrated; 471 nvmem-cells = <&phy_calibration>; 472 nvmem-cell-names = "phy-cal-data"; 473 }; 474 }; 475 }; 476 477 eth_sram: sram@15140000 { 478 compatible = "mmio-sram"; 479 reg = <0 0x15140000 0 0x40000>; 480 ranges = <0 0x15140000 0 0x40000>; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 }; 484 485 wo_ccif0: syscon@151a5000 { 486 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 487 reg = <0 0x151a5000 0 0x1000>; 488 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 489 }; 490 491 wifi: wifi@18000000 { 492 compatible = "mediatek,mt7981-wmac"; 493 reg = <0 0x18000000 0 0x1000000>, 494 <0 0x10003000 0 0x1000>, 495 <0 0x11d10000 0 0x1000>; 496 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, 501 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 502 clock-names = "mcu", "ap2conn"; 503 memory-region = <&wmcpu_emi>; 504 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 505 reset-names = "consys"; 506 status = "disabled"; 507 }; 508 }; 509 510 timer { 511 compatible = "arm,armv8-timer"; 512 interrupt-parent = <&gic>; 513 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 514 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 515 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 516 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 517 }; 518}; 519