1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7981-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/reset/mt7986-resets.h> 6 7/ { 8 compatible = "mediatek,mt7981b"; 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "arm,cortex-a53"; 19 reg = <0x0>; 20 device_type = "cpu"; 21 enable-method = "psci"; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a53"; 26 reg = <0x1>; 27 device_type = "cpu"; 28 enable-method = "psci"; 29 }; 30 }; 31 32 oscillator-40m { 33 compatible = "fixed-clock"; 34 clock-frequency = <40000000>; 35 clock-output-names = "clkxtal"; 36 #clock-cells = <0>; 37 }; 38 39 psci { 40 compatible = "arm,psci-1.0"; 41 method = "smc"; 42 }; 43 44 soc { 45 compatible = "simple-bus"; 46 ranges; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 50 gic: interrupt-controller@c000000 { 51 compatible = "arm,gic-v3"; 52 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 53 <0 0x0c080000 0 0x200000>; /* GICR */ 54 interrupt-parent = <&gic>; 55 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-controller; 57 #interrupt-cells = <3>; 58 }; 59 60 infracfg: clock-controller@10001000 { 61 compatible = "mediatek,mt7981-infracfg", "syscon"; 62 reg = <0 0x10001000 0 0x1000>; 63 #clock-cells = <1>; 64 }; 65 66 topckgen: clock-controller@1001b000 { 67 compatible = "mediatek,mt7981-topckgen", "syscon"; 68 reg = <0 0x1001b000 0 0x1000>; 69 #clock-cells = <1>; 70 }; 71 72 watchdog: watchdog@1001c000 { 73 compatible = "mediatek,mt7986-wdt"; 74 reg = <0 0x1001c000 0 0x1000>; 75 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 76 #reset-cells = <1>; 77 }; 78 79 clock-controller@1001e000 { 80 compatible = "mediatek,mt7981-apmixedsys"; 81 reg = <0 0x1001e000 0 0x1000>; 82 #clock-cells = <1>; 83 }; 84 85 pwm@10048000 { 86 compatible = "mediatek,mt7981-pwm"; 87 reg = <0 0x10048000 0 0x1000>; 88 clocks = <&infracfg CLK_INFRA_PWM_STA>, 89 <&infracfg CLK_INFRA_PWM_HCK>, 90 <&infracfg CLK_INFRA_PWM1_CK>, 91 <&infracfg CLK_INFRA_PWM2_CK>, 92 <&infracfg CLK_INFRA_PWM3_CK>; 93 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 94 #pwm-cells = <2>; 95 }; 96 97 i2c@11007000 { 98 compatible = "mediatek,mt7981-i2c"; 99 reg = <0 0x11007000 0 0x1000>, 100 <0 0x10217080 0 0x80>; 101 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 103 <&infracfg CLK_INFRA_AP_DMA_CK>, 104 <&infracfg CLK_INFRA_I2C_MCK_CK>, 105 <&infracfg CLK_INFRA_I2C_PCK_CK>; 106 clock-names = "main", "dma", "arb", "pmic"; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 status = "disabled"; 110 }; 111 112 spi@11009000 { 113 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 114 reg = <0 0x11009000 0 0x1000>; 115 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&topckgen CLK_TOP_CB_M_D2>, 117 <&topckgen CLK_TOP_SPI_SEL>, 118 <&infracfg CLK_INFRA_SPI2_CK>, 119 <&infracfg CLK_INFRA_SPI2_HCK_CK>; 120 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 status = "disabled"; 124 }; 125 126 spi@1100a000 { 127 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 128 reg = <0 0x1100a000 0 0x1000>; 129 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&topckgen CLK_TOP_CB_M_D2>, 131 <&topckgen CLK_TOP_SPI_SEL>, 132 <&infracfg CLK_INFRA_SPI0_CK>, 133 <&infracfg CLK_INFRA_SPI0_HCK_CK>; 134 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 status = "disabled"; 138 }; 139 140 spi@1100b000 { 141 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; 142 reg = <0 0x1100b000 0 0x1000>; 143 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&topckgen CLK_TOP_CB_M_D2>, 145 <&topckgen CLK_TOP_SPI_SEL>, 146 <&infracfg CLK_INFRA_SPI1_CK>, 147 <&infracfg CLK_INFRA_SPI1_HCK_CK>; 148 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 status = "disabled"; 152 }; 153 154 pio: pinctrl@11d00000 { 155 compatible = "mediatek,mt7981-pinctrl"; 156 reg = <0 0x11d00000 0 0x1000>, 157 <0 0x11c00000 0 0x1000>, 158 <0 0x11c10000 0 0x1000>, 159 <0 0x11d20000 0 0x1000>, 160 <0 0x11e00000 0 0x1000>, 161 <0 0x11e20000 0 0x1000>, 162 <0 0x11f00000 0 0x1000>, 163 <0 0x11f10000 0 0x1000>, 164 <0 0x1000b000 0 0x1000>; 165 reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", 166 "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; 167 interrupt-controller; 168 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-parent = <&gic>; 170 gpio-ranges = <&pio 0 0 56>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 #interrupt-cells = <2>; 174 }; 175 176 efuse@11f20000 { 177 compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; 178 reg = <0 0x11f20000 0 0x1000>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 }; 182 183 clock-controller@15000000 { 184 compatible = "mediatek,mt7981-ethsys", "syscon"; 185 reg = <0 0x15000000 0 0x1000>; 186 #clock-cells = <1>; 187 #reset-cells = <1>; 188 }; 189 190 wifi@18000000 { 191 compatible = "mediatek,mt7981-wmac"; 192 reg = <0 0x18000000 0 0x1000000>, 193 <0 0x10003000 0 0x1000>, 194 <0 0x11d10000 0 0x1000>; 195 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, 200 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 201 clock-names = "mcu", "ap2conn"; 202 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 203 reset-names = "consys"; 204 }; 205 }; 206 207 timer { 208 compatible = "arm,armv8-timer"; 209 interrupt-parent = <&gic>; 210 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 211 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 212 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 213 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 214 }; 215}; 216