xref: /linux/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts (revision 88872790923e2d80edf29a00b4e440f1473fa8f5) 
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "MediaTek MT7622 RFB1 board";
18	chassis-type = "embedded";
19	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
28	};
29
30	cpus {
31		cpu@0 {
32			proc-supply = <&mt6380_vcpu_reg>;
33			sram-supply = <&mt6380_vm_reg>;
34		};
35
36		cpu@1 {
37			proc-supply = <&mt6380_vcpu_reg>;
38			sram-supply = <&mt6380_vm_reg>;
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		key-factory {
46			label = "factory";
47			linux,code = <BTN_0>;
48			gpios = <&pio 0 0>;
49		};
50
51		key-wps {
52			label = "wps";
53			linux,code = <KEY_WPS_BUTTON>;
54			gpios = <&pio 102 0>;
55		};
56	};
57
58	memory {
59		reg = <0 0x40000000 0 0x20000000>;
60	};
61
62	reg_1p8v: regulator-1p8v {
63		compatible = "regulator-fixed";
64		regulator-name = "fixed-1.8V";
65		regulator-min-microvolt = <1800000>;
66		regulator-max-microvolt = <1800000>;
67		regulator-always-on;
68	};
69
70	reg_3p3v: regulator-3p3v {
71		compatible = "regulator-fixed";
72		regulator-name = "fixed-3.3V";
73		regulator-min-microvolt = <3300000>;
74		regulator-max-microvolt = <3300000>;
75		regulator-boot-on;
76		regulator-always-on;
77	};
78
79	reg_5v: regulator-5v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-5V";
82		regulator-min-microvolt = <5000000>;
83		regulator-max-microvolt = <5000000>;
84		regulator-boot-on;
85		regulator-always-on;
86	};
87};
88
89&bch {
90	status = "disabled";
91};
92
93&btif {
94	status = "okay";
95};
96
97&cir {
98	pinctrl-names = "default";
99	pinctrl-0 = <&irrx_pins>;
100	status = "okay";
101};
102
103&eth {
104	pinctrl-names = "default";
105	pinctrl-0 = <&eth_pins>;
106	status = "okay";
107
108	gmac0: mac@0 {
109		compatible = "mediatek,eth-mac";
110		reg = <0>;
111		phy-mode = "2500base-x";
112
113		fixed-link {
114			speed = <2500>;
115			full-duplex;
116			pause;
117		};
118	};
119
120	mdio-bus {
121		#address-cells = <1>;
122		#size-cells = <0>;
123
124		switch@0 {
125			compatible = "mediatek,mt7531";
126			reg = <0>;
127			reset-gpios = <&pio 54 0>;
128
129			ports {
130				#address-cells = <1>;
131				#size-cells = <0>;
132
133				port@0 {
134					reg = <0>;
135					label = "lan0";
136				};
137
138				port@1 {
139					reg = <1>;
140					label = "lan1";
141				};
142
143				port@2 {
144					reg = <2>;
145					label = "lan2";
146				};
147
148				port@3 {
149					reg = <3>;
150					label = "lan3";
151				};
152
153				port@4 {
154					reg = <4>;
155					label = "wan";
156				};
157
158				port@6 {
159					reg = <6>;
160					label = "cpu";
161					ethernet = <&gmac0>;
162					phy-mode = "2500base-x";
163
164					fixed-link {
165						speed = <2500>;
166						full-duplex;
167						pause;
168					};
169				};
170			};
171		};
172
173	};
174};
175
176&i2c1 {
177	pinctrl-names = "default";
178	pinctrl-0 = <&i2c1_pins>;
179	status = "okay";
180};
181
182&i2c2 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&i2c2_pins>;
185	status = "okay";
186};
187
188&mmc0 {
189	pinctrl-names = "default", "state_uhs";
190	pinctrl-0 = <&emmc_pins_default>;
191	pinctrl-1 = <&emmc_pins_uhs>;
192	status = "okay";
193	bus-width = <8>;
194	max-frequency = <50000000>;
195	cap-mmc-highspeed;
196	mmc-hs200-1_8v;
197	vmmc-supply = <&reg_3p3v>;
198	vqmmc-supply = <&reg_1p8v>;
199	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
200	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
201	non-removable;
202};
203
204&mmc1 {
205	pinctrl-names = "default", "state_uhs";
206	pinctrl-0 = <&sd0_pins_default>;
207	pinctrl-1 = <&sd0_pins_uhs>;
208	status = "okay";
209	bus-width = <4>;
210	max-frequency = <50000000>;
211	cap-sd-highspeed;
212	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
213	vmmc-supply = <&reg_3p3v>;
214	vqmmc-supply = <&reg_3p3v>;
215	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
216	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
217};
218
219&nandc {
220	pinctrl-names = "default";
221	pinctrl-0 = <&parallel_nand_pins>;
222	status = "disabled";
223};
224
225&nor_flash {
226	pinctrl-names = "default";
227	pinctrl-0 = <&spi_nor_pins>;
228	status = "disabled";
229
230	flash@0 {
231		compatible = "jedec,spi-nor";
232		reg = <0>;
233	};
234};
235
236&pcie0 {
237	pinctrl-names = "default";
238	pinctrl-0 = <&pcie0_pins>;
239	status = "okay";
240};
241
242&pio {
243	/* eMMC is shared pin with parallel NAND */
244	emmc_pins_default: emmc-pins-default {
245		mux {
246			function = "emmc", "emmc_rst";
247			groups = "emmc";
248		};
249
250		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
251		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
252		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
253		 */
254		conf-cmd-dat {
255			pins = "NDL0", "NDL1", "NDL2",
256			       "NDL3", "NDL4", "NDL5",
257			       "NDL6", "NDL7", "NRB";
258			input-enable;
259			bias-pull-up;
260		};
261
262		conf-clk {
263			pins = "NCLE";
264			bias-pull-down;
265		};
266	};
267
268	emmc_pins_uhs: emmc-pins-uhs {
269		mux {
270			function = "emmc";
271			groups = "emmc";
272		};
273
274		conf-cmd-dat {
275			pins = "NDL0", "NDL1", "NDL2",
276			       "NDL3", "NDL4", "NDL5",
277			       "NDL6", "NDL7", "NRB";
278			input-enable;
279			drive-strength = <4>;
280			bias-pull-up;
281		};
282
283		conf-clk {
284			pins = "NCLE";
285			drive-strength = <4>;
286			bias-pull-down;
287		};
288	};
289
290	eth_pins: eth-pins {
291		mux {
292			function = "eth";
293			groups = "mdc_mdio", "rgmii_via_gmac2";
294		};
295	};
296
297	i2c1_pins: i2c1-pins {
298		mux {
299			function = "i2c";
300			groups = "i2c1_0";
301		};
302	};
303
304	i2c2_pins: i2c2-pins {
305		mux {
306			function = "i2c";
307			groups = "i2c2_0";
308		};
309	};
310
311	i2s1_pins: i2s1-pins {
312		mux {
313			function = "i2s";
314			groups =  "i2s_out_mclk_bclk_ws",
315				  "i2s1_in_data",
316				  "i2s1_out_data";
317		};
318
319		conf {
320			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
321			       "I2S_WS", "I2S_MCLK";
322			drive-strength = <12>;
323			bias-pull-down;
324		};
325	};
326
327	irrx_pins: irrx-pins {
328		mux {
329			function = "ir";
330			groups = "ir_1_rx";
331		};
332	};
333
334	irtx_pins: irtx-pins {
335		mux {
336			function = "ir";
337			groups = "ir_1_tx";
338		};
339	};
340
341	/* Parallel nand is shared pin with eMMC */
342	parallel_nand_pins: parallel-nand-pins {
343		mux {
344			function = "flash";
345			groups = "par_nand";
346		};
347	};
348
349	pcie0_pins: pcie0-pins {
350		mux {
351			function = "pcie";
352			groups = "pcie0_pad_perst",
353				 "pcie0_1_waken",
354				 "pcie0_1_clkreq";
355		};
356	};
357
358	pcie1_pins: pcie1-pins {
359		mux {
360			function = "pcie";
361			groups = "pcie1_pad_perst",
362				 "pcie1_0_waken",
363				 "pcie1_0_clkreq";
364		};
365	};
366
367	pmic_bus_pins: pmic-bus-pins {
368		mux {
369			function = "pmic";
370			groups = "pmic_bus";
371		};
372	};
373
374	pwm7_pins: pwm1-2-pins {
375		mux {
376			function = "pwm";
377			groups = "pwm_ch7_2";
378		};
379	};
380
381	wled_pins: wled-pins {
382		mux {
383			function = "led";
384			groups = "wled";
385		};
386	};
387
388	sd0_pins_default: sd0-pins-default {
389		mux {
390			function = "sd";
391			groups = "sd_0";
392		};
393
394		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
395		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
396		 *  DAT2, DAT3, CMD, CLK for SD respectively.
397		 */
398		conf-cmd-data {
399			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
400			       "I2S2_IN","I2S4_OUT";
401			input-enable;
402			drive-strength = <8>;
403			bias-pull-up;
404		};
405		conf-clk {
406			pins = "I2S3_OUT";
407			drive-strength = <12>;
408			bias-pull-down;
409		};
410		conf-cd {
411			pins = "TXD3";
412			bias-pull-up;
413		};
414	};
415
416	sd0_pins_uhs: sd0-pins-uhs {
417		mux {
418			function = "sd";
419			groups = "sd_0";
420		};
421
422		conf-cmd-data {
423			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
424			       "I2S2_IN","I2S4_OUT";
425			input-enable;
426			bias-pull-up;
427		};
428
429		conf-clk {
430			pins = "I2S3_OUT";
431			bias-pull-down;
432		};
433	};
434
435	/* Serial NAND is shared pin with SPI-NOR */
436	serial_nand_pins: serial-nand-pins {
437		mux {
438			function = "flash";
439			groups = "snfi";
440		};
441	};
442
443	spic0_pins: spic0-pins {
444		mux {
445			function = "spi";
446			groups = "spic0_0";
447		};
448	};
449
450	spic1_pins: spic1-pins {
451		mux {
452			function = "spi";
453			groups = "spic1_0";
454		};
455	};
456
457	/* SPI-NOR is shared pin with serial NAND */
458	spi_nor_pins: spi-nor-pins {
459		mux {
460			function = "flash";
461			groups = "spi_nor";
462		};
463	};
464
465	/* serial NAND is shared pin with SPI-NOR */
466	serial_nand_pins: serial-nand-pins {
467		mux {
468			function = "flash";
469			groups = "snfi";
470		};
471	};
472
473	uart0_pins: uart0-pins {
474		mux {
475			function = "uart";
476			groups = "uart0_0_tx_rx" ;
477		};
478	};
479
480	uart2_pins: uart2-pins {
481		mux {
482			function = "uart";
483			groups = "uart2_1_tx_rx" ;
484		};
485	};
486
487	watchdog_pins: watchdog-pins {
488		mux {
489			function = "watchdog";
490			groups = "watchdog";
491		};
492	};
493
494	wmac_pins: wmac-pins {
495		mux {
496			function = "antsel";
497			groups = "antsel0", "antsel1", "antsel2", "antsel3",
498				 "antsel4", "antsel5", "antsel6", "antsel7",
499				 "antsel8", "antsel9", "antsel12", "antsel13",
500				 "antsel14", "antsel15", "antsel16", "antsel17";
501		};
502	};
503};
504
505&pwm {
506	pinctrl-names = "default";
507	pinctrl-0 = <&pwm7_pins>;
508	status = "okay";
509};
510
511&pwrap {
512	pinctrl-names = "default";
513	pinctrl-0 = <&pmic_bus_pins>;
514
515	status = "okay";
516};
517
518&sata {
519	status = "okay";
520};
521
522&sata_phy {
523	status = "okay";
524};
525
526&spi0 {
527	pinctrl-names = "default";
528	pinctrl-0 = <&spic0_pins>;
529	status = "okay";
530};
531
532&spi1 {
533	pinctrl-names = "default";
534	pinctrl-0 = <&spic1_pins>;
535	status = "okay";
536};
537
538&ssusb {
539	vusb33-supply = <&reg_3p3v>;
540	vbus-supply = <&reg_5v>;
541	status = "okay";
542};
543
544&u3phy {
545	status = "okay";
546};
547
548&uart0 {
549	pinctrl-names = "default";
550	pinctrl-0 = <&uart0_pins>;
551	status = "okay";
552};
553
554&uart2 {
555	pinctrl-names = "default";
556	pinctrl-0 = <&uart2_pins>;
557	status = "okay";
558};
559
560&watchdog {
561	pinctrl-names = "default";
562	pinctrl-0 = <&watchdog_pins>;
563	status = "okay";
564};
565
566&wmac {
567	pinctrl-names = "default";
568	pinctrl-0 = <&wmac_pins>;
569	status = "okay";
570};
571