xref: /linux/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts (revision 702648721db590b3425c31ade294000e18808345) 
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "MediaTek MT7622 RFB1 board";
18	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
27	};
28
29	cpus {
30		cpu@0 {
31			proc-supply = <&mt6380_vcpu_reg>;
32			sram-supply = <&mt6380_vm_reg>;
33		};
34
35		cpu@1 {
36			proc-supply = <&mt6380_vcpu_reg>;
37			sram-supply = <&mt6380_vm_reg>;
38		};
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43
44		key-factory {
45			label = "factory";
46			linux,code = <BTN_0>;
47			gpios = <&pio 0 0>;
48		};
49
50		key-wps {
51			label = "wps";
52			linux,code = <KEY_WPS_BUTTON>;
53			gpios = <&pio 102 0>;
54		};
55	};
56
57	memory {
58		reg = <0 0x40000000 0 0x20000000>;
59	};
60
61	reg_1p8v: regulator-1p8v {
62		compatible = "regulator-fixed";
63		regulator-name = "fixed-1.8V";
64		regulator-min-microvolt = <1800000>;
65		regulator-max-microvolt = <1800000>;
66		regulator-always-on;
67	};
68
69	reg_3p3v: regulator-3p3v {
70		compatible = "regulator-fixed";
71		regulator-name = "fixed-3.3V";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74		regulator-boot-on;
75		regulator-always-on;
76	};
77
78	reg_5v: regulator-5v {
79		compatible = "regulator-fixed";
80		regulator-name = "fixed-5V";
81		regulator-min-microvolt = <5000000>;
82		regulator-max-microvolt = <5000000>;
83		regulator-boot-on;
84		regulator-always-on;
85	};
86};
87
88&bch {
89	status = "disabled";
90};
91
92&btif {
93	status = "okay";
94};
95
96&cir {
97	pinctrl-names = "default";
98	pinctrl-0 = <&irrx_pins>;
99	status = "okay";
100};
101
102&eth {
103	pinctrl-names = "default";
104	pinctrl-0 = <&eth_pins>;
105	status = "okay";
106
107	gmac0: mac@0 {
108		compatible = "mediatek,eth-mac";
109		reg = <0>;
110		phy-mode = "2500base-x";
111
112		fixed-link {
113			speed = <2500>;
114			full-duplex;
115			pause;
116		};
117	};
118
119	mdio-bus {
120		#address-cells = <1>;
121		#size-cells = <0>;
122
123		switch@0 {
124			compatible = "mediatek,mt7531";
125			reg = <0>;
126			reset-gpios = <&pio 54 0>;
127
128			ports {
129				#address-cells = <1>;
130				#size-cells = <0>;
131
132				port@0 {
133					reg = <0>;
134					label = "lan0";
135				};
136
137				port@1 {
138					reg = <1>;
139					label = "lan1";
140				};
141
142				port@2 {
143					reg = <2>;
144					label = "lan2";
145				};
146
147				port@3 {
148					reg = <3>;
149					label = "lan3";
150				};
151
152				port@4 {
153					reg = <4>;
154					label = "wan";
155				};
156
157				port@6 {
158					reg = <6>;
159					label = "cpu";
160					ethernet = <&gmac0>;
161					phy-mode = "2500base-x";
162
163					fixed-link {
164						speed = <2500>;
165						full-duplex;
166						pause;
167					};
168				};
169			};
170		};
171
172	};
173};
174
175&i2c1 {
176	pinctrl-names = "default";
177	pinctrl-0 = <&i2c1_pins>;
178	status = "okay";
179};
180
181&i2c2 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&i2c2_pins>;
184	status = "okay";
185};
186
187&mmc0 {
188	pinctrl-names = "default", "state_uhs";
189	pinctrl-0 = <&emmc_pins_default>;
190	pinctrl-1 = <&emmc_pins_uhs>;
191	status = "okay";
192	bus-width = <8>;
193	max-frequency = <50000000>;
194	cap-mmc-highspeed;
195	mmc-hs200-1_8v;
196	vmmc-supply = <&reg_3p3v>;
197	vqmmc-supply = <&reg_1p8v>;
198	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
199	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
200	non-removable;
201};
202
203&mmc1 {
204	pinctrl-names = "default", "state_uhs";
205	pinctrl-0 = <&sd0_pins_default>;
206	pinctrl-1 = <&sd0_pins_uhs>;
207	status = "okay";
208	bus-width = <4>;
209	max-frequency = <50000000>;
210	cap-sd-highspeed;
211	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
212	vmmc-supply = <&reg_3p3v>;
213	vqmmc-supply = <&reg_3p3v>;
214	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
215	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
216};
217
218&nandc {
219	pinctrl-names = "default";
220	pinctrl-0 = <&parallel_nand_pins>;
221	status = "disabled";
222};
223
224&nor_flash {
225	pinctrl-names = "default";
226	pinctrl-0 = <&spi_nor_pins>;
227	status = "disabled";
228
229	flash@0 {
230		compatible = "jedec,spi-nor";
231		reg = <0>;
232	};
233};
234
235&pcie0 {
236	pinctrl-names = "default";
237	pinctrl-0 = <&pcie0_pins>;
238	status = "okay";
239};
240
241&pio {
242	/* eMMC is shared pin with parallel NAND */
243	emmc_pins_default: emmc-pins-default {
244		mux {
245			function = "emmc", "emmc_rst";
246			groups = "emmc";
247		};
248
249		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
250		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
251		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
252		 */
253		conf-cmd-dat {
254			pins = "NDL0", "NDL1", "NDL2",
255			       "NDL3", "NDL4", "NDL5",
256			       "NDL6", "NDL7", "NRB";
257			input-enable;
258			bias-pull-up;
259		};
260
261		conf-clk {
262			pins = "NCLE";
263			bias-pull-down;
264		};
265	};
266
267	emmc_pins_uhs: emmc-pins-uhs {
268		mux {
269			function = "emmc";
270			groups = "emmc";
271		};
272
273		conf-cmd-dat {
274			pins = "NDL0", "NDL1", "NDL2",
275			       "NDL3", "NDL4", "NDL5",
276			       "NDL6", "NDL7", "NRB";
277			input-enable;
278			drive-strength = <4>;
279			bias-pull-up;
280		};
281
282		conf-clk {
283			pins = "NCLE";
284			drive-strength = <4>;
285			bias-pull-down;
286		};
287	};
288
289	eth_pins: eth-pins {
290		mux {
291			function = "eth";
292			groups = "mdc_mdio", "rgmii_via_gmac2";
293		};
294	};
295
296	i2c1_pins: i2c1-pins {
297		mux {
298			function = "i2c";
299			groups = "i2c1_0";
300		};
301	};
302
303	i2c2_pins: i2c2-pins {
304		mux {
305			function = "i2c";
306			groups = "i2c2_0";
307		};
308	};
309
310	i2s1_pins: i2s1-pins {
311		mux {
312			function = "i2s";
313			groups =  "i2s_out_mclk_bclk_ws",
314				  "i2s1_in_data",
315				  "i2s1_out_data";
316		};
317
318		conf {
319			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
320			       "I2S_WS", "I2S_MCLK";
321			drive-strength = <12>;
322			bias-pull-down;
323		};
324	};
325
326	irrx_pins: irrx-pins {
327		mux {
328			function = "ir";
329			groups = "ir_1_rx";
330		};
331	};
332
333	irtx_pins: irtx-pins {
334		mux {
335			function = "ir";
336			groups = "ir_1_tx";
337		};
338	};
339
340	/* Parallel nand is shared pin with eMMC */
341	parallel_nand_pins: parallel-nand-pins {
342		mux {
343			function = "flash";
344			groups = "par_nand";
345		};
346	};
347
348	pcie0_pins: pcie0-pins {
349		mux {
350			function = "pcie";
351			groups = "pcie0_pad_perst",
352				 "pcie0_1_waken",
353				 "pcie0_1_clkreq";
354		};
355	};
356
357	pcie1_pins: pcie1-pins {
358		mux {
359			function = "pcie";
360			groups = "pcie1_pad_perst",
361				 "pcie1_0_waken",
362				 "pcie1_0_clkreq";
363		};
364	};
365
366	pmic_bus_pins: pmic-bus-pins {
367		mux {
368			function = "pmic";
369			groups = "pmic_bus";
370		};
371	};
372
373	pwm7_pins: pwm1-2-pins {
374		mux {
375			function = "pwm";
376			groups = "pwm_ch7_2";
377		};
378	};
379
380	wled_pins: wled-pins {
381		mux {
382			function = "led";
383			groups = "wled";
384		};
385	};
386
387	sd0_pins_default: sd0-pins-default {
388		mux {
389			function = "sd";
390			groups = "sd_0";
391		};
392
393		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
394		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
395		 *  DAT2, DAT3, CMD, CLK for SD respectively.
396		 */
397		conf-cmd-data {
398			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
399			       "I2S2_IN","I2S4_OUT";
400			input-enable;
401			drive-strength = <8>;
402			bias-pull-up;
403		};
404		conf-clk {
405			pins = "I2S3_OUT";
406			drive-strength = <12>;
407			bias-pull-down;
408		};
409		conf-cd {
410			pins = "TXD3";
411			bias-pull-up;
412		};
413	};
414
415	sd0_pins_uhs: sd0-pins-uhs {
416		mux {
417			function = "sd";
418			groups = "sd_0";
419		};
420
421		conf-cmd-data {
422			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
423			       "I2S2_IN","I2S4_OUT";
424			input-enable;
425			bias-pull-up;
426		};
427
428		conf-clk {
429			pins = "I2S3_OUT";
430			bias-pull-down;
431		};
432	};
433
434	/* Serial NAND is shared pin with SPI-NOR */
435	serial_nand_pins: serial-nand-pins {
436		mux {
437			function = "flash";
438			groups = "snfi";
439		};
440	};
441
442	spic0_pins: spic0-pins {
443		mux {
444			function = "spi";
445			groups = "spic0_0";
446		};
447	};
448
449	spic1_pins: spic1-pins {
450		mux {
451			function = "spi";
452			groups = "spic1_0";
453		};
454	};
455
456	/* SPI-NOR is shared pin with serial NAND */
457	spi_nor_pins: spi-nor-pins {
458		mux {
459			function = "flash";
460			groups = "spi_nor";
461		};
462	};
463
464	/* serial NAND is shared pin with SPI-NOR */
465	serial_nand_pins: serial-nand-pins {
466		mux {
467			function = "flash";
468			groups = "snfi";
469		};
470	};
471
472	uart0_pins: uart0-pins {
473		mux {
474			function = "uart";
475			groups = "uart0_0_tx_rx" ;
476		};
477	};
478
479	uart2_pins: uart2-pins {
480		mux {
481			function = "uart";
482			groups = "uart2_1_tx_rx" ;
483		};
484	};
485
486	watchdog_pins: watchdog-pins {
487		mux {
488			function = "watchdog";
489			groups = "watchdog";
490		};
491	};
492
493	wmac_pins: wmac-pins {
494		mux {
495			function = "antsel";
496			groups = "antsel0", "antsel1", "antsel2", "antsel3",
497				 "antsel4", "antsel5", "antsel6", "antsel7",
498				 "antsel8", "antsel9", "antsel12", "antsel13",
499				 "antsel14", "antsel15", "antsel16", "antsel17";
500		};
501	};
502};
503
504&pwm {
505	pinctrl-names = "default";
506	pinctrl-0 = <&pwm7_pins>;
507	status = "okay";
508};
509
510&pwrap {
511	pinctrl-names = "default";
512	pinctrl-0 = <&pmic_bus_pins>;
513
514	status = "okay";
515};
516
517&sata {
518	status = "okay";
519};
520
521&sata_phy {
522	status = "okay";
523};
524
525&spi0 {
526	pinctrl-names = "default";
527	pinctrl-0 = <&spic0_pins>;
528	status = "okay";
529};
530
531&spi1 {
532	pinctrl-names = "default";
533	pinctrl-0 = <&spic1_pins>;
534	status = "okay";
535};
536
537&ssusb {
538	vusb33-supply = <&reg_3p3v>;
539	vbus-supply = <&reg_5v>;
540	status = "okay";
541};
542
543&u3phy {
544	status = "okay";
545};
546
547&uart0 {
548	pinctrl-names = "default";
549	pinctrl-0 = <&uart0_pins>;
550	status = "okay";
551};
552
553&uart2 {
554	pinctrl-names = "default";
555	pinctrl-0 = <&uart2_pins>;
556	status = "okay";
557};
558
559&watchdog {
560	pinctrl-names = "default";
561	pinctrl-0 = <&watchdog_pins>;
562	status = "okay";
563};
564
565&wmac {
566	pinctrl-names = "default";
567	pinctrl-0 = <&wmac_pins>;
568	status = "okay";
569};
570