1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: YT Shen <yt.shen@mediatek.com> 4 * 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 */ 7 8#include <dt-bindings/clock/mt2712-clk.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/mt2712-power.h> 12#include "mt2712-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt2712"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cluster0_opp: opp_table0 { 21 compatible = "operating-points-v2"; 22 opp-shared; 23 opp00 { 24 opp-hz = /bits/ 64 <598000000>; 25 opp-microvolt = <1000000>; 26 }; 27 opp01 { 28 opp-hz = /bits/ 64 <702000000>; 29 opp-microvolt = <1000000>; 30 }; 31 opp02 { 32 opp-hz = /bits/ 64 <793000000>; 33 opp-microvolt = <1000000>; 34 }; 35 }; 36 37 cluster1_opp: opp_table1 { 38 compatible = "operating-points-v2"; 39 opp-shared; 40 opp00 { 41 opp-hz = /bits/ 64 <598000000>; 42 opp-microvolt = <1000000>; 43 }; 44 opp01 { 45 opp-hz = /bits/ 64 <702000000>; 46 opp-microvolt = <1000000>; 47 }; 48 opp02 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <1000000>; 51 }; 52 opp03 { 53 opp-hz = /bits/ 64 <897000000>; 54 opp-microvolt = <1000000>; 55 }; 56 opp04 { 57 opp-hz = /bits/ 64 <1001000000>; 58 opp-microvolt = <1000000>; 59 }; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 cpu-map { 67 cluster0 { 68 core0 { 69 cpu = <&cpu0>; 70 }; 71 core1 { 72 cpu = <&cpu1>; 73 }; 74 }; 75 76 cluster1 { 77 core0 { 78 cpu = <&cpu2>; 79 }; 80 }; 81 }; 82 83 cpu0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a35"; 86 reg = <0x000>; 87 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 88 <&topckgen CLK_TOP_F_MP0_PLL1>; 89 clock-names = "cpu", "intermediate"; 90 proc-supply = <&cpus_fixed_vproc0>; 91 operating-points-v2 = <&cluster0_opp>; 92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 93 }; 94 95 cpu1: cpu@1 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a35"; 98 reg = <0x001>; 99 enable-method = "psci"; 100 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 101 <&topckgen CLK_TOP_F_MP0_PLL1>; 102 clock-names = "cpu", "intermediate"; 103 proc-supply = <&cpus_fixed_vproc0>; 104 operating-points-v2 = <&cluster0_opp>; 105 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 106 }; 107 108 cpu2: cpu@200 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a72"; 111 reg = <0x200>; 112 enable-method = "psci"; 113 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 114 <&topckgen CLK_TOP_F_BIG_PLL1>; 115 clock-names = "cpu", "intermediate"; 116 proc-supply = <&cpus_fixed_vproc1>; 117 operating-points-v2 = <&cluster1_opp>; 118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 119 }; 120 121 idle-states { 122 entry-method = "psci"; 123 124 CPU_SLEEP_0: cpu-sleep-0 { 125 compatible = "arm,idle-state"; 126 local-timer-stop; 127 entry-latency-us = <100>; 128 exit-latency-us = <80>; 129 min-residency-us = <2000>; 130 arm,psci-suspend-param = <0x0010000>; 131 }; 132 133 CLUSTER_SLEEP_0: cluster-sleep-0 { 134 compatible = "arm,idle-state"; 135 local-timer-stop; 136 entry-latency-us = <350>; 137 exit-latency-us = <80>; 138 min-residency-us = <3000>; 139 arm,psci-suspend-param = <0x1010000>; 140 }; 141 }; 142 }; 143 144 psci { 145 compatible = "arm,psci-0.2"; 146 method = "smc"; 147 }; 148 149 baud_clk: dummy26m { 150 compatible = "fixed-clock"; 151 clock-frequency = <26000000>; 152 #clock-cells = <0>; 153 }; 154 155 sys_clk: dummyclk { 156 compatible = "fixed-clock"; 157 clock-frequency = <26000000>; 158 #clock-cells = <0>; 159 }; 160 161 clk26m: oscillator@0 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <26000000>; 165 clock-output-names = "clk26m"; 166 }; 167 168 clk32k: oscillator@1 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <32768>; 172 clock-output-names = "clk32k"; 173 }; 174 175 clkfpc: oscillator@2 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <50000000>; 179 clock-output-names = "clkfpc"; 180 }; 181 182 clkaud_ext_i_0: oscillator@3 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency = <6500000>; 186 clock-output-names = "clkaud_ext_i_0"; 187 }; 188 189 clkaud_ext_i_1: oscillator@4 { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 clock-frequency = <196608000>; 193 clock-output-names = "clkaud_ext_i_1"; 194 }; 195 196 clkaud_ext_i_2: oscillator@5 { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <180633600>; 200 clock-output-names = "clkaud_ext_i_2"; 201 }; 202 203 clki2si0_mck_i: oscillator@6 { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <30000000>; 207 clock-output-names = "clki2si0_mck_i"; 208 }; 209 210 clki2si1_mck_i: oscillator@7 { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency = <30000000>; 214 clock-output-names = "clki2si1_mck_i"; 215 }; 216 217 clki2si2_mck_i: oscillator@8 { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <30000000>; 221 clock-output-names = "clki2si2_mck_i"; 222 }; 223 224 clktdmin_mclk_i: oscillator@9 { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <30000000>; 228 clock-output-names = "clktdmin_mclk_i"; 229 }; 230 231 timer { 232 compatible = "arm,armv8-timer"; 233 interrupt-parent = <&gic>; 234 interrupts = <GIC_PPI 13 235 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 11 239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 10 241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 242 }; 243 244 topckgen: syscon@10000000 { 245 compatible = "mediatek,mt2712-topckgen", "syscon"; 246 reg = <0 0x10000000 0 0x1000>; 247 #clock-cells = <1>; 248 }; 249 250 infracfg: syscon@10001000 { 251 compatible = "mediatek,mt2712-infracfg", "syscon"; 252 reg = <0 0x10001000 0 0x1000>; 253 #clock-cells = <1>; 254 }; 255 256 pericfg: syscon@10003000 { 257 compatible = "mediatek,mt2712-pericfg", "syscon"; 258 reg = <0 0x10003000 0 0x1000>; 259 #clock-cells = <1>; 260 }; 261 262 syscfg_pctl_a: syscfg_pctl_a@10005000 { 263 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 264 reg = <0 0x10005000 0 0x1000>; 265 }; 266 267 pio: pinctrl@10005000 { 268 compatible = "mediatek,mt2712-pinctrl"; 269 reg = <0 0x1000b000 0 0x1000>; 270 mediatek,pctl-regmap = <&syscfg_pctl_a>; 271 pins-are-numbered; 272 gpio-controller; 273 #gpio-cells = <2>; 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 277 }; 278 279 scpsys: scpsys@10006000 { 280 compatible = "mediatek,mt2712-scpsys", "syscon"; 281 #power-domain-cells = <1>; 282 reg = <0 0x10006000 0 0x1000>; 283 clocks = <&topckgen CLK_TOP_MM_SEL>, 284 <&topckgen CLK_TOP_MFG_SEL>, 285 <&topckgen CLK_TOP_VENC_SEL>, 286 <&topckgen CLK_TOP_JPGDEC_SEL>, 287 <&topckgen CLK_TOP_A1SYS_HP_SEL>, 288 <&topckgen CLK_TOP_VDEC_SEL>; 289 clock-names = "mm", "mfg", "venc", 290 "jpgdec", "audio", "vdec"; 291 infracfg = <&infracfg>; 292 }; 293 294 uart5: serial@1000f000 { 295 compatible = "mediatek,mt2712-uart", 296 "mediatek,mt6577-uart"; 297 reg = <0 0x1000f000 0 0x400>; 298 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 299 clocks = <&baud_clk>, <&sys_clk>; 300 clock-names = "baud", "bus"; 301 status = "disabled"; 302 }; 303 304 spis1: spi@10013000 { 305 compatible = "mediatek,mt2712-spi-slave"; 306 reg = <0 0x10013000 0 0x100>; 307 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 308 clocks = <&infracfg CLK_INFRA_AO_SPI1>; 309 clock-names = "spi"; 310 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 311 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 312 status = "disabled"; 313 }; 314 315 apmixedsys: syscon@10209000 { 316 compatible = "mediatek,mt2712-apmixedsys", "syscon"; 317 reg = <0 0x10209000 0 0x1000>; 318 #clock-cells = <1>; 319 }; 320 321 mcucfg: syscon@10220000 { 322 compatible = "mediatek,mt2712-mcucfg", "syscon"; 323 reg = <0 0x10220000 0 0x1000>; 324 #clock-cells = <1>; 325 }; 326 327 sysirq: interrupt-controller@10220a80 { 328 compatible = "mediatek,mt2712-sysirq", 329 "mediatek,mt6577-sysirq"; 330 interrupt-controller; 331 #interrupt-cells = <3>; 332 interrupt-parent = <&gic>; 333 reg = <0 0x10220a80 0 0x40>; 334 }; 335 336 gic: interrupt-controller@10510000 { 337 compatible = "arm,gic-400"; 338 #interrupt-cells = <3>; 339 interrupt-parent = <&gic>; 340 interrupt-controller; 341 reg = <0 0x10510000 0 0x10000>, 342 <0 0x10520000 0 0x20000>, 343 <0 0x10540000 0 0x20000>, 344 <0 0x10560000 0 0x20000>; 345 interrupts = <GIC_PPI 9 346 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 347 }; 348 349 auxadc: adc@11001000 { 350 compatible = "mediatek,mt2712-auxadc"; 351 reg = <0 0x11001000 0 0x1000>; 352 clocks = <&pericfg CLK_PERI_AUXADC>; 353 clock-names = "main"; 354 #io-channel-cells = <1>; 355 status = "disabled"; 356 }; 357 358 uart0: serial@11002000 { 359 compatible = "mediatek,mt2712-uart", 360 "mediatek,mt6577-uart"; 361 reg = <0 0x11002000 0 0x400>; 362 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 363 clocks = <&baud_clk>, <&sys_clk>; 364 clock-names = "baud", "bus"; 365 status = "disabled"; 366 }; 367 368 uart1: serial@11003000 { 369 compatible = "mediatek,mt2712-uart", 370 "mediatek,mt6577-uart"; 371 reg = <0 0x11003000 0 0x400>; 372 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 373 clocks = <&baud_clk>, <&sys_clk>; 374 clock-names = "baud", "bus"; 375 status = "disabled"; 376 }; 377 378 uart2: serial@11004000 { 379 compatible = "mediatek,mt2712-uart", 380 "mediatek,mt6577-uart"; 381 reg = <0 0x11004000 0 0x400>; 382 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 383 clocks = <&baud_clk>, <&sys_clk>; 384 clock-names = "baud", "bus"; 385 status = "disabled"; 386 }; 387 388 uart3: serial@11005000 { 389 compatible = "mediatek,mt2712-uart", 390 "mediatek,mt6577-uart"; 391 reg = <0 0x11005000 0 0x400>; 392 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 393 clocks = <&baud_clk>, <&sys_clk>; 394 clock-names = "baud", "bus"; 395 status = "disabled"; 396 }; 397 398 uart4: serial@11019000 { 399 compatible = "mediatek,mt2712-uart", 400 "mediatek,mt6577-uart"; 401 reg = <0 0x11019000 0 0x400>; 402 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 403 clocks = <&baud_clk>, <&sys_clk>; 404 clock-names = "baud", "bus"; 405 status = "disabled"; 406 }; 407 408 mfgcfg: syscon@13000000 { 409 compatible = "mediatek,mt2712-mfgcfg", "syscon"; 410 reg = <0 0x13000000 0 0x1000>; 411 #clock-cells = <1>; 412 }; 413 414 mmsys: syscon@14000000 { 415 compatible = "mediatek,mt2712-mmsys", "syscon"; 416 reg = <0 0x14000000 0 0x1000>; 417 #clock-cells = <1>; 418 }; 419 420 imgsys: syscon@15000000 { 421 compatible = "mediatek,mt2712-imgsys", "syscon"; 422 reg = <0 0x15000000 0 0x1000>; 423 #clock-cells = <1>; 424 }; 425 426 bdpsys: syscon@15010000 { 427 compatible = "mediatek,mt2712-bdpsys", "syscon"; 428 reg = <0 0x15010000 0 0x1000>; 429 #clock-cells = <1>; 430 }; 431 432 vdecsys: syscon@16000000 { 433 compatible = "mediatek,mt2712-vdecsys", "syscon"; 434 reg = <0 0x16000000 0 0x1000>; 435 #clock-cells = <1>; 436 }; 437 438 vencsys: syscon@18000000 { 439 compatible = "mediatek,mt2712-vencsys", "syscon"; 440 reg = <0 0x18000000 0 0x1000>; 441 #clock-cells = <1>; 442 }; 443 444 jpgdecsys: syscon@19000000 { 445 compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 446 reg = <0 0x19000000 0 0x1000>; 447 #clock-cells = <1>; 448 }; 449}; 450 451