1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com> 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8 9/* 10 * Instantiate the first external CP115 11 */ 12 13#define CP11X_NAME cp1 14#define CP11X_BASE f4000000 15#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) 16#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 17#define CP11X_PCIE0_BASE f4600000 18#define CP11X_PCIE1_BASE f4620000 19#define CP11X_PCIE2_BASE f4640000 20 21#include "armada-cp115.dtsi" 22 23#undef CP11X_NAME 24#undef CP11X_BASE 25#undef CP11X_PCIEx_MEM_BASE 26#undef CP11X_PCIEx_MEM_SIZE 27#undef CP11X_PCIE0_BASE 28#undef CP11X_PCIE1_BASE 29#undef CP11X_PCIE2_BASE 30 31/* 32 * Instantiate the second external CP115 33 */ 34 35#define CP11X_NAME cp2 36#define CP11X_BASE f6000000 37#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) 38#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 39#define CP11X_PCIE0_BASE f6600000 40#define CP11X_PCIE1_BASE f6620000 41#define CP11X_PCIE2_BASE f6640000 42 43#include "armada-cp115.dtsi" 44 45#undef CP11X_NAME 46#undef CP11X_BASE 47#undef CP11X_PCIEx_MEM_BASE 48#undef CP11X_PCIEx_MEM_SIZE 49#undef CP11X_PCIE0_BASE 50#undef CP11X_PCIE1_BASE 51#undef CP11X_PCIE2_BASE 52 53/ { 54 model = "SolidRun CN9132 COM Express Type 7 Module"; 55 compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130"; 56 57 aliases { 58 ethernet0 = &cp0_eth1; 59 gpio3 = &cp1_gpio1; 60 gpio4 = &cp1_gpio2; 61 gpio5 = &cp2_gpio1; 62 gpio6 = &cp2_gpio2; 63 i2c0 = &cp0_i2c0; 64 i2c1 = &cp0_i2c1; 65 i2c2 = &com_clkgen_i2c; 66 i2c3 = &com_10g_led_i2c; 67 i2c4 = &com_10g_sfp_i2c0; 68 i2c5 = &com_smbus; 69 i2c6 = &com_fanctrl_i2c; 70 mmc0 = &ap_sdhci0; 71 rtc0 = &cp0_rtc; 72 }; 73 74 chosen { 75 stdout-path = "serial0:115200n8"; 76 }; 77 78 fan: pwm-fan { 79 compatible = "pwm-fan"; 80 cooling-levels = <0 51 102 153 204 255>; 81 #cooling-cells = <2>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>; 84 pwms = <&cp0_gpio2 7 40000>; 85 interrupt-parent = <&cp0_gpio1>; 86 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 87 }; 88 89 v_1_8: regulator-1-8 { 90 compatible = "regulator-fixed"; 91 regulator-name = "1v8"; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 }; 95 96 ap_vhv: regulator-ap-vhv-1-8 { 97 compatible = "regulator-fixed"; 98 regulator-name = "ap-vhv-1v8"; 99 regulator-min-microvolt = <1800000>; 100 regulator-max-microvolt = <1800000>; 101 pinctrl-0 = <&cp0_reg_ap_vhv_pins>; 102 pinctrl-names = "default"; 103 gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 }; 106 107 cp_vhv: regulator-cp-vhv-1-8 { 108 compatible = "regulator-fixed"; 109 regulator-name = "cp-vhv-1v8"; 110 regulator-min-microvolt = <1800000>; 111 regulator-max-microvolt = <1800000>; 112 pinctrl-0 = <&cp0_reg_cp_vhv_pins>; 113 pinctrl-names = "default"; 114 gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117}; 118 119&ap_pinctrl { 120 ap_mmc0_pins: ap-mmc0-pins { 121 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", 122 "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12"; 123 marvell,function = "sdio"; 124 /* 125 * mpp12 is emmc reset, function should be sdio (hw_rst), 126 * but pinctrl-mvebu does not support this. 127 * 128 * From pinctrl-mvebu.h: 129 * "The name will be used to switch to this setting in DT description, e.g. 130 * marvell,function = "uart2". subname is only for debugging purposes." 131 */ 132 }; 133}; 134 135&ap_sdhci0 { 136 bus-width = <8>; 137 pinctrl-0 = <&ap_mmc0_pins>; 138 pinctrl-names = "default"; 139 vqmmc-supply = <&v_1_8>; 140 status = "okay"; 141}; 142 143&ap_thermal_ic { 144 polling-delay = <1000>; 145 146 trips { 147 ap_active: trip-active { 148 temperature = <40000>; 149 hysteresis = <4000>; 150 type = "active"; 151 }; 152 }; 153 154 cooling-maps { 155 map0 { 156 trip = <&ap_active>; 157 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 158 }; 159 160 map1 { 161 trip = <&ap_crit>; 162 cooling-device = <&fan 4 5>; 163 }; 164 }; 165}; 166 167&cp0_ethernet { 168 status = "okay"; 169}; 170 171&cp0_eth1 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&cp0_eth1_pins>; 174 phy-mode = "rgmii-id"; 175 phy = <&cp0_eth_phy0>; 176 status = "okay"; 177}; 178 179&cp0_gpio1 { 180 status = "okay"; 181 182 /* 183 * Tacho signal used as interrupt source by pwm-fan driver. 184 * Hog IO as input to ensure mvebu-gpio irq driver`s 185 * irq_set_type can succeed. 186 */ 187 pwm-tacho-irq-hog { 188 gpio-hog; 189 gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; 190 input; 191 line-name = "fan-tacho"; 192 }; 193}; 194 195&cp0_gpio2 { 196 status = "okay"; 197}; 198 199&cp0_i2c0 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&cp0_i2c0_pins>; 202 clock-frequency = <100000>; 203 status = "okay"; 204 205 com_eeprom: eeprom@50 { 206 compatible = "atmel,24c02"; 207 reg = <0x50>; 208 pagesize = <8>; 209 }; 210 211 eeprom@53 { 212 compatible = "atmel,spd"; 213 reg = <0x53>; 214 }; 215}; 216 217&cp0_i2c1 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&cp0_i2c1_pins>; 220 clock-frequency = <100000>; 221 status = "okay"; 222 223 i2c-mux@77 { 224 compatible = "nxp,pca9547"; 225 reg = <0x77>; 226 i2c-mux-idle-disconnect; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 com_clkgen_i2c: i2c@0 { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0>; 234 235 /* clock-controller@6b */ 236 }; 237 238 com_10g_led_i2c: i2c@1 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <1>; 242 243 /* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */ 244 }; 245 246 com_10g_sfp_i2c0: i2c@2 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 reg = <2>; 250 251 /* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */ 252 }; 253 254 com_smbus: i2c@3 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <3>; 258 259 /* Routed to B2B Connector as SBM_CLK/DAT */ 260 }; 261 262 com_fanctrl_i2c: i2c@4 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <4>; 266 267 /* fan-controller@2f (assembly option) */ 268 }; 269 }; 270}; 271 272&cp0_mdio { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&cp0_mdio_pins>; 275 status = "okay"; 276 277 cp0_eth_phy0: ethernet-phy@0 { 278 reg = <0>; 279 }; 280}; 281 282&cp0_spi1 { 283 pinctrl-names = "default"; 284 pinctrl-0 = <&cp0_spi1_pins>; 285 status = "okay"; 286 287 flash@0 { 288 compatible = "jedec,spi-nor"; 289 reg = <0>; 290 /* read command supports max. 50MHz */ 291 spi-max-frequency = <50000000>; 292 }; 293}; 294 295&cp0_syscon0 { 296 cp0_pinctrl: pinctrl { 297 compatible = "marvell,cp115-standalone-pinctrl"; 298 299 com_10g_int0_pins: cp0-10g-int-pins { 300 marvell,pins = "mpp24"; 301 marvell,function = "gpio"; 302 }; 303 304 cp0_eth1_pins: cp0-eth1-pins { 305 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", 306 "mpp4", "mpp5", "mpp6", "mpp7", 307 "mpp8", "mpp9", "mpp10", "mpp11"; 308 /* docs call it "ge1", but cp110-pinctrl "ge0" */ 309 marvell,function = "ge0"; 310 }; 311 312 cp0_fan_pwm_pins: cp0-fan-pwm-pins { 313 marvell,pins = "mpp39"; 314 marvell,function = "gpio"; 315 }; 316 317 cp0_fan_tacho_pins: cp0-fan-tacho-pins { 318 marvell,pins = "mpp26"; 319 marvell,function = "gpio"; 320 }; 321 322 cp0_i2c0_pins: cp0-i2c0-pins { 323 marvell,pins = "mpp37", "mpp38"; 324 marvell,function = "i2c0"; 325 }; 326 327 cp0_i2c1_pins: cp0-i2c1-pins { 328 marvell,pins = "mpp35", "mpp36"; 329 marvell,function = "i2c1"; 330 }; 331 332 cp0_mdio_pins: cp0-mdio-pins { 333 marvell,pins = "mpp40", "mpp41"; 334 marvell,function = "ge"; 335 }; 336 337 cp0_mmc0_pins: cp0-mmc0-pins { 338 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59", 339 "mpp60", "mpp61"; 340 marvell,function = "sdio"; 341 }; 342 343 cp0_mmc0_cd_pins: cp0-mmc0-cd-pins { 344 marvell,pins = "mpp55"; 345 marvell,function = "sdio_cd"; 346 }; 347 348 cp0_pwrbtn_pins: cp0-pwrbtn-pins { 349 marvell,pins = "mpp31"; 350 marvell,function = "gpio"; 351 }; 352 353 cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins { 354 marvell,pins = "mpp53"; 355 marvell,function = "gpio"; 356 }; 357 358 cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins { 359 marvell,pins = "mpp49"; 360 marvell,function = "gpio"; 361 }; 362 363 cp0_spi1_pins: cp0-spi1-pins { 364 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 365 marvell,function = "spi1"; 366 }; 367 368 cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { 369 marvell,pins = "mpp12"; 370 marvell,function = "spi1"; 371 }; 372 373 cp0_uart2_pins: cp0-uart2-pins { 374 marvell,pins = "mpp50", "mpp51"; 375 marvell,function = "uart2"; 376 }; 377 }; 378}; 379 380&cp0_thermal_ic { 381 polling-delay = <1000>; 382 383 trips { 384 cp0_active: trip-active { 385 temperature = <40000>; 386 hysteresis = <4000>; 387 type = "active"; 388 }; 389 }; 390 391 cooling-maps { 392 map0 { 393 trip = <&cp0_active>; 394 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 395 }; 396 397 map1 { 398 trip = <&cp0_crit>; 399 cooling-device = <&fan 4 5>; 400 }; 401 }; 402}; 403 404/* USB-2.0 Host */ 405&cp0_usb3_0 { 406 phys = <&cp0_utmi0>; 407 phy-names = "utmi"; 408 dr_mode = "host"; 409 status = "okay"; 410}; 411 412/* USB-2.0 Host */ 413&cp0_usb3_1 { 414 phys = <&cp0_utmi1>; 415 phy-names = "utmi"; 416 dr_mode = "host"; 417 status = "okay"; 418}; 419 420&cp0_utmi { 421 status = "okay"; 422}; 423 424&cp1_gpio1 { 425 status = "okay"; 426}; 427 428&cp1_gpio2 { 429 status = "okay"; 430}; 431 432&cp1_rtc { 433 status = "disabled"; 434}; 435 436&cp1_spi1 { 437 pinctrl-names = "default"; 438 pinctrl-0 = <&cp1_spi1_pins>; 439 status = "okay"; 440 441 tpm@0 { 442 reg = <0>; 443 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 444 spi-max-frequency = <10000000>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&cp1_tpm_irq_pins>; 447 interrupt-parent = <&cp1_gpio1>; 448 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 449 }; 450}; 451 452&cp1_syscon0 { 453 cp1_pinctrl: pinctrl { 454 compatible = "marvell,cp115-standalone-pinctrl"; 455 456 com_10g_int1_pins: cp1-10g-int-pins { 457 marvell,pins = "mpp50"; 458 marvell,function = "gpio"; 459 }; 460 461 cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins { 462 marvell,pins = "mpp43"; 463 marvell,function = "gpio"; 464 }; 465 466 cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins { 467 marvell,pins = "mpp42"; 468 marvell,function = "gpio"; 469 }; 470 471 cp1_batlow_pins: cp1-batlow-pins { 472 marvell,pins = "mpp11"; 473 marvell,function = "gpio"; 474 }; 475 476 cp1_rsvd16_pins: cp1-rsvd16-pins { 477 marvell,pins = "mpp29"; 478 marvell,function = "gpio"; 479 }; 480 481 cp1_sata_act_pins: cp1-sata-act-pins { 482 marvell,pins = "mpp39"; 483 marvell,function = "gpio"; 484 }; 485 486 cp1_spi1_pins: cp1-spi1-pins { 487 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 488 marvell,function = "spi1"; 489 }; 490 491 cp1_thrm_irq_pins: cp1-thrm-irq-pins { 492 marvell,pins = "mpp34"; 493 marvell,function = "gpio"; 494 }; 495 496 cp1_thrm_trip_pins: cp1-thrm-trip-pins { 497 marvell,pins = "mpp33"; 498 marvell,function = "gpio"; 499 }; 500 501 cp1_tpm_irq_pins: cp1-tpm-irq-pins { 502 marvell,pins = "mpp17"; 503 marvell,function = "gpio"; 504 }; 505 506 cp1_wake0_pins: cp1-wake0-pins { 507 marvell,pins = "mpp40"; 508 marvell,function = "gpio"; 509 }; 510 511 cp1_wake1_pins: cp1-wake1-pins { 512 marvell,pins = "mpp51"; 513 marvell,function = "gpio"; 514 }; 515 516 cp1_xmdio_pins: cp1-xmdio-pins { 517 marvell,pins = "mpp37", "mpp38"; 518 marvell,function = "xg"; 519 }; 520 }; 521}; 522 523&cp1_thermal_ic { 524 polling-delay = <1000>; 525 526 trips { 527 cp1_active: trip-active { 528 temperature = <40000>; 529 hysteresis = <4000>; 530 type = "active"; 531 }; 532 }; 533 534 cooling-maps { 535 map0 { 536 trip = <&cp1_active>; 537 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 538 }; 539 540 map1 { 541 trip = <&cp1_crit>; 542 cooling-device = <&fan 4 5>; 543 }; 544 }; 545}; 546 547/* USB-2.0 Host */ 548&cp1_usb3_0 { 549 phys = <&cp1_utmi0>; 550 phy-names = "utmi"; 551 dr_mode = "host"; 552 status = "okay"; 553}; 554 555&cp1_utmi { 556 status = "okay"; 557}; 558 559&cp2_ethernet { 560 status = "okay"; 561}; 562 563&cp2_gpio1 { 564 status = "okay"; 565}; 566 567&cp2_gpio2 { 568 status = "okay"; 569}; 570 571&cp2_rtc { 572 status = "disabled"; 573}; 574 575&cp2_syscon0 { 576 cp2_pinctrl: pinctrl { 577 compatible = "marvell,cp115-standalone-pinctrl"; 578 579 com_10g_int2_pins: cp2-10g-int-pins { 580 marvell,pins = "mpp50"; 581 marvell,function = "gpio"; 582 }; 583 584 cp2_rsvd0_pins: cp2-rsvd0-pins { 585 marvell,pins = "mpp0"; 586 marvell,function = "gpio"; 587 }; 588 589 cp2_rsvd1_pins: cp2-rsvd1-pins { 590 marvell,pins = "mpp1"; 591 marvell,function = "gpio"; 592 }; 593 594 cp2_rsvd2_pins: cp2-rsvd2-pins { 595 marvell,pins = "mpp2"; 596 marvell,function = "gpio"; 597 }; 598 599 cp2_rsvd3_pins: cp2-rsvd3-pins { 600 marvell,pins = "mpp3"; 601 marvell,function = "gpio"; 602 }; 603 604 cp2_rsvd4_pins: cp2-rsvd4-pins { 605 marvell,pins = "mpp4"; 606 marvell,function = "gpio"; 607 }; 608 609 cp2_rsvd5_pins: cp2-rsvd5-pins { 610 marvell,pins = "mpp54"; 611 marvell,function = "gpio"; 612 }; 613 614 cp2_rsvd7_pins: cp2-rsvd7-pins { 615 marvell,pins = "mpp7"; 616 marvell,function = "gpio"; 617 }; 618 619 cp2_rsvd8_pins: cp2-rsvd8-pins { 620 marvell,pins = "mpp8"; 621 marvell,function = "gpio"; 622 }; 623 624 cp2_rsvd9_pins: cp2-rsvd9-pins { 625 marvell,pins = "mpp9"; 626 marvell,function = "gpio"; 627 }; 628 629 cp2_rsvd10_pins: cp2-rsvd10-pins { 630 marvell,pins = "mpp10"; 631 marvell,function = "gpio"; 632 }; 633 634 cp2_rsvd11_pins: cp2-rsvd11-pins { 635 marvell,pins = "mpp11"; 636 marvell,function = "gpio"; 637 }; 638 639 cp2_rsvd27_pins: cp2-rsvd27-pins { 640 marvell,pins = "mpp11"; 641 marvell,function = "gpio"; 642 }; 643 644 cp2_rsvd31_pins: cp2-rsvd31-pins { 645 marvell,pins = "mpp31"; 646 marvell,function = "gpio"; 647 }; 648 649 cp2_rsvd32_pins: cp2-rsvd32-pins { 650 marvell,pins = "mpp32"; 651 marvell,function = "gpio"; 652 }; 653 654 cp2_rsvd55_pins: cp2-rsvd55-pins { 655 marvell,pins = "mpp55"; 656 marvell,function = "gpio"; 657 }; 658 659 cp2_rsvd56_pins: cp2-rsvd56-pins { 660 marvell,pins = "mpp56"; 661 marvell,function = "gpio"; 662 }; 663 664 cp2_xmdio_pins: cp2-xmdio-pins { 665 marvell,pins = "mpp37", "mpp38"; 666 marvell,function = "xg"; 667 }; 668 }; 669}; 670 671&cp2_thermal_ic { 672 polling-delay = <1000>; 673 674 trips { 675 cp2_active: trip-active { 676 temperature = <40000>; 677 hysteresis = <4000>; 678 type = "active"; 679 }; 680 }; 681 682 cooling-maps { 683 map0 { 684 trip = <&cp2_active>; 685 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 686 }; 687 688 map1 { 689 trip = <&cp2_crit>; 690 cooling-device = <&fan 4 5>; 691 }; 692 }; 693}; 694 695/* USB-2.0/3.0 Host */ 696&cp2_usb3_0 { 697 phys = <&cp2_utmi0>, <&cp2_comphy1 0>; 698 phy-names = "utmi", "comphy"; 699 dr_mode = "host"; 700 status = "okay"; 701}; 702 703&cp2_utmi { 704 status = "okay"; 705}; 706 707/* AP default console */ 708&uart0 { 709 pinctrl-0 = <&uart0_pins>; 710 pinctrl-names = "default"; 711 status = "okay"; 712}; 713