xref: /linux/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts (revision ee057c8c194b9283f4137b253b70e292693a39f0) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
4 *
5 * DTS for SolidRun CN9130 Clearfog Pro.
6 *
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/leds/common.h>
13
14#include "cn9130.dtsi"
15#include "cn9130-sr-som.dtsi"
16#include "cn9130-cf.dtsi"
17
18/ {
19	model = "SolidRun CN9130 Clearfog Pro";
20	compatible = "solidrun,cn9130-clearfog-pro",
21		     "solidrun,cn9130-sr-som", "marvell,cn9130";
22
23	gpio-keys {
24		compatible = "gpio-keys";
25		pinctrl-0 = <&rear_button_pins>;
26		pinctrl-names = "default";
27
28		button-0 {
29			/* The rear SW3 button */
30			label = "Rear Button";
31			gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
32			linux,can-disable;
33			linux,code = <BTN_0>;
34		};
35	};
36};
37
38/* SRDS #3 - SGMII 1GE to L2 switch */
39&cp0_eth1 {
40	phys = <&cp0_comphy3 1>;
41	phy-mode = "sgmii";
42	status = "okay";
43
44	fixed-link {
45		speed = <1000>;
46		full-duplex;
47	};
48};
49
50&cp0_eth2_phy {
51	/*
52	 * Configure LEDs default behaviour similar to switch ports:
53	 * - LED[0]: link/activity: On/blink (green)
54	 * - LED[1]: link is 100/1000Mbps: On (red)
55	 * - LED[2]: high impedance (floating)
56	 *
57	 * Switch port defaults:
58	 * - LED0: link/activity: On/blink (green)
59	 * - LED1: link is 1000Mbps: On (red)
60	 *
61	 * Identical configuration is impossible with hardware offload.
62	 */
63	marvell,reg-init = <3 16 0xf000 0x0a61>;
64
65	leds {
66		#address-cells = <1>;
67		#size-cells = <0>;
68
69		led@0 {
70			reg = <0>;
71			color = <LED_COLOR_ID_GREEN>;
72			function = LED_FUNCTION_WAN;
73			label = "LED2";
74			default-state = "keep";
75		};
76
77		led@1 {
78			reg = <1>;
79			color = <LED_COLOR_ID_RED>;
80			function = LED_FUNCTION_WAN;
81			label = "LED1";
82			default-state = "keep";
83		};
84	};
85};
86
87&cp0_mdio {
88	ethernet-switch@4 {
89		compatible = "marvell,mv88e6085";
90		reg = <4>;
91		pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
92		pinctrl-names = "default";
93		reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
94		interrupt-parent = <&cp0_gpio1>;
95		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
96
97		ethernet-ports {
98			#address-cells = <1>;
99			#size-cells = <0>;
100
101			ethernet-port@0 {
102				reg = <0>;
103				label = "lan5";
104				phy = <&switch0phy0>;
105
106				leds {
107					#address-cells = <1>;
108					#size-cells = <0>;
109
110					led@0 {
111						reg = <0>;
112						color = <LED_COLOR_ID_GREEN>;
113						function = LED_FUNCTION_LAN;
114						label = "LED12";
115						default-state = "keep";
116					};
117
118					led@1 {
119						reg = <1>;
120						color = <LED_COLOR_ID_RED>;
121						function = LED_FUNCTION_LAN;
122						label = "LED11";
123						default-state = "keep";
124					};
125				};
126			};
127
128			ethernet-port@1 {
129				reg = <1>;
130				label = "lan4";
131				phy = <&switch0phy1>;
132
133				leds {
134					#address-cells = <1>;
135					#size-cells = <0>;
136
137					led@0 {
138						reg = <0>;
139						color = <LED_COLOR_ID_GREEN>;
140						function = LED_FUNCTION_LAN;
141						label = "LED10";
142						default-state = "keep";
143					};
144
145					led@1 {
146						reg = <1>;
147						color = <LED_COLOR_ID_RED>;
148						function = LED_FUNCTION_LAN;
149						label = "LED9";
150						default-state = "keep";
151					};
152				};
153			};
154
155			ethernet-port@2 {
156				reg = <2>;
157				label = "lan3";
158				phy = <&switch0phy2>;
159
160				leds {
161					#address-cells = <1>;
162					#size-cells = <0>;
163
164					led@0 {
165						reg = <0>;
166						color = <LED_COLOR_ID_GREEN>;
167						function = LED_FUNCTION_LAN;
168						label = "LED8";
169						default-state = "keep";
170					};
171
172					led@1 {
173						reg = <1>;
174						color = <LED_COLOR_ID_RED>;
175						function = LED_FUNCTION_LAN;
176						label = "LED7";
177						default-state = "keep";
178					};
179				};
180			};
181
182			ethernet-port@3 {
183				reg = <3>;
184				label = "lan2";
185				phy = <&switch0phy3>;
186
187				leds {
188					#address-cells = <1>;
189					#size-cells = <0>;
190
191					led@0 {
192						reg = <0>;
193						color = <LED_COLOR_ID_GREEN>;
194						function = LED_FUNCTION_LAN;
195						label = "LED6";
196						default-state = "keep";
197					};
198
199					led@1 {
200						reg = <1>;
201						color = <LED_COLOR_ID_RED>;
202						function = LED_FUNCTION_LAN;
203						label = "LED5";
204						default-state = "keep";
205					};
206				};
207			};
208
209			ethernet-port@4 {
210				reg = <4>;
211				label = "lan1";
212				phy = <&switch0phy4>;
213
214				leds {
215					#address-cells = <1>;
216					#size-cells = <0>;
217
218					led@0 {
219						reg = <0>;
220						color = <LED_COLOR_ID_GREEN>;
221						function = LED_FUNCTION_LAN;
222						label = "LED4";
223						default-state = "keep";
224					};
225
226					led@1 {
227						reg = <1>;
228						color = <LED_COLOR_ID_RED>;
229						function = LED_FUNCTION_LAN;
230						label = "LED3";
231						default-state = "keep";
232					};
233				};
234			};
235
236			ethernet-port@5 {
237				reg = <5>;
238				label = "cpu";
239				ethernet = <&cp0_eth1>;
240				phy-mode = "sgmii";
241
242				fixed-link {
243					speed = <1000>;
244					full-duplex;
245				};
246			};
247
248			ethernet-port@6 {
249				reg = <6>;
250				label = "lan6";
251				phy-mode = "rgmii";
252
253				/*
254				 * Because of mdio address conflict the
255				 * external phy is not readable.
256				 * Force a fixed link instead.
257				 */
258				fixed-link {
259					speed = <1000>;
260					full-duplex;
261				};
262			};
263		};
264
265		mdio {
266			#address-cells = <1>;
267			#size-cells = <0>;
268
269			switch0phy0: ethernet-phy@0 {
270				reg = <0x0>;
271			};
272
273			switch0phy1: ethernet-phy@1 {
274				reg = <0x1>;
275				/*
276				 * Indirectly configure default behaviour
277				 * for port lan6 leds behind external phy.
278				 * Internal PHYs are not using page 3,
279				 * therefore writing to it is safe.
280				 */
281				marvell,reg-init = <3 16 0xf000 0x0a61>;
282			};
283
284			switch0phy2: ethernet-phy@2 {
285				reg = <0x2>;
286			};
287
288			switch0phy3: ethernet-phy@3 {
289				reg = <0x3>;
290			};
291
292			switch0phy4: ethernet-phy@4 {
293				reg = <0x4>;
294			};
295		};
296
297		/*
298		 * There is an external phy on the switch mdio bus.
299		 * Because its mdio address collides with internal phys,
300		 * it is not readable.
301		 *
302		 * mdio-external {
303		 *	compatible = "marvell,mv88e6xxx-mdio-external";
304		 *	#address-cells = <1>;
305		 *	#size-cells = <0>;
306		 *
307		 *	ethernet-phy@1 {
308		 *		reg = <0x1>;
309		 *	};
310		 * };
311		 */
312	};
313};
314
315/* SRDS #4 - miniPCIe (CON2) */
316&cp0_pcie1 {
317	num-lanes = <1>;
318	phys = <&cp0_comphy4 1>;
319	/* dw-pcie inverts internally */
320	reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
321	status = "okay";
322};
323
324&cp0_pinctrl {
325	dsa_clk_pins: cp0-dsa-clk-pins {
326		marvell,pins = "mpp40";
327		marvell,function = "synce1";
328	};
329
330	dsa_pins: cp0-dsa-pins {
331		marvell,pins = "mpp27", "mpp29";
332		marvell,function = "gpio";
333	};
334
335	rear_button_pins: cp0-rear-button-pins {
336		marvell,pins = "mpp32";
337		marvell,function = "gpio";
338	};
339
340	cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
341		marvell,pins = "mpp12";
342		marvell,function = "spi1";
343	};
344};
345
346&cp0_spi1 {
347	/* add pin for chip-select 1 on mikrobus */
348	pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
349};
350
351/* USB-2.0 Host on Type-A connector */
352&cp0_usb3_1 {
353	phys = <&cp0_utmi1>;
354	phy-names = "utmi";
355	dr_mode = "host";
356	status = "okay";
357};
358
359&expander0 {
360	/* CON2 */
361	pcie1-0-clkreq-hog {
362		gpio-hog;
363		gpios = <4 GPIO_ACTIVE_LOW>;
364		input;
365		line-name = "pcie1.0-clkreq";
366	};
367
368	/* CON2 */
369	pcie1-0-w-disable-hog {
370		gpio-hog;
371		gpios = <7 GPIO_ACTIVE_LOW>;
372		output-low;
373		line-name = "pcie1.0-w-disable";
374	};
375};
376