1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP11x. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "armada-common.dtsi" 12 13#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) 14 15/ { 16 /* 17 * The contents of the node are defined below, in order to 18 * save one indentation level 19 */ 20 CP11X_NAME: CP11X_NODE_NAME(bus) { }; 21 22 /* 23 * CPs only have one sensor in the thermal IC. 24 * 25 * The cooling maps are empty as there are no cooling devices. 26 */ 27 thermal-zones { 28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) { 29 polling-delay-passive = <0>; /* Interrupt driven */ 30 polling-delay = <0>; /* Interrupt driven */ 31 32 thermal-sensors = <&CP11X_LABEL(thermal) 0>; 33 34 trips { 35 CP11X_LABEL(crit): crit { 36 temperature = <100000>; /* mC degrees */ 37 hysteresis = <2000>; /* mC degrees */ 38 type = "critical"; 39 }; 40 }; 41 42 cooling-maps { }; 43 }; 44 }; 45}; 46 47&CP11X_NAME { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 compatible = "simple-bus"; 51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>; 52 ranges; 53 54 bus@CP11X_BASE { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 compatible = "simple-bus"; 58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; 59 60 CP11X_LABEL(ethernet): ethernet@0 { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 compatible = "marvell,armada-7k-pp22"; 64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; 65 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, 66 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, 67 <&CP11X_LABEL(clk) 1 18>; 68 clock-names = "pp_clk", "gop_clk", 69 "mg_clk", "mg_core_clk", "axi_clk"; 70 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 71 status = "disabled"; 72 dma-coherent; 73 74 CP11X_LABEL(eth0): ethernet-port@0 { 75 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, 76 <43 IRQ_TYPE_LEVEL_HIGH>, 77 <47 IRQ_TYPE_LEVEL_HIGH>, 78 <51 IRQ_TYPE_LEVEL_HIGH>, 79 <55 IRQ_TYPE_LEVEL_HIGH>, 80 <59 IRQ_TYPE_LEVEL_HIGH>, 81 <63 IRQ_TYPE_LEVEL_HIGH>, 82 <67 IRQ_TYPE_LEVEL_HIGH>, 83 <71 IRQ_TYPE_LEVEL_HIGH>, 84 <129 IRQ_TYPE_LEVEL_HIGH>; 85 interrupt-names = "hif0", "hif1", "hif2", 86 "hif3", "hif4", "hif5", "hif6", "hif7", 87 "hif8", "link"; 88 reg = <0>; 89 port-id = <0>; /* For backward compatibility. */ 90 gop-port-id = <0>; 91 status = "disabled"; 92 }; 93 94 CP11X_LABEL(eth1): ethernet-port@1 { 95 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, 96 <44 IRQ_TYPE_LEVEL_HIGH>, 97 <48 IRQ_TYPE_LEVEL_HIGH>, 98 <52 IRQ_TYPE_LEVEL_HIGH>, 99 <56 IRQ_TYPE_LEVEL_HIGH>, 100 <60 IRQ_TYPE_LEVEL_HIGH>, 101 <64 IRQ_TYPE_LEVEL_HIGH>, 102 <68 IRQ_TYPE_LEVEL_HIGH>, 103 <72 IRQ_TYPE_LEVEL_HIGH>, 104 <128 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-names = "hif0", "hif1", "hif2", 106 "hif3", "hif4", "hif5", "hif6", "hif7", 107 "hif8", "link"; 108 reg = <1>; 109 port-id = <1>; /* For backward compatibility. */ 110 gop-port-id = <2>; 111 status = "disabled"; 112 }; 113 114 CP11X_LABEL(eth2): ethernet-port@2 { 115 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, 116 <45 IRQ_TYPE_LEVEL_HIGH>, 117 <49 IRQ_TYPE_LEVEL_HIGH>, 118 <53 IRQ_TYPE_LEVEL_HIGH>, 119 <57 IRQ_TYPE_LEVEL_HIGH>, 120 <61 IRQ_TYPE_LEVEL_HIGH>, 121 <65 IRQ_TYPE_LEVEL_HIGH>, 122 <69 IRQ_TYPE_LEVEL_HIGH>, 123 <73 IRQ_TYPE_LEVEL_HIGH>, 124 <127 IRQ_TYPE_LEVEL_HIGH>; 125 interrupt-names = "hif0", "hif1", "hif2", 126 "hif3", "hif4", "hif5", "hif6", "hif7", 127 "hif8", "link"; 128 reg = <2>; 129 port-id = <2>; /* For backward compatibility. */ 130 gop-port-id = <3>; 131 status = "disabled"; 132 }; 133 }; 134 135 CP11X_LABEL(comphy): phy@120000 { 136 compatible = "marvell,comphy-cp110"; 137 reg = <0x120000 0x6000>; 138 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 139 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, 140 <&CP11X_LABEL(clk) 1 18>; 141 clock-names = "mg_clk", "mg_core_clk", "axi_clk"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 CP11X_LABEL(comphy0): phy@0 { 146 reg = <0>; 147 #phy-cells = <1>; 148 }; 149 150 CP11X_LABEL(comphy1): phy@1 { 151 reg = <1>; 152 #phy-cells = <1>; 153 }; 154 155 CP11X_LABEL(comphy2): phy@2 { 156 reg = <2>; 157 #phy-cells = <1>; 158 }; 159 160 CP11X_LABEL(comphy3): phy@3 { 161 reg = <3>; 162 #phy-cells = <1>; 163 }; 164 165 CP11X_LABEL(comphy4): phy@4 { 166 reg = <4>; 167 #phy-cells = <1>; 168 }; 169 170 CP11X_LABEL(comphy5): phy@5 { 171 reg = <5>; 172 #phy-cells = <1>; 173 }; 174 }; 175 176 CP11X_LABEL(mdio): mdio@12a200 { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 compatible = "marvell,orion-mdio"; 180 reg = <0x12a200 0x10>; 181 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>, 182 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; 183 status = "disabled"; 184 }; 185 186 CP11X_LABEL(xmdio): mdio@12a600 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "marvell,xmdio"; 190 reg = <0x12a600 0x10>; 191 clocks = <&CP11X_LABEL(clk) 1 5>, 192 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; 193 status = "disabled"; 194 }; 195 196 CP11X_LABEL(icu): interrupt-controller@1e0000 { 197 compatible = "marvell,cp110-icu"; 198 reg = <0x1e0000 0x440>; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 202 CP11X_LABEL(icu_nsr): interrupt-controller@10 { 203 compatible = "marvell,cp110-icu-nsr"; 204 reg = <0x10 0x20>; 205 #address-cells = <0>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 msi-parent = <&gicp>; 209 }; 210 211 CP11X_LABEL(icu_sei): interrupt-controller@50 { 212 compatible = "marvell,cp110-icu-sei"; 213 reg = <0x50 0x10>; 214 #interrupt-cells = <2>; 215 interrupt-controller; 216 msi-parent = <&sei>; 217 }; 218 }; 219 220 CP11X_LABEL(rtc): rtc@284000 { 221 compatible = "marvell,armada-8k-rtc"; 222 reg = <0x284000 0x20>, <0x284080 0x24>; 223 reg-names = "rtc", "rtc-soc"; 224 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 227 CP11X_LABEL(syscon0): system-controller@440000 { 228 compatible = "syscon", "simple-mfd"; 229 reg = <0x440000 0x2000>; 230 231 CP11X_LABEL(clk): clock { 232 compatible = "marvell,cp110-clock"; 233 #clock-cells = <2>; 234 }; 235 236 CP11X_LABEL(gpio1): gpio@100 { 237 compatible = "marvell,armada-8k-gpio"; 238 offset = <0x100>; 239 ngpios = <32>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; 243 marvell,pwm-offset = <0x1f0>; 244 #pwm-cells = <2>; 245 interrupt-controller; 246 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, 247 <85 IRQ_TYPE_LEVEL_HIGH>, 248 <84 IRQ_TYPE_LEVEL_HIGH>, 249 <83 IRQ_TYPE_LEVEL_HIGH>; 250 #interrupt-cells = <2>; 251 clock-names = "core", "axi"; 252 clocks = <&CP11X_LABEL(clk) 1 21>, 253 <&CP11X_LABEL(clk) 1 17>; 254 status = "disabled"; 255 }; 256 257 CP11X_LABEL(gpio2): gpio@140 { 258 compatible = "marvell,armada-8k-gpio"; 259 offset = <0x140>; 260 ngpios = <31>; 261 gpio-controller; 262 #gpio-cells = <2>; 263 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; 264 marvell,pwm-offset = <0x1f0>; 265 #pwm-cells = <2>; 266 interrupt-controller; 267 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, 268 <81 IRQ_TYPE_LEVEL_HIGH>, 269 <80 IRQ_TYPE_LEVEL_HIGH>, 270 <79 IRQ_TYPE_LEVEL_HIGH>; 271 #interrupt-cells = <2>; 272 clock-names = "core", "axi"; 273 clocks = <&CP11X_LABEL(clk) 1 21>, 274 <&CP11X_LABEL(clk) 1 17>; 275 status = "disabled"; 276 }; 277 }; 278 279 CP11X_LABEL(syscon1): system-controller@400000 { 280 compatible = "syscon", "simple-mfd"; 281 reg = <0x400000 0x1000>; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 285 CP11X_LABEL(thermal): thermal-sensor@70 { 286 compatible = "marvell,armada-cp110-thermal"; 287 reg = <0x70 0x10>; 288 interrupts-extended = 289 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; 290 #thermal-sensor-cells = <1>; 291 }; 292 }; 293 294 CP11X_LABEL(utmi): utmi@580000 { 295 compatible = "marvell,cp110-utmi-phy"; 296 reg = <0x580000 0x2000>; 297 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 302 CP11X_LABEL(utmi0): usb-phy@0 { 303 reg = <0>; 304 #phy-cells = <0>; 305 }; 306 307 CP11X_LABEL(utmi1): usb-phy@1 { 308 reg = <1>; 309 #phy-cells = <0>; 310 }; 311 }; 312 313 CP11X_LABEL(usb3_0): usb@500000 { 314 compatible = "marvell,armada-8k-xhci", 315 "generic-xhci"; 316 reg = <0x500000 0x4000>; 317 dma-coherent; 318 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; 319 clock-names = "core", "reg"; 320 clocks = <&CP11X_LABEL(clk) 1 22>, 321 <&CP11X_LABEL(clk) 1 16>; 322 status = "disabled"; 323 }; 324 325 CP11X_LABEL(usb3_1): usb@510000 { 326 compatible = "marvell,armada-8k-xhci", 327 "generic-xhci"; 328 reg = <0x510000 0x4000>; 329 dma-coherent; 330 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; 331 clock-names = "core", "reg"; 332 clocks = <&CP11X_LABEL(clk) 1 23>, 333 <&CP11X_LABEL(clk) 1 16>; 334 status = "disabled"; 335 }; 336 337 CP11X_LABEL(sata0): sata@540000 { 338 compatible = "marvell,armada-8k-ahci", 339 "generic-ahci"; 340 reg = <0x540000 0x30000>; 341 dma-coherent; 342 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&CP11X_LABEL(clk) 1 15>, 344 <&CP11X_LABEL(clk) 1 16>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 349 sata-port@0 { 350 reg = <0>; 351 status = "disabled"; 352 }; 353 354 sata-port@1 { 355 reg = <1>; 356 status = "disabled"; 357 }; 358 }; 359 360 CP11X_LABEL(xor0): xor@6a0000 { 361 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 362 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 363 dma-coherent; 364 msi-parent = <&gic_v2m0>; 365 clock-names = "core", "reg"; 366 clocks = <&CP11X_LABEL(clk) 1 8>, 367 <&CP11X_LABEL(clk) 1 14>; 368 }; 369 370 CP11X_LABEL(xor1): xor@6c0000 { 371 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 372 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 373 dma-coherent; 374 msi-parent = <&gic_v2m0>; 375 clock-names = "core", "reg"; 376 clocks = <&CP11X_LABEL(clk) 1 7>, 377 <&CP11X_LABEL(clk) 1 14>; 378 }; 379 380 CP11X_LABEL(spi0): spi@700600 { 381 compatible = "marvell,armada-380-spi"; 382 reg = <0x700600 0x50>; 383 #address-cells = <0x1>; 384 #size-cells = <0x0>; 385 clock-names = "core", "axi"; 386 clocks = <&CP11X_LABEL(clk) 1 21>, 387 <&CP11X_LABEL(clk) 1 17>; 388 status = "disabled"; 389 }; 390 391 CP11X_LABEL(spi1): spi@700680 { 392 compatible = "marvell,armada-380-spi"; 393 reg = <0x700680 0x50>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clock-names = "core", "axi"; 397 clocks = <&CP11X_LABEL(clk) 1 21>, 398 <&CP11X_LABEL(clk) 1 17>; 399 status = "disabled"; 400 }; 401 402 CP11X_LABEL(i2c0): i2c@701000 { 403 compatible = "marvell,mv78230-i2c"; 404 reg = <0x701000 0x20>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; 408 clock-names = "core", "reg"; 409 clocks = <&CP11X_LABEL(clk) 1 21>, 410 <&CP11X_LABEL(clk) 1 17>; 411 status = "disabled"; 412 }; 413 414 CP11X_LABEL(i2c1): i2c@701100 { 415 compatible = "marvell,mv78230-i2c"; 416 reg = <0x701100 0x20>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; 420 clock-names = "core", "reg"; 421 clocks = <&CP11X_LABEL(clk) 1 21>, 422 <&CP11X_LABEL(clk) 1 17>; 423 status = "disabled"; 424 }; 425 426 CP11X_LABEL(uart0): serial@702000 { 427 compatible = "snps,dw-apb-uart"; 428 reg = <0x702000 0x100>; 429 reg-shift = <2>; 430 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; 431 reg-io-width = <1>; 432 clock-names = "baudclk", "apb_pclk"; 433 clocks = <&CP11X_LABEL(clk) 1 21>, 434 <&CP11X_LABEL(clk) 1 17>; 435 status = "disabled"; 436 }; 437 438 CP11X_LABEL(uart1): serial@702100 { 439 compatible = "snps,dw-apb-uart"; 440 reg = <0x702100 0x100>; 441 reg-shift = <2>; 442 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; 443 reg-io-width = <1>; 444 clock-names = "baudclk", "apb_pclk"; 445 clocks = <&CP11X_LABEL(clk) 1 21>, 446 <&CP11X_LABEL(clk) 1 17>; 447 status = "disabled"; 448 }; 449 450 CP11X_LABEL(uart2): serial@702200 { 451 compatible = "snps,dw-apb-uart"; 452 reg = <0x702200 0x100>; 453 reg-shift = <2>; 454 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; 455 reg-io-width = <1>; 456 clock-names = "baudclk", "apb_pclk"; 457 clocks = <&CP11X_LABEL(clk) 1 21>, 458 <&CP11X_LABEL(clk) 1 17>; 459 status = "disabled"; 460 }; 461 462 CP11X_LABEL(uart3): serial@702300 { 463 compatible = "snps,dw-apb-uart"; 464 reg = <0x702300 0x100>; 465 reg-shift = <2>; 466 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 467 reg-io-width = <1>; 468 clock-names = "baudclk", "apb_pclk"; 469 clocks = <&CP11X_LABEL(clk) 1 21>, 470 <&CP11X_LABEL(clk) 1 17>; 471 status = "disabled"; 472 }; 473 474 CP11X_LABEL(nand_controller): nand-controller@720000 { 475 /* 476 * Due to the limitation of the pins available 477 * this controller is only usable on the CPM 478 * for A7K and on the CPS for A8K. 479 */ 480 compatible = "marvell,armada-8k-nand-controller", 481 "marvell,armada370-nand-controller"; 482 reg = <0x720000 0x54>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; 486 clock-names = "core", "reg"; 487 clocks = <&CP11X_LABEL(clk) 1 2>, 488 <&CP11X_LABEL(clk) 1 17>; 489 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 490 status = "disabled"; 491 }; 492 493 CP11X_LABEL(trng): trng@760000 { 494 compatible = "marvell,armada-8k-rng", 495 "inside-secure,safexcel-eip76"; 496 reg = <0x760000 0x7d>; 497 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; 498 clock-names = "core", "reg"; 499 clocks = <&CP11X_LABEL(clk) 1 25>, 500 <&CP11X_LABEL(clk) 1 17>; 501 status = "okay"; 502 }; 503 504 CP11X_LABEL(sdhci0): mmc@780000 { 505 compatible = "marvell,armada-cp110-sdhci"; 506 reg = <0x780000 0x300>; 507 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 508 clock-names = "core", "axi"; 509 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>; 510 dma-coherent; 511 status = "disabled"; 512 }; 513 514 CP11X_LABEL(crypto): crypto@800000 { 515 compatible = "inside-secure,safexcel-eip197b"; 516 reg = <0x800000 0x200000>; 517 interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, 518 <89 IRQ_TYPE_LEVEL_HIGH>, 519 <90 IRQ_TYPE_LEVEL_HIGH>, 520 <91 IRQ_TYPE_LEVEL_HIGH>, 521 <92 IRQ_TYPE_LEVEL_HIGH>, 522 <87 IRQ_TYPE_LEVEL_HIGH>; 523 interrupt-names = "ring0", "ring1", "ring2", "ring3", 524 "eip", "mem"; 525 clock-names = "core", "reg"; 526 clocks = <&CP11X_LABEL(clk) 1 26>, 527 <&CP11X_LABEL(clk) 1 17>; 528 dma-coherent; 529 }; 530 }; 531 532 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { 533 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 534 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, 535 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; 536 reg-names = "ctrl", "config"; 537 #address-cells = <3>; 538 #size-cells = <2>; 539 #interrupt-cells = <1>; 540 device_type = "pci"; 541 dma-coherent; 542 msi-parent = <&gic_v2m0>; 543 544 bus-range = <0 0xff>; 545 /* non-prefetchable memory */ 546 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; 547 interrupt-map-mask = <0 0 0 0>; 548 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; 549 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 550 num-lanes = <1>; 551 clock-names = "core", "reg"; 552 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; 553 status = "disabled"; 554 }; 555 556 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { 557 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 558 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, 559 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; 560 reg-names = "ctrl", "config"; 561 #address-cells = <3>; 562 #size-cells = <2>; 563 #interrupt-cells = <1>; 564 device_type = "pci"; 565 dma-coherent; 566 msi-parent = <&gic_v2m0>; 567 568 bus-range = <0 0xff>; 569 /* non-prefetchable memory */ 570 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; 571 interrupt-map-mask = <0 0 0 0>; 572 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; 573 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 574 575 num-lanes = <1>; 576 clock-names = "core", "reg"; 577 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; 578 status = "disabled"; 579 }; 580 581 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { 582 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 583 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, 584 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; 585 reg-names = "ctrl", "config"; 586 #address-cells = <3>; 587 #size-cells = <2>; 588 #interrupt-cells = <1>; 589 device_type = "pci"; 590 dma-coherent; 591 msi-parent = <&gic_v2m0>; 592 593 bus-range = <0 0xff>; 594 /* non-prefetchable memory */ 595 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; 596 interrupt-map-mask = <0 0 0 0>; 597 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; 598 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 599 600 num-lanes = <1>; 601 clock-names = "core", "reg"; 602 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; 603 status = "disabled"; 604 }; 605}; 606