1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2bf32f2aeSHanna Hawa/* 3bf32f2aeSHanna Hawa * Copyright (C) 2017 Marvell Technology Group Ltd. 4bf32f2aeSHanna Hawa * 5bf32f2aeSHanna Hawa * Device Tree file for Marvell Armada AP810. 6bf32f2aeSHanna Hawa */ 7bf32f2aeSHanna Hawa 8bf32f2aeSHanna Hawa#include <dt-bindings/interrupt-controller/arm-gic.h> 9bf32f2aeSHanna Hawa 10bf32f2aeSHanna Hawa/dts-v1/; 11bf32f2aeSHanna Hawa 12bf32f2aeSHanna Hawa/ { 13bf32f2aeSHanna Hawa model = "Marvell Armada AP810"; 14bf32f2aeSHanna Hawa compatible = "marvell,armada-ap810"; 15bf32f2aeSHanna Hawa #address-cells = <2>; 16bf32f2aeSHanna Hawa #size-cells = <2>; 17bf32f2aeSHanna Hawa 18bf32f2aeSHanna Hawa aliases { 19bf32f2aeSHanna Hawa serial0 = &uart0_ap0; 20bf32f2aeSHanna Hawa serial1 = &uart1_ap0; 21bf32f2aeSHanna Hawa }; 22bf32f2aeSHanna Hawa 23bf32f2aeSHanna Hawa psci { 24bf32f2aeSHanna Hawa compatible = "arm,psci-0.2"; 25bf32f2aeSHanna Hawa method = "smc"; 26bf32f2aeSHanna Hawa }; 27bf32f2aeSHanna Hawa 28bf32f2aeSHanna Hawa ap810-ap0 { 29bf32f2aeSHanna Hawa #address-cells = <2>; 30bf32f2aeSHanna Hawa #size-cells = <2>; 31bf32f2aeSHanna Hawa compatible = "simple-bus"; 32bf32f2aeSHanna Hawa interrupt-parent = <&gic>; 33bf32f2aeSHanna Hawa ranges; 34bf32f2aeSHanna Hawa 35bf32f2aeSHanna Hawa config-space@e8000000 { 36bf32f2aeSHanna Hawa #address-cells = <1>; 37bf32f2aeSHanna Hawa #size-cells = <1>; 38bf32f2aeSHanna Hawa compatible = "simple-bus"; 39bf32f2aeSHanna Hawa ranges = <0x0 0x0 0xe8000000 0x4000000>; 40bf32f2aeSHanna Hawa interrupt-parent = <&gic>; 41bf32f2aeSHanna Hawa 42bf32f2aeSHanna Hawa gic: interrupt-controller@3000000 { 43bf32f2aeSHanna Hawa compatible = "arm,gic-v3"; 44bf32f2aeSHanna Hawa #interrupt-cells = <3>; 45bf32f2aeSHanna Hawa #address-cells = <1>; 46bf32f2aeSHanna Hawa #size-cells = <1>; 47bf32f2aeSHanna Hawa interrupt-controller; 48bf32f2aeSHanna Hawa interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 49bf32f2aeSHanna Hawa ranges; 50bf32f2aeSHanna Hawa 51bf32f2aeSHanna Hawa reg = <0x3000000 0x10000>, /* GICD */ 52bf32f2aeSHanna Hawa <0x3060000 0x100000>, /* GICR */ 53bf32f2aeSHanna Hawa <0x00c0000 0x2000>, /* GICC */ 54bf32f2aeSHanna Hawa <0x00d0000 0x1000>, /* GICH */ 55bf32f2aeSHanna Hawa <0x00e0000 0x2000>; /* GICV */ 56bf32f2aeSHanna Hawa 57*fce7defbSRob Herring gic_its_ap0: msi-controller@3040000 { 58bf32f2aeSHanna Hawa compatible = "arm,gic-v3-its"; 59bf32f2aeSHanna Hawa msi-controller; 60bf32f2aeSHanna Hawa #msi-cells = <1>; 61bf32f2aeSHanna Hawa reg = <0x3040000 0x20000>; 62bf32f2aeSHanna Hawa }; 63bf32f2aeSHanna Hawa }; 64bf32f2aeSHanna Hawa 65bf32f2aeSHanna Hawa timer { 66bf32f2aeSHanna Hawa compatible = "arm,armv8-timer"; 67bf32f2aeSHanna Hawa interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 68bf32f2aeSHanna Hawa <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 69bf32f2aeSHanna Hawa <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 70bf32f2aeSHanna Hawa <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 71bf32f2aeSHanna Hawa }; 72bf32f2aeSHanna Hawa 73bf32f2aeSHanna Hawa xor@400000 { 74bf32f2aeSHanna Hawa compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 75bf32f2aeSHanna Hawa reg = <0x400000 0x1000>, 76bf32f2aeSHanna Hawa <0x410000 0x1000>; 77bf32f2aeSHanna Hawa msi-parent = <&gic_its_ap0 0xa0>; 78bf32f2aeSHanna Hawa dma-coherent; 79bf32f2aeSHanna Hawa }; 80bf32f2aeSHanna Hawa 81bf32f2aeSHanna Hawa xor@420000 { 82bf32f2aeSHanna Hawa compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 83bf32f2aeSHanna Hawa reg = <0x420000 0x1000>, 84bf32f2aeSHanna Hawa <0x430000 0x1000>; 85bf32f2aeSHanna Hawa msi-parent = <&gic_its_ap0 0xa1>; 86bf32f2aeSHanna Hawa dma-coherent; 87bf32f2aeSHanna Hawa }; 88bf32f2aeSHanna Hawa 89bf32f2aeSHanna Hawa xor@440000 { 90bf32f2aeSHanna Hawa compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 91bf32f2aeSHanna Hawa reg = <0x440000 0x1000>, 92bf32f2aeSHanna Hawa <0x450000 0x1000>; 93bf32f2aeSHanna Hawa msi-parent = <&gic_its_ap0 0xa2>; 94bf32f2aeSHanna Hawa dma-coherent; 95bf32f2aeSHanna Hawa }; 96bf32f2aeSHanna Hawa 97bf32f2aeSHanna Hawa xor@460000 { 98bf32f2aeSHanna Hawa compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 99bf32f2aeSHanna Hawa reg = <0x460000 0x1000>, 100bf32f2aeSHanna Hawa <0x470000 0x1000>; 101bf32f2aeSHanna Hawa msi-parent = <&gic_its_ap0 0xa3>; 102bf32f2aeSHanna Hawa dma-coherent; 103bf32f2aeSHanna Hawa }; 104bf32f2aeSHanna Hawa 105bf32f2aeSHanna Hawa uart0_ap0: serial@512000 { 106bf32f2aeSHanna Hawa compatible = "snps,dw-apb-uart"; 107bf32f2aeSHanna Hawa reg = <0x512000 0x100>; 108bf32f2aeSHanna Hawa reg-shift = <2>; 109bf32f2aeSHanna Hawa interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 110bf32f2aeSHanna Hawa reg-io-width = <1>; 111bf32f2aeSHanna Hawa status = "disabled"; 112bf32f2aeSHanna Hawa }; 113bf32f2aeSHanna Hawa 114bf32f2aeSHanna Hawa uart1_ap0: serial@512100 { 115bf32f2aeSHanna Hawa compatible = "snps,dw-apb-uart"; 116bf32f2aeSHanna Hawa reg = <0x512100 0x100>; 117bf32f2aeSHanna Hawa reg-shift = <2>; 118bf32f2aeSHanna Hawa interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 119bf32f2aeSHanna Hawa reg-io-width = <1>; 120bf32f2aeSHanna Hawa status = "disabled"; 121bf32f2aeSHanna Hawa }; 122bf32f2aeSHanna Hawa }; 123bf32f2aeSHanna Hawa }; 124bf32f2aeSHanna Hawa}; 125