1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2023, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/intel,agilex5-clkmgr.h> 12 13/ { 14 compatible = "intel,socfpga-agilex5"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 service_reserved: svcbuffer@0 { 24 compatible = "shared-dma-pool"; 25 reg = <0x0 0x80000000 0x0 0x2000000>; 26 alignment = <0x1000>; 27 no-map; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 compatible = "arm,cortex-a55"; 37 reg = <0x0>; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 }; 41 42 cpu1: cpu@1 { 43 compatible = "arm,cortex-a55"; 44 reg = <0x100>; 45 device_type = "cpu"; 46 enable-method = "psci"; 47 }; 48 49 cpu2: cpu@2 { 50 compatible = "arm,cortex-a76"; 51 reg = <0x200>; 52 device_type = "cpu"; 53 enable-method = "psci"; 54 }; 55 56 cpu3: cpu@3 { 57 compatible = "arm,cortex-a76"; 58 reg = <0x300>; 59 device_type = "cpu"; 60 enable-method = "psci"; 61 }; 62 }; 63 64 psci { 65 compatible = "arm,psci-0.2"; 66 method = "smc"; 67 }; 68 69 intc: interrupt-controller@1d000000 { 70 compatible = "arm,gic-v3"; 71 reg = <0x0 0x1d000000 0 0x10000>, 72 <0x0 0x1d060000 0 0x100000>; 73 ranges; 74 #interrupt-cells = <3>; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 interrupt-controller; 78 #redistributor-regions = <1>; 79 redistributor-stride = <0x0 0x20000>; 80 81 its: msi-controller@1d040000 { 82 compatible = "arm,gic-v3-its"; 83 reg = <0x0 0x1d040000 0x0 0x20000>; 84 msi-controller; 85 #msi-cells = <1>; 86 }; 87 }; 88 89 /* Clock tree 5 main sources*/ 90 clocks { 91 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 92 #clock-cells = <0>; 93 compatible = "fixed-clock"; 94 clock-frequency = <0>; 95 }; 96 97 cb_intosc_ls_clk: cb-intosc-ls-clk { 98 #clock-cells = <0>; 99 compatible = "fixed-clock"; 100 clock-frequency = <0>; 101 }; 102 103 f2s_free_clk: f2s-free-clk { 104 #clock-cells = <0>; 105 compatible = "fixed-clock"; 106 clock-frequency = <0>; 107 }; 108 109 osc1: osc1 { 110 #clock-cells = <0>; 111 compatible = "fixed-clock"; 112 clock-frequency = <0>; 113 }; 114 115 qspi_clk: qspi-clk { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <200000000>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&intc>; 125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 usbphy0: usbphy { 132 #phy-cells = <0>; 133 compatible = "usb-nop-xceiv"; 134 }; 135 136 soc: soc@0 { 137 compatible = "simple-bus"; 138 ranges = <0 0 0 0xffffffff>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 device_type = "soc"; 142 interrupt-parent = <&intc>; 143 144 clkmgr: clock-controller@10d10000 { 145 compatible = "intel,agilex5-clkmgr"; 146 reg = <0x10d10000 0x1000>; 147 #clock-cells = <1>; 148 }; 149 150 i2c0: i2c@10c02800 { 151 compatible = "snps,designware-i2c"; 152 reg = <0x10c02800 0x100>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 156 resets = <&rst I2C0_RESET>; 157 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 158 status = "disabled"; 159 }; 160 161 i2c1: i2c@10c02900 { 162 compatible = "snps,designware-i2c"; 163 reg = <0x10c02900 0x100>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 167 resets = <&rst I2C1_RESET>; 168 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 169 status = "disabled"; 170 }; 171 172 i2c2: i2c@10c02a00 { 173 compatible = "snps,designware-i2c"; 174 reg = <0x10c02a00 0x100>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 178 resets = <&rst I2C2_RESET>; 179 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 180 status = "disabled"; 181 }; 182 183 i2c3: i2c@10c02b00 { 184 compatible = "snps,designware-i2c"; 185 reg = <0x10c02b00 0x100>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 189 resets = <&rst I2C3_RESET>; 190 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 191 status = "disabled"; 192 }; 193 194 i2c4: i2c@10c02c00 { 195 compatible = "snps,designware-i2c"; 196 reg = <0x10c02c00 0x100>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 200 resets = <&rst I2C4_RESET>; 201 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 202 status = "disabled"; 203 }; 204 205 i3c0: i3c@10da0000 { 206 compatible = "snps,dw-i3c-master-1.00a"; 207 reg = <0x10da0000 0x1000>; 208 #address-cells = <3>; 209 #size-cells = <0>; 210 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 212 status = "disabled"; 213 }; 214 215 i3c1: i3c@10da1000 { 216 compatible = "snps,dw-i3c-master-1.00a"; 217 reg = <0x10da1000 0x1000>; 218 #address-cells = <3>; 219 #size-cells = <0>; 220 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 222 status = "disabled"; 223 }; 224 225 gpio0: gpio@10c03200 { 226 compatible = "snps,dw-apb-gpio"; 227 reg = <0x10c03200 0x100>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 resets = <&rst GPIO0_RESET>; 231 status = "disabled"; 232 233 porta: gpio-controller@0 { 234 compatible = "snps,dw-apb-gpio-port"; 235 reg = <0>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 snps,nr-gpios = <24>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 }; 244 245 gpio1: gpio@10c03300 { 246 compatible = "snps,dw-apb-gpio"; 247 reg = <0x10c03300 0x100>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 resets = <&rst GPIO1_RESET>; 251 status = "disabled"; 252 253 portb: gpio-controller@0 { 254 compatible = "snps,dw-apb-gpio-port"; 255 reg = <0>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 snps,nr-gpios = <24>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 }; 264 265 nand: nand-controller@10b80000 { 266 compatible = "cdns,hp-nfc"; 267 reg = <0x10b80000 0x10000>, 268 <0x10840000 0x10000>; 269 reg-names = "reg", "sdma"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; 274 cdns,board-delay-ps = <4830>; 275 status = "disabled"; 276 }; 277 278 ocram: sram@0 { 279 compatible = "mmio-sram"; 280 reg = <0x00000000 0x80000>; 281 ranges = <0 0 0x80000>; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 }; 285 286 dmac0: dma-controller@10db0000 { 287 compatible = "snps,axi-dma-1.01a"; 288 reg = <0x10db0000 0x500>; 289 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 290 <&clkmgr AGILEX5_L4_MP_CLK>; 291 clock-names = "core-clk", "cfgr-clk"; 292 interrupt-parent = <&intc>; 293 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 294 #dma-cells = <1>; 295 dma-channels = <4>; 296 snps,dma-masters = <1>; 297 snps,data-width = <2>; 298 snps,block-size = <32767 32767 32767 32767>; 299 snps,priority = <0 1 2 3>; 300 snps,axi-max-burst-len = <8>; 301 }; 302 303 dmac1: dma-controller@10dc0000 { 304 compatible = "snps,axi-dma-1.01a"; 305 reg = <0x10dc0000 0x500>; 306 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 307 <&clkmgr AGILEX5_L4_MP_CLK>; 308 clock-names = "core-clk", "cfgr-clk"; 309 interrupt-parent = <&intc>; 310 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 311 #dma-cells = <1>; 312 dma-channels = <4>; 313 snps,dma-masters = <1>; 314 snps,data-width = <2>; 315 snps,block-size = <32767 32767 32767 32767>; 316 snps,priority = <0 1 2 3>; 317 snps,axi-max-burst-len = <8>; 318 }; 319 320 rst: rstmgr@10d11000 { 321 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 322 reg = <0x10d11000 0x1000>; 323 #reset-cells = <1>; 324 }; 325 326 spi0: spi@10da4000 { 327 compatible = "snps,dw-apb-ssi"; 328 reg = <0x10da4000 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 332 resets = <&rst SPIM0_RESET>; 333 reset-names = "spi"; 334 reg-io-width = <4>; 335 num-cs = <4>; 336 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 337 dmas = <&dmac0 16>, <&dmac0 17>; 338 dma-names = "tx", "rx"; 339 status = "disabled"; 340 341 }; 342 343 spi1: spi@10da5000 { 344 compatible = "snps,dw-apb-ssi"; 345 reg = <0x10da5000 0x1000>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 349 resets = <&rst SPIM1_RESET>; 350 reset-names = "spi"; 351 reg-io-width = <4>; 352 num-cs = <4>; 353 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 354 dmas = <&dmac0 20>, <&dmac0 21>; 355 dma-names = "tx", "rx"; 356 status = "disabled"; 357 }; 358 359 sysmgr: sysmgr@10d12000 { 360 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 361 reg = <0x10d12000 0x500>; 362 }; 363 364 timer0: timer0@10c03000 { 365 compatible = "snps,dw-apb-timer"; 366 reg = <0x10c03000 0x100>; 367 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 369 clock-names = "timer"; 370 }; 371 372 timer1: timer1@10c03100 { 373 compatible = "snps,dw-apb-timer"; 374 reg = <0x10c03100 0x100>; 375 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 377 clock-names = "timer"; 378 }; 379 380 timer2: timer2@10d00000 { 381 compatible = "snps,dw-apb-timer"; 382 reg = <0x10d00000 0x100>; 383 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 385 clock-names = "timer"; 386 }; 387 388 timer3: timer3@10d00100 { 389 compatible = "snps,dw-apb-timer"; 390 reg = <0x10d00100 0x100>; 391 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 393 clock-names = "timer"; 394 }; 395 396 uart0: serial@10c02000 { 397 compatible = "snps,dw-apb-uart"; 398 reg = <0x10c02000 0x100>; 399 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 resets = <&rst UART0_RESET>; 403 status = "disabled"; 404 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 405 }; 406 407 uart1: serial@10c02100 { 408 compatible = "snps,dw-apb-uart"; 409 reg = <0x10c02100 0x100>; 410 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 411 reg-shift = <2>; 412 reg-io-width = <4>; 413 resets = <&rst UART1_RESET>; 414 status = "disabled"; 415 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 416 }; 417 418 usb0: usb@10b00000 { 419 compatible = "snps,dwc2"; 420 reg = <0x10b00000 0x40000>; 421 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 422 phys = <&usbphy0>; 423 phy-names = "usb2-phy"; 424 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 425 reset-names = "dwc2", "dwc2-ecc"; 426 clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; 427 clock-names = "otg"; 428 status = "disabled"; 429 }; 430 431 watchdog0: watchdog@10d00200 { 432 compatible = "snps,dw-wdt"; 433 reg = <0x10d00200 0x100>; 434 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 435 resets = <&rst WATCHDOG0_RESET>; 436 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 437 status = "disabled"; 438 }; 439 440 watchdog1: watchdog@10d00300 { 441 compatible = "snps,dw-wdt"; 442 reg = <0x10d00300 0x100>; 443 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 444 resets = <&rst WATCHDOG1_RESET>; 445 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 446 status = "disabled"; 447 }; 448 449 watchdog2: watchdog@10d00400 { 450 compatible = "snps,dw-wdt"; 451 reg = <0x10d00400 0x100>; 452 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 453 resets = <&rst WATCHDOG2_RESET>; 454 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 455 status = "disabled"; 456 }; 457 458 watchdog3: watchdog@10d00500 { 459 compatible = "snps,dw-wdt"; 460 reg = <0x10d00500 0x100>; 461 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 462 resets = <&rst WATCHDOG3_RESET>; 463 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 464 status = "disabled"; 465 }; 466 467 watchdog4: watchdog@10d00600 { 468 compatible = "snps,dw-wdt"; 469 reg = <0x10d00600 0x100>; 470 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 471 resets = <&rst WATCHDOG4_RESET>; 472 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 473 status = "disabled"; 474 }; 475 476 qspi: spi@108d2000 { 477 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 478 reg = <0x108d2000 0x100>, 479 <0x10900000 0x100000>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 483 cdns,fifo-depth = <128>; 484 cdns,fifo-width = <4>; 485 cdns,trigger-address = <0x00000000>; 486 clocks = <&qspi_clk>; 487 status = "disabled"; 488 }; 489 490 gmac0: ethernet@10810000 { 491 compatible = "altr,socfpga-stmmac-agilex5", 492 "snps,dwxgmac-2.10"; 493 reg = <0x10810000 0x3500>; 494 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "macirq"; 496 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 497 reset-names = "stmmaceth", "ahb"; 498 clocks = <&clkmgr AGILEX5_EMAC0_CLK>, 499 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 500 clock-names = "stmmaceth", "ptp_ref"; 501 mac-address = [00 00 00 00 00 00]; 502 tx-fifo-depth = <32768>; 503 rx-fifo-depth = <16384>; 504 snps,multicast-filter-bins = <64>; 505 snps,perfect-filter-entries = <64>; 506 snps,axi-config = <&stmmac_axi_emac0_setup>; 507 snps,mtl-rx-config = <&mtl_rx_emac0_setup>; 508 snps,mtl-tx-config = <&mtl_tx_emac0_setup>; 509 snps,pbl = <32>; 510 snps,tso; 511 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 512 snps,clk-csr = <0>; 513 status = "disabled"; 514 515 stmmac_axi_emac0_setup: stmmac-axi-config { 516 snps,wr_osr_lmt = <31>; 517 snps,rd_osr_lmt = <31>; 518 snps,blen = <0 0 0 32 16 8 4>; 519 }; 520 521 mtl_rx_emac0_setup: rx-queues-config { 522 snps,rx-queues-to-use = <8>; 523 snps,rx-sched-sp; 524 queue0 { 525 snps,dcb-algorithm; 526 snps,map-to-dma-channel = <0x0>; 527 }; 528 queue1 { 529 snps,dcb-algorithm; 530 snps,map-to-dma-channel = <0x1>; 531 }; 532 queue2 { 533 snps,dcb-algorithm; 534 snps,map-to-dma-channel = <0x2>; 535 }; 536 queue3 { 537 snps,dcb-algorithm; 538 snps,map-to-dma-channel = <0x3>; 539 }; 540 queue4 { 541 snps,dcb-algorithm; 542 snps,map-to-dma-channel = <0x4>; 543 }; 544 queue5 { 545 snps,dcb-algorithm; 546 snps,map-to-dma-channel = <0x5>; 547 }; 548 queue6 { 549 snps,dcb-algorithm; 550 snps,map-to-dma-channel = <0x6>; 551 }; 552 queue7 { 553 snps,dcb-algorithm; 554 snps,map-to-dma-channel = <0x7>; 555 }; 556 }; 557 558 mtl_tx_emac0_setup: tx-queues-config { 559 snps,tx-queues-to-use = <8>; 560 snps,tx-sched-wrr; 561 queue0 { 562 snps,weight = <0x09>; 563 snps,dcb-algorithm; 564 }; 565 queue1 { 566 snps,weight = <0x0A>; 567 snps,dcb-algorithm; 568 }; 569 queue2 { 570 snps,weight = <0x0B>; 571 snps,coe-unsupported; 572 snps,dcb-algorithm; 573 }; 574 queue3 { 575 snps,weight = <0x0C>; 576 snps,coe-unsupported; 577 snps,dcb-algorithm; 578 }; 579 queue4 { 580 snps,weight = <0x0D>; 581 snps,coe-unsupported; 582 snps,dcb-algorithm; 583 }; 584 queue5 { 585 snps,weight = <0x0E>; 586 snps,coe-unsupported; 587 snps,dcb-algorithm; 588 }; 589 queue6 { 590 snps,weight = <0x0F>; 591 snps,coe-unsupported; 592 snps,dcb-algorithm; 593 }; 594 queue7 { 595 snps,weight = <0x10>; 596 snps,coe-unsupported; 597 snps,dcb-algorithm; 598 }; 599 }; 600 }; 601 602 gmac1: ethernet@10820000 { 603 compatible = "altr,socfpga-stmmac-agilex5", 604 "snps,dwxgmac-2.10"; 605 reg = <0x10820000 0x3500>; 606 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "macirq"; 608 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 609 reset-names = "stmmaceth", "ahb"; 610 clocks = <&clkmgr AGILEX5_EMAC1_CLK>, 611 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 612 clock-names = "stmmaceth", "ptp_ref"; 613 mac-address = [00 00 00 00 00 00]; 614 tx-fifo-depth = <32768>; 615 rx-fifo-depth = <16384>; 616 snps,multicast-filter-bins = <64>; 617 snps,perfect-filter-entries = <64>; 618 snps,axi-config = <&stmmac_axi_emac1_setup>; 619 snps,mtl-rx-config = <&mtl_rx_emac1_setup>; 620 snps,mtl-tx-config = <&mtl_tx_emac1_setup>; 621 snps,pbl = <32>; 622 snps,tso; 623 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 624 snps,clk-csr = <0>; 625 status = "disabled"; 626 627 stmmac_axi_emac1_setup: stmmac-axi-config { 628 snps,wr_osr_lmt = <31>; 629 snps,rd_osr_lmt = <31>; 630 snps,blen = <0 0 0 32 16 8 4>; 631 }; 632 633 mtl_rx_emac1_setup: rx-queues-config { 634 snps,rx-queues-to-use = <8>; 635 snps,rx-sched-sp; 636 queue0 { 637 snps,dcb-algorithm; 638 snps,map-to-dma-channel = <0x0>; 639 }; 640 queue1 { 641 snps,dcb-algorithm; 642 snps,map-to-dma-channel = <0x1>; 643 }; 644 queue2 { 645 snps,dcb-algorithm; 646 snps,map-to-dma-channel = <0x2>; 647 }; 648 queue3 { 649 snps,dcb-algorithm; 650 snps,map-to-dma-channel = <0x3>; 651 }; 652 queue4 { 653 snps,dcb-algorithm; 654 snps,map-to-dma-channel = <0x4>; 655 }; 656 queue5 { 657 snps,dcb-algorithm; 658 snps,map-to-dma-channel = <0x5>; 659 }; 660 queue6 { 661 snps,dcb-algorithm; 662 snps,map-to-dma-channel = <0x6>; 663 }; 664 queue7 { 665 snps,dcb-algorithm; 666 snps,map-to-dma-channel = <0x7>; 667 }; 668 }; 669 670 mtl_tx_emac1_setup: tx-queues-config { 671 snps,tx-queues-to-use = <8>; 672 snps,tx-sched-wrr; 673 queue0 { 674 snps,weight = <0x09>; 675 snps,dcb-algorithm; 676 }; 677 queue1 { 678 snps,weight = <0x0A>; 679 snps,dcb-algorithm; 680 }; 681 queue2 { 682 snps,weight = <0x0B>; 683 snps,coe-unsupported; 684 snps,dcb-algorithm; 685 }; 686 queue3 { 687 snps,weight = <0x0C>; 688 snps,coe-unsupported; 689 snps,dcb-algorithm; 690 }; 691 queue4 { 692 snps,weight = <0x0D>; 693 snps,coe-unsupported; 694 snps,dcb-algorithm; 695 }; 696 queue5 { 697 snps,weight = <0x0E>; 698 snps,coe-unsupported; 699 snps,dcb-algorithm; 700 }; 701 queue6 { 702 snps,weight = <0x0F>; 703 snps,coe-unsupported; 704 snps,dcb-algorithm; 705 }; 706 queue7 { 707 snps,weight = <0x10>; 708 snps,coe-unsupported; 709 snps,dcb-algorithm; 710 }; 711 }; 712 }; 713 714 gmac2: ethernet@10830000 { 715 compatible = "altr,socfpga-stmmac-agilex5", 716 "snps,dwxgmac-2.10"; 717 reg = <0x10830000 0x3500>; 718 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "macirq"; 720 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 721 reset-names = "stmmaceth", "ahb"; 722 clocks = <&clkmgr AGILEX5_EMAC2_CLK>, 723 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 724 clock-names = "stmmaceth", "ptp_ref"; 725 mac-address = [00 00 00 00 00 00]; 726 tx-fifo-depth = <32768>; 727 rx-fifo-depth = <16384>; 728 snps,multicast-filter-bins = <64>; 729 snps,perfect-filter-entries = <64>; 730 snps,axi-config = <&stmmac_axi_emac2_setup>; 731 snps,mtl-rx-config = <&mtl_rx_emac2_setup>; 732 snps,mtl-tx-config = <&mtl_tx_emac2_setup>; 733 snps,pbl = <32>; 734 snps,tso; 735 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 736 snps,clk-csr = <0>; 737 status = "disabled"; 738 739 stmmac_axi_emac2_setup: stmmac-axi-config { 740 snps,wr_osr_lmt = <31>; 741 snps,rd_osr_lmt = <31>; 742 snps,blen = <0 0 0 32 16 8 4>; 743 }; 744 745 mtl_rx_emac2_setup: rx-queues-config { 746 snps,rx-queues-to-use = <8>; 747 snps,rx-sched-sp; 748 queue0 { 749 snps,dcb-algorithm; 750 snps,map-to-dma-channel = <0x0>; 751 }; 752 queue1 { 753 snps,dcb-algorithm; 754 snps,map-to-dma-channel = <0x1>; 755 }; 756 queue2 { 757 snps,dcb-algorithm; 758 snps,map-to-dma-channel = <0x2>; 759 }; 760 queue3 { 761 snps,dcb-algorithm; 762 snps,map-to-dma-channel = <0x3>; 763 }; 764 queue4 { 765 snps,dcb-algorithm; 766 snps,map-to-dma-channel = <0x4>; 767 }; 768 queue5 { 769 snps,dcb-algorithm; 770 snps,map-to-dma-channel = <0x5>; 771 }; 772 queue6 { 773 snps,dcb-algorithm; 774 snps,map-to-dma-channel = <0x6>; 775 }; 776 queue7 { 777 snps,dcb-algorithm; 778 snps,map-to-dma-channel = <0x7>; 779 }; 780 }; 781 782 mtl_tx_emac2_setup: tx-queues-config { 783 snps,tx-queues-to-use = <8>; 784 snps,tx-sched-wrr; 785 queue0 { 786 snps,weight = <0x09>; 787 snps,dcb-algorithm; 788 }; 789 queue1 { 790 snps,weight = <0x0A>; 791 snps,dcb-algorithm; 792 }; 793 queue2 { 794 snps,weight = <0x0B>; 795 snps,coe-unsupported; 796 snps,dcb-algorithm; 797 }; 798 queue3 { 799 snps,weight = <0x0C>; 800 snps,coe-unsupported; 801 snps,dcb-algorithm; 802 }; 803 queue4 { 804 snps,weight = <0x0D>; 805 snps,coe-unsupported; 806 snps,dcb-algorithm; 807 }; 808 queue5 { 809 snps,weight = <0x0E>; 810 snps,coe-unsupported; 811 snps,dcb-algorithm; 812 }; 813 queue6 { 814 snps,weight = <0x0F>; 815 snps,coe-unsupported; 816 snps,dcb-algorithm; 817 }; 818 queue7 { 819 snps,weight = <0x10>; 820 snps,coe-unsupported; 821 snps,dcb-algorithm; 822 }; 823 }; 824 }; 825 }; 826}; 827