1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 compatible = "intel,socfpga-agilex"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a53"; 21 device_type = "cpu"; 22 enable-method = "psci"; 23 reg = <0x0>; 24 }; 25 26 cpu1: cpu@1 { 27 compatible = "arm,cortex-a53"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 reg = <0x1>; 31 }; 32 33 cpu2: cpu@2 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x2>; 38 }; 39 40 cpu3: cpu@3 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x3>; 45 }; 46 }; 47 48 pmu { 49 compatible = "arm,armv8-pmuv3"; 50 interrupts = <0 120 8>, 51 <0 121 8>, 52 <0 122 8>, 53 <0 123 8>; 54 interrupt-affinity = <&cpu0>, 55 <&cpu1>, 56 <&cpu2>, 57 <&cpu3>; 58 interrupt-parent = <&intc>; 59 }; 60 61 psci { 62 compatible = "arm,psci-0.2"; 63 method = "smc"; 64 }; 65 66 intc: intc@fffc1000 { 67 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 68 #interrupt-cells = <3>; 69 interrupt-controller; 70 reg = <0x0 0xfffc1000 0x0 0x1000>, 71 <0x0 0xfffc2000 0x0 0x2000>, 72 <0x0 0xfffc4000 0x0 0x2000>, 73 <0x0 0xfffc6000 0x0 0x2000>; 74 }; 75 76 soc { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "simple-bus"; 80 device_type = "soc"; 81 interrupt-parent = <&intc>; 82 ranges = <0 0 0 0xffffffff>; 83 84 gmac0: ethernet@ff800000 { 85 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 86 reg = <0xff800000 0x2000>; 87 interrupts = <0 90 4>; 88 interrupt-names = "macirq"; 89 mac-address = [00 00 00 00 00 00]; 90 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 91 reset-names = "stmmaceth", "stmmaceth-ocp"; 92 tx-fifo-depth = <16384>; 93 rx-fifo-depth = <16384>; 94 snps,multicast-filter-bins = <256>; 95 iommus = <&smmu 1>; 96 status = "disabled"; 97 }; 98 99 gmac1: ethernet@ff802000 { 100 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 101 reg = <0xff802000 0x2000>; 102 interrupts = <0 91 4>; 103 interrupt-names = "macirq"; 104 mac-address = [00 00 00 00 00 00]; 105 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 106 reset-names = "stmmaceth", "stmmaceth-ocp"; 107 tx-fifo-depth = <16384>; 108 rx-fifo-depth = <16384>; 109 snps,multicast-filter-bins = <256>; 110 iommus = <&smmu 2>; 111 status = "disabled"; 112 }; 113 114 gmac2: ethernet@ff804000 { 115 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 116 reg = <0xff804000 0x2000>; 117 interrupts = <0 92 4>; 118 interrupt-names = "macirq"; 119 mac-address = [00 00 00 00 00 00]; 120 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 121 reset-names = "stmmaceth", "stmmaceth-ocp"; 122 tx-fifo-depth = <16384>; 123 rx-fifo-depth = <16384>; 124 snps,multicast-filter-bins = <256>; 125 iommus = <&smmu 3>; 126 status = "disabled"; 127 }; 128 129 gpio0: gpio@ffc03200 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "snps,dw-apb-gpio"; 133 reg = <0xffc03200 0x100>; 134 resets = <&rst GPIO0_RESET>; 135 status = "disabled"; 136 137 porta: gpio-controller@0 { 138 compatible = "snps,dw-apb-gpio-port"; 139 gpio-controller; 140 #gpio-cells = <2>; 141 snps,nr-gpios = <24>; 142 reg = <0>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 interrupts = <0 110 4>; 146 }; 147 }; 148 149 gpio1: gpio@ffc03300 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 compatible = "snps,dw-apb-gpio"; 153 reg = <0xffc03300 0x100>; 154 resets = <&rst GPIO1_RESET>; 155 status = "disabled"; 156 157 portb: gpio-controller@0 { 158 compatible = "snps,dw-apb-gpio-port"; 159 gpio-controller; 160 #gpio-cells = <2>; 161 snps,nr-gpios = <24>; 162 reg = <0>; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 interrupts = <0 111 4>; 166 }; 167 }; 168 169 i2c0: i2c@ffc02800 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "snps,designware-i2c"; 173 reg = <0xffc02800 0x100>; 174 interrupts = <0 103 4>; 175 resets = <&rst I2C0_RESET>; 176 status = "disabled"; 177 }; 178 179 i2c1: i2c@ffc02900 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "snps,designware-i2c"; 183 reg = <0xffc02900 0x100>; 184 interrupts = <0 104 4>; 185 resets = <&rst I2C1_RESET>; 186 status = "disabled"; 187 }; 188 189 i2c2: i2c@ffc02a00 { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 compatible = "snps,designware-i2c"; 193 reg = <0xffc02a00 0x100>; 194 interrupts = <0 105 4>; 195 resets = <&rst I2C2_RESET>; 196 status = "disabled"; 197 }; 198 199 i2c3: i2c@ffc02b00 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 compatible = "snps,designware-i2c"; 203 reg = <0xffc02b00 0x100>; 204 interrupts = <0 106 4>; 205 resets = <&rst I2C3_RESET>; 206 status = "disabled"; 207 }; 208 209 i2c4: i2c@ffc02c00 { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 compatible = "snps,designware-i2c"; 213 reg = <0xffc02c00 0x100>; 214 interrupts = <0 107 4>; 215 resets = <&rst I2C4_RESET>; 216 status = "disabled"; 217 }; 218 219 mmc: dwmmc0@ff808000 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "altr,socfpga-dw-mshc"; 223 reg = <0xff808000 0x1000>; 224 interrupts = <0 96 4>; 225 fifo-depth = <0x400>; 226 resets = <&rst SDMMC_RESET>; 227 reset-names = "reset"; 228 iommus = <&smmu 5>; 229 status = "disabled"; 230 }; 231 232 ocram: sram@ffe00000 { 233 compatible = "mmio-sram"; 234 reg = <0xffe00000 0x40000>; 235 }; 236 237 pdma: pdma@ffda0000 { 238 compatible = "arm,pl330", "arm,primecell"; 239 reg = <0xffda0000 0x1000>; 240 interrupts = <0 81 4>, 241 <0 82 4>, 242 <0 83 4>, 243 <0 84 4>, 244 <0 85 4>, 245 <0 86 4>, 246 <0 87 4>, 247 <0 88 4>, 248 <0 89 4>; 249 #dma-cells = <1>; 250 #dma-channels = <8>; 251 #dma-requests = <32>; 252 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 253 reset-names = "dma", "dma-ocp"; 254 }; 255 256 rst: rstmgr@ffd11000 { 257 #reset-cells = <1>; 258 compatible = "altr,stratix10-rst-mgr"; 259 reg = <0xffd11000 0x100>; 260 }; 261 262 smmu: iommu@fa000000 { 263 compatible = "arm,mmu-500", "arm,smmu-v2"; 264 reg = <0xfa000000 0x40000>; 265 #global-interrupts = <2>; 266 #iommu-cells = <1>; 267 interrupt-parent = <&intc>; 268 interrupts = <0 128 4>, /* Global Secure Fault */ 269 <0 129 4>, /* Global Non-secure Fault */ 270 /* Non-secure Context Interrupts (32) */ 271 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 272 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 273 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 274 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 275 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 276 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 277 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 278 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 279 stream-match-mask = <0x7ff0>; 280 status = "disabled"; 281 }; 282 283 spi0: spi@ffda4000 { 284 compatible = "snps,dw-apb-ssi"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <0xffda4000 0x1000>; 288 interrupts = <0 99 4>; 289 resets = <&rst SPIM0_RESET>; 290 reg-io-width = <4>; 291 num-cs = <4>; 292 status = "disabled"; 293 }; 294 295 spi1: spi@ffda5000 { 296 compatible = "snps,dw-apb-ssi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0xffda5000 0x1000>; 300 interrupts = <0 100 4>; 301 resets = <&rst SPIM1_RESET>; 302 reg-io-width = <4>; 303 num-cs = <4>; 304 status = "disabled"; 305 }; 306 307 sysmgr: sysmgr@ffd12000 { 308 compatible = "altr,sys-mgr", "syscon"; 309 reg = <0xffd12000 0x500>; 310 }; 311 312 /* Local timer */ 313 timer { 314 compatible = "arm,armv8-timer"; 315 interrupts = <1 13 0xf08>, 316 <1 14 0xf08>, 317 <1 11 0xf08>, 318 <1 10 0xf08>; 319 }; 320 321 timer0: timer0@ffc03000 { 322 compatible = "snps,dw-apb-timer"; 323 interrupts = <0 113 4>; 324 reg = <0xffc03000 0x100>; 325 }; 326 327 timer1: timer1@ffc03100 { 328 compatible = "snps,dw-apb-timer"; 329 interrupts = <0 114 4>; 330 reg = <0xffc03100 0x100>; 331 }; 332 333 timer2: timer2@ffd00000 { 334 compatible = "snps,dw-apb-timer"; 335 interrupts = <0 115 4>; 336 reg = <0xffd00000 0x100>; 337 }; 338 339 timer3: timer3@ffd00100 { 340 compatible = "snps,dw-apb-timer"; 341 interrupts = <0 116 4>; 342 reg = <0xffd00100 0x100>; 343 }; 344 345 uart0: serial0@ffc02000 { 346 compatible = "snps,dw-apb-uart"; 347 reg = <0xffc02000 0x100>; 348 interrupts = <0 108 4>; 349 reg-shift = <2>; 350 reg-io-width = <4>; 351 resets = <&rst UART0_RESET>; 352 status = "disabled"; 353 }; 354 355 uart1: serial1@ffc02100 { 356 compatible = "snps,dw-apb-uart"; 357 reg = <0xffc02100 0x100>; 358 interrupts = <0 109 4>; 359 reg-shift = <2>; 360 reg-io-width = <4>; 361 resets = <&rst UART1_RESET>; 362 status = "disabled"; 363 }; 364 365 usbphy0: usbphy@0 { 366 #phy-cells = <0>; 367 compatible = "usb-nop-xceiv"; 368 status = "okay"; 369 }; 370 371 usb0: usb@ffb00000 { 372 compatible = "snps,dwc2"; 373 reg = <0xffb00000 0x40000>; 374 interrupts = <0 93 4>; 375 phys = <&usbphy0>; 376 phy-names = "usb2-phy"; 377 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 378 reset-names = "dwc2", "dwc2-ecc"; 379 iommus = <&smmu 6>; 380 status = "disabled"; 381 }; 382 383 usb1: usb@ffb40000 { 384 compatible = "snps,dwc2"; 385 reg = <0xffb40000 0x40000>; 386 interrupts = <0 94 4>; 387 phys = <&usbphy0>; 388 phy-names = "usb2-phy"; 389 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 390 reset-names = "dwc2", "dwc2-ecc"; 391 iommus = <&smmu 7>; 392 status = "disabled"; 393 }; 394 395 watchdog0: watchdog@ffd00200 { 396 compatible = "snps,dw-wdt"; 397 reg = <0xffd00200 0x100>; 398 interrupts = <0 117 4>; 399 resets = <&rst WATCHDOG0_RESET>; 400 status = "disabled"; 401 }; 402 403 watchdog1: watchdog@ffd00300 { 404 compatible = "snps,dw-wdt"; 405 reg = <0xffd00300 0x100>; 406 interrupts = <0 118 4>; 407 resets = <&rst WATCHDOG1_RESET>; 408 status = "disabled"; 409 }; 410 411 watchdog2: watchdog@ffd00400 { 412 compatible = "snps,dw-wdt"; 413 reg = <0xffd00400 0x100>; 414 interrupts = <0 125 4>; 415 resets = <&rst WATCHDOG2_RESET>; 416 status = "disabled"; 417 }; 418 419 watchdog3: watchdog@ffd00500 { 420 compatible = "snps,dw-wdt"; 421 reg = <0xffd00500 0x100>; 422 interrupts = <0 126 4>; 423 resets = <&rst WATCHDOG3_RESET>; 424 status = "disabled"; 425 }; 426 427 sdr: sdr@f8011100 { 428 compatible = "altr,sdr-ctl", "syscon"; 429 reg = <0xf8011100 0xc0>; 430 }; 431 432 qspi: spi@ff8d2000 { 433 compatible = "cdns,qspi-nor"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0xff8d2000 0x100>, 437 <0xff900000 0x100000>; 438 interrupts = <0 3 4>; 439 cdns,fifo-depth = <128>; 440 cdns,fifo-width = <4>; 441 cdns,trigger-address = <0x00000000>; 442 443 status = "disabled"; 444 }; 445 }; 446}; 447