1*0a6e92f2SDaniele Alessandrelli// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2*0a6e92f2SDaniele Alessandrelli/* 3*0a6e92f2SDaniele Alessandrelli * Copyright (C) 2020, Intel Corporation. 4*0a6e92f2SDaniele Alessandrelli * 5*0a6e92f2SDaniele Alessandrelli * Device tree describing Keem Bay SoC. 6*0a6e92f2SDaniele Alessandrelli */ 7*0a6e92f2SDaniele Alessandrelli 8*0a6e92f2SDaniele Alessandrelli#include <dt-bindings/interrupt-controller/arm-gic.h> 9*0a6e92f2SDaniele Alessandrelli 10*0a6e92f2SDaniele Alessandrelli/ { 11*0a6e92f2SDaniele Alessandrelli interrupt-parent = <&gic>; 12*0a6e92f2SDaniele Alessandrelli #address-cells = <2>; 13*0a6e92f2SDaniele Alessandrelli #size-cells = <2>; 14*0a6e92f2SDaniele Alessandrelli 15*0a6e92f2SDaniele Alessandrelli cpus { 16*0a6e92f2SDaniele Alessandrelli #address-cells = <1>; 17*0a6e92f2SDaniele Alessandrelli #size-cells = <0>; 18*0a6e92f2SDaniele Alessandrelli 19*0a6e92f2SDaniele Alessandrelli cpu@0 { 20*0a6e92f2SDaniele Alessandrelli compatible = "arm,cortex-a53"; 21*0a6e92f2SDaniele Alessandrelli device_type = "cpu"; 22*0a6e92f2SDaniele Alessandrelli reg = <0x0>; 23*0a6e92f2SDaniele Alessandrelli enable-method = "psci"; 24*0a6e92f2SDaniele Alessandrelli }; 25*0a6e92f2SDaniele Alessandrelli 26*0a6e92f2SDaniele Alessandrelli cpu@1 { 27*0a6e92f2SDaniele Alessandrelli compatible = "arm,cortex-a53"; 28*0a6e92f2SDaniele Alessandrelli device_type = "cpu"; 29*0a6e92f2SDaniele Alessandrelli reg = <0x1>; 30*0a6e92f2SDaniele Alessandrelli enable-method = "psci"; 31*0a6e92f2SDaniele Alessandrelli }; 32*0a6e92f2SDaniele Alessandrelli 33*0a6e92f2SDaniele Alessandrelli cpu@2 { 34*0a6e92f2SDaniele Alessandrelli compatible = "arm,cortex-a53"; 35*0a6e92f2SDaniele Alessandrelli device_type = "cpu"; 36*0a6e92f2SDaniele Alessandrelli reg = <0x2>; 37*0a6e92f2SDaniele Alessandrelli enable-method = "psci"; 38*0a6e92f2SDaniele Alessandrelli }; 39*0a6e92f2SDaniele Alessandrelli 40*0a6e92f2SDaniele Alessandrelli cpu@3 { 41*0a6e92f2SDaniele Alessandrelli compatible = "arm,cortex-a53"; 42*0a6e92f2SDaniele Alessandrelli device_type = "cpu"; 43*0a6e92f2SDaniele Alessandrelli reg = <0x3>; 44*0a6e92f2SDaniele Alessandrelli enable-method = "psci"; 45*0a6e92f2SDaniele Alessandrelli }; 46*0a6e92f2SDaniele Alessandrelli }; 47*0a6e92f2SDaniele Alessandrelli 48*0a6e92f2SDaniele Alessandrelli psci { 49*0a6e92f2SDaniele Alessandrelli compatible = "arm,psci-0.2"; 50*0a6e92f2SDaniele Alessandrelli method = "smc"; 51*0a6e92f2SDaniele Alessandrelli }; 52*0a6e92f2SDaniele Alessandrelli 53*0a6e92f2SDaniele Alessandrelli gic: interrupt-controller@20500000 { 54*0a6e92f2SDaniele Alessandrelli compatible = "arm,gic-v3"; 55*0a6e92f2SDaniele Alessandrelli interrupt-controller; 56*0a6e92f2SDaniele Alessandrelli #interrupt-cells = <3>; 57*0a6e92f2SDaniele Alessandrelli reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ 58*0a6e92f2SDaniele Alessandrelli <0x0 0x20580000 0x0 0x80000>; /* GICR */ 59*0a6e92f2SDaniele Alessandrelli /* VGIC maintenance interrupt */ 60*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 61*0a6e92f2SDaniele Alessandrelli }; 62*0a6e92f2SDaniele Alessandrelli 63*0a6e92f2SDaniele Alessandrelli timer { 64*0a6e92f2SDaniele Alessandrelli compatible = "arm,armv8-timer"; 65*0a6e92f2SDaniele Alessandrelli /* Secure, non-secure, virtual, and hypervisor */ 66*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 67*0a6e92f2SDaniele Alessandrelli <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 68*0a6e92f2SDaniele Alessandrelli <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 69*0a6e92f2SDaniele Alessandrelli <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 70*0a6e92f2SDaniele Alessandrelli }; 71*0a6e92f2SDaniele Alessandrelli 72*0a6e92f2SDaniele Alessandrelli pmu { 73*0a6e92f2SDaniele Alessandrelli compatible = "arm,armv8-pmuv3"; 74*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; 75*0a6e92f2SDaniele Alessandrelli }; 76*0a6e92f2SDaniele Alessandrelli 77*0a6e92f2SDaniele Alessandrelli soc { 78*0a6e92f2SDaniele Alessandrelli compatible = "simple-bus"; 79*0a6e92f2SDaniele Alessandrelli #address-cells = <2>; 80*0a6e92f2SDaniele Alessandrelli #size-cells = <2>; 81*0a6e92f2SDaniele Alessandrelli ranges; 82*0a6e92f2SDaniele Alessandrelli 83*0a6e92f2SDaniele Alessandrelli uart0: serial@20150000 { 84*0a6e92f2SDaniele Alessandrelli compatible = "snps,dw-apb-uart"; 85*0a6e92f2SDaniele Alessandrelli reg = <0x0 0x20150000 0x0 0x100>; 86*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 87*0a6e92f2SDaniele Alessandrelli clock-frequency = <24000000>; 88*0a6e92f2SDaniele Alessandrelli reg-shift = <2>; 89*0a6e92f2SDaniele Alessandrelli reg-io-width = <4>; 90*0a6e92f2SDaniele Alessandrelli status = "disabled"; 91*0a6e92f2SDaniele Alessandrelli }; 92*0a6e92f2SDaniele Alessandrelli 93*0a6e92f2SDaniele Alessandrelli uart1: serial@20160000 { 94*0a6e92f2SDaniele Alessandrelli compatible = "snps,dw-apb-uart"; 95*0a6e92f2SDaniele Alessandrelli reg = <0x0 0x20160000 0x0 0x100>; 96*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 97*0a6e92f2SDaniele Alessandrelli clock-frequency = <24000000>; 98*0a6e92f2SDaniele Alessandrelli reg-shift = <2>; 99*0a6e92f2SDaniele Alessandrelli reg-io-width = <4>; 100*0a6e92f2SDaniele Alessandrelli status = "disabled"; 101*0a6e92f2SDaniele Alessandrelli }; 102*0a6e92f2SDaniele Alessandrelli 103*0a6e92f2SDaniele Alessandrelli uart2: serial@20170000 { 104*0a6e92f2SDaniele Alessandrelli compatible = "snps,dw-apb-uart"; 105*0a6e92f2SDaniele Alessandrelli reg = <0x0 0x20170000 0x0 0x100>; 106*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 107*0a6e92f2SDaniele Alessandrelli clock-frequency = <24000000>; 108*0a6e92f2SDaniele Alessandrelli reg-shift = <2>; 109*0a6e92f2SDaniele Alessandrelli reg-io-width = <4>; 110*0a6e92f2SDaniele Alessandrelli status = "disabled"; 111*0a6e92f2SDaniele Alessandrelli }; 112*0a6e92f2SDaniele Alessandrelli 113*0a6e92f2SDaniele Alessandrelli uart3: serial@20180000 { 114*0a6e92f2SDaniele Alessandrelli compatible = "snps,dw-apb-uart"; 115*0a6e92f2SDaniele Alessandrelli reg = <0x0 0x20180000 0x0 0x100>; 116*0a6e92f2SDaniele Alessandrelli interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 117*0a6e92f2SDaniele Alessandrelli clock-frequency = <24000000>; 118*0a6e92f2SDaniele Alessandrelli reg-shift = <2>; 119*0a6e92f2SDaniele Alessandrelli reg-io-width = <4>; 120*0a6e92f2SDaniele Alessandrelli status = "disabled"; 121*0a6e92f2SDaniele Alessandrelli }; 122*0a6e92f2SDaniele Alessandrelli }; 123*0a6e92f2SDaniele Alessandrelli}; 124