1// SPDX-License-Identifier: GPL-2.0-only 2/** 3 * dts file for Hisilicon D02 Development Board 4 * 5 * Copyright (C) 2014,2015 HiSilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "hisilicon,hip05-d02"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 cluster2 { 55 core0 { 56 cpu = <&cpu8>; 57 }; 58 core1 { 59 cpu = <&cpu9>; 60 }; 61 core2 { 62 cpu = <&cpu10>; 63 }; 64 core3 { 65 cpu = <&cpu11>; 66 }; 67 }; 68 cluster3 { 69 core0 { 70 cpu = <&cpu12>; 71 }; 72 core1 { 73 cpu = <&cpu13>; 74 }; 75 core2 { 76 cpu = <&cpu14>; 77 }; 78 core3 { 79 cpu = <&cpu15>; 80 }; 81 }; 82 }; 83 84 cpu0: cpu@20000 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a57"; 87 reg = <0x20000>; 88 enable-method = "psci"; 89 next-level-cache = <&cluster0_l2>; 90 }; 91 92 cpu1: cpu@20001 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a57"; 95 reg = <0x20001>; 96 enable-method = "psci"; 97 next-level-cache = <&cluster0_l2>; 98 }; 99 100 cpu2: cpu@20002 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a57"; 103 reg = <0x20002>; 104 enable-method = "psci"; 105 next-level-cache = <&cluster0_l2>; 106 }; 107 108 cpu3: cpu@20003 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a57"; 111 reg = <0x20003>; 112 enable-method = "psci"; 113 next-level-cache = <&cluster0_l2>; 114 }; 115 116 cpu4: cpu@20100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a57"; 119 reg = <0x20100>; 120 enable-method = "psci"; 121 next-level-cache = <&cluster1_l2>; 122 }; 123 124 cpu5: cpu@20101 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a57"; 127 reg = <0x20101>; 128 enable-method = "psci"; 129 next-level-cache = <&cluster1_l2>; 130 }; 131 132 cpu6: cpu@20102 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a57"; 135 reg = <0x20102>; 136 enable-method = "psci"; 137 next-level-cache = <&cluster1_l2>; 138 }; 139 140 cpu7: cpu@20103 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a57"; 143 reg = <0x20103>; 144 enable-method = "psci"; 145 next-level-cache = <&cluster1_l2>; 146 }; 147 148 cpu8: cpu@20200 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a57"; 151 reg = <0x20200>; 152 enable-method = "psci"; 153 next-level-cache = <&cluster2_l2>; 154 }; 155 156 cpu9: cpu@20201 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a57"; 159 reg = <0x20201>; 160 enable-method = "psci"; 161 next-level-cache = <&cluster2_l2>; 162 }; 163 164 cpu10: cpu@20202 { 165 device_type = "cpu"; 166 compatible = "arm,cortex-a57"; 167 reg = <0x20202>; 168 enable-method = "psci"; 169 next-level-cache = <&cluster2_l2>; 170 }; 171 172 cpu11: cpu@20203 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a57"; 175 reg = <0x20203>; 176 enable-method = "psci"; 177 next-level-cache = <&cluster2_l2>; 178 }; 179 180 cpu12: cpu@20300 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a57"; 183 reg = <0x20300>; 184 enable-method = "psci"; 185 next-level-cache = <&cluster3_l2>; 186 }; 187 188 cpu13: cpu@20301 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a57"; 191 reg = <0x20301>; 192 enable-method = "psci"; 193 next-level-cache = <&cluster3_l2>; 194 }; 195 196 cpu14: cpu@20302 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a57"; 199 reg = <0x20302>; 200 enable-method = "psci"; 201 next-level-cache = <&cluster3_l2>; 202 }; 203 204 cpu15: cpu@20303 { 205 device_type = "cpu"; 206 compatible = "arm,cortex-a57"; 207 reg = <0x20303>; 208 enable-method = "psci"; 209 next-level-cache = <&cluster3_l2>; 210 }; 211 212 cluster0_l2: l2-cache0 { 213 compatible = "cache"; 214 cache-level = <2>; 215 }; 216 217 cluster1_l2: l2-cache1 { 218 compatible = "cache"; 219 cache-level = <2>; 220 }; 221 222 cluster2_l2: l2-cache2 { 223 compatible = "cache"; 224 cache-level = <2>; 225 }; 226 227 cluster3_l2: l2-cache3 { 228 compatible = "cache"; 229 cache-level = <2>; 230 }; 231 }; 232 233 gic: interrupt-controller@8d000000 { 234 compatible = "arm,gic-v3"; 235 #interrupt-cells = <3>; 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges; 239 interrupt-controller; 240 #redistributor-regions = <1>; 241 redistributor-stride = <0x0 0x30000>; 242 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 243 <0x0 0x8d100000 0 0x300000>, /* GICR */ 244 <0x0 0xfe000000 0 0x10000>, /* GICC */ 245 <0x0 0xfe010000 0 0x10000>, /* GICH */ 246 <0x0 0xfe020000 0 0x10000>; /* GICV */ 247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 248 249 its_peri: msi-controller@8c000000 { 250 compatible = "arm,gic-v3-its"; 251 msi-controller; 252 #msi-cells = <1>; 253 reg = <0x0 0x8c000000 0x0 0x40000>; 254 }; 255 256 its_m3: msi-controller@a3000000 { 257 compatible = "arm,gic-v3-its"; 258 msi-controller; 259 #msi-cells = <1>; 260 reg = <0x0 0xa3000000 0x0 0x40000>; 261 }; 262 263 its_pcie: msi-controller@b7000000 { 264 compatible = "arm,gic-v3-its"; 265 msi-controller; 266 #msi-cells = <1>; 267 reg = <0x0 0xb7000000 0x0 0x40000>; 268 }; 269 270 its_dsa: msi-controller@c6000000 { 271 compatible = "arm,gic-v3-its"; 272 msi-controller; 273 #msi-cells = <1>; 274 reg = <0x0 0xc6000000 0x0 0x40000>; 275 }; 276 }; 277 278 timer { 279 compatible = "arm,armv8-timer"; 280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 282 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 283 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 pmu { 287 compatible = "arm,cortex-a57-pmu"; 288 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 soc { 292 compatible = "simple-bus"; 293 #address-cells = <2>; 294 #size-cells = <2>; 295 ranges; 296 297 refclk200mhz: refclk200mhz { 298 compatible = "fixed-clock"; 299 #clock-cells = <0>; 300 clock-frequency = <200000000>; 301 }; 302 303 uart0: serial@80300000 { 304 compatible = "snps,dw-apb-uart"; 305 reg = <0x0 0x80300000 0x0 0x10000>; 306 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&refclk200mhz>, <&refclk200mhz>; 308 clock-names = "baudclk", "apb_pclk"; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 status = "disabled"; 312 }; 313 314 uart1: serial@80310000 { 315 compatible = "snps,dw-apb-uart"; 316 reg = <0x0 0x80310000 0x0 0x10000>; 317 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&refclk200mhz>, <&refclk200mhz>; 319 clock-names = "baudclk", "apb_pclk"; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 status = "disabled"; 323 }; 324 325 lbc: local-bus@80380000 { 326 compatible = "hisilicon,hisi-localbus", "simple-bus"; 327 reg = <0x0 0x80380000 0x0 0x10000>; 328 status = "disabled"; 329 }; 330 331 peri_gpio0: gpio@802e0000 { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 compatible = "snps,dw-apb-gpio"; 335 reg = <0x0 0x802e0000 0x0 0x10000>; 336 status = "disabled"; 337 338 porta: gpio-controller@0 { 339 compatible = "snps,dw-apb-gpio-port"; 340 gpio-controller; 341 #gpio-cells = <2>; 342 ngpios = <32>; 343 reg = <0>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 347 }; 348 }; 349 350 peri_gpio1: gpio@802f0000 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 compatible = "snps,dw-apb-gpio"; 354 reg = <0x0 0x802f0000 0x0 0x10000>; 355 status = "disabled"; 356 357 portb: gpio-controller@0 { 358 compatible = "snps,dw-apb-gpio-port"; 359 gpio-controller; 360 #gpio-cells = <2>; 361 ngpios = <32>; 362 reg = <0>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 366 }; 367 }; 368 }; 369}; 370