1/* 2 * dts file for Hisilicon Hi6220 SoC 3 * 4 * Copyright (C) 2015, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi6220-clock.h> 9#include <dt-bindings/pinctrl/hisi.h> 10 11/ { 12 compatible = "hisilicon,hi6220"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 idle-states { 58 entry-method = "psci"; 59 60 CPU_SLEEP: cpu-sleep { 61 compatible = "arm,idle-state"; 62 local-timer-stop; 63 arm,psci-suspend-param = <0x0010000>; 64 entry-latency-us = <700>; 65 exit-latency-us = <250>; 66 min-residency-us = <1000>; 67 }; 68 69 CLUSTER_SLEEP: cluster-sleep { 70 compatible = "arm,idle-state"; 71 local-timer-stop; 72 arm,psci-suspend-param = <0x1010000>; 73 entry-latency-us = <1000>; 74 exit-latency-us = <700>; 75 min-residency-us = <2700>; 76 wakeup-latency-us = <1500>; 77 }; 78 }; 79 80 cpu0: cpu@0 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <0x0 0x0>; 84 enable-method = "psci"; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 }; 87 88 cpu1: cpu@1 { 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 device_type = "cpu"; 91 reg = <0x0 0x1>; 92 enable-method = "psci"; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 94 }; 95 96 cpu2: cpu@2 { 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 device_type = "cpu"; 99 reg = <0x0 0x2>; 100 enable-method = "psci"; 101 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 102 }; 103 104 cpu3: cpu@3 { 105 compatible = "arm,cortex-a53", "arm,armv8"; 106 device_type = "cpu"; 107 reg = <0x0 0x3>; 108 enable-method = "psci"; 109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 110 }; 111 112 cpu4: cpu@100 { 113 compatible = "arm,cortex-a53", "arm,armv8"; 114 device_type = "cpu"; 115 reg = <0x0 0x100>; 116 enable-method = "psci"; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 }; 119 120 cpu5: cpu@101 { 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 device_type = "cpu"; 123 reg = <0x0 0x101>; 124 enable-method = "psci"; 125 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 126 }; 127 128 cpu6: cpu@102 { 129 compatible = "arm,cortex-a53", "arm,armv8"; 130 device_type = "cpu"; 131 reg = <0x0 0x102>; 132 enable-method = "psci"; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 134 }; 135 136 cpu7: cpu@103 { 137 compatible = "arm,cortex-a53", "arm,armv8"; 138 device_type = "cpu"; 139 reg = <0x0 0x103>; 140 enable-method = "psci"; 141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 142 }; 143 }; 144 145 gic: interrupt-controller@f6801000 { 146 compatible = "arm,gic-400"; 147 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 148 <0x0 0xf6802000 0 0x2000>, /* GICC */ 149 <0x0 0xf6804000 0 0x2000>, /* GICH */ 150 <0x0 0xf6806000 0 0x2000>; /* GICV */ 151 #address-cells = <0>; 152 #interrupt-cells = <3>; 153 interrupt-controller; 154 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 155 }; 156 157 timer { 158 compatible = "arm,armv8-timer"; 159 interrupt-parent = <&gic>; 160 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 162 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 164 }; 165 166 soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 ao_ctrl: ao_ctrl@f7800000 { 173 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 174 reg = <0x0 0xf7800000 0x0 0x2000>; 175 #clock-cells = <1>; 176 }; 177 178 sys_ctrl: sys_ctrl@f7030000 { 179 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 180 reg = <0x0 0xf7030000 0x0 0x2000>; 181 #clock-cells = <1>; 182 #reset-cells = <1>; 183 }; 184 185 media_ctrl: media_ctrl@f4410000 { 186 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 187 reg = <0x0 0xf4410000 0x0 0x1000>; 188 #clock-cells = <1>; 189 }; 190 191 pm_ctrl: pm_ctrl@f7032000 { 192 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 193 reg = <0x0 0xf7032000 0x0 0x1000>; 194 #clock-cells = <1>; 195 }; 196 197 uart0: uart@f8015000 { /* console */ 198 compatible = "arm,pl011", "arm,primecell"; 199 reg = <0x0 0xf8015000 0x0 0x1000>; 200 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 202 <&ao_ctrl HI6220_UART0_PCLK>; 203 clock-names = "uartclk", "apb_pclk"; 204 }; 205 206 uart1: uart@f7111000 { 207 compatible = "arm,pl011", "arm,primecell"; 208 reg = <0x0 0xf7111000 0x0 0x1000>; 209 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 211 <&sys_ctrl HI6220_UART1_PCLK>; 212 clock-names = "uartclk", "apb_pclk"; 213 status = "disabled"; 214 }; 215 216 uart2: uart@f7112000 { 217 compatible = "arm,pl011", "arm,primecell"; 218 reg = <0x0 0xf7112000 0x0 0x1000>; 219 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 221 <&sys_ctrl HI6220_UART2_PCLK>; 222 clock-names = "uartclk", "apb_pclk"; 223 status = "disabled"; 224 }; 225 226 uart3: uart@f7113000 { 227 compatible = "arm,pl011", "arm,primecell"; 228 reg = <0x0 0xf7113000 0x0 0x1000>; 229 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 231 <&sys_ctrl HI6220_UART3_PCLK>; 232 clock-names = "uartclk", "apb_pclk"; 233 }; 234 235 uart4: uart@f7114000 { 236 compatible = "arm,pl011", "arm,primecell"; 237 reg = <0x0 0xf7114000 0x0 0x1000>; 238 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 240 <&sys_ctrl HI6220_UART4_PCLK>; 241 clock-names = "uartclk", "apb_pclk"; 242 status = "disabled"; 243 }; 244 245 dual_timer0: timer@f8008000 { 246 compatible = "arm,sp804", "arm,primecell"; 247 reg = <0x0 0xf8008000 0x0 0x1000>; 248 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 251 <&ao_ctrl HI6220_TIMER0_PCLK>, 252 <&ao_ctrl HI6220_TIMER0_PCLK>; 253 clock-names = "timer1", "timer2", "apb_pclk"; 254 }; 255 256 pmx0: pinmux@f7010000 { 257 compatible = "pinctrl-single"; 258 reg = <0x0 0xf7010000 0x0 0x27c>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 #gpio-range-cells = <3>; 262 pinctrl-single,register-width = <32>; 263 pinctrl-single,function-mask = <7>; 264 pinctrl-single,gpio-range = < 265 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 266 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 267 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 268 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 269 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 270 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 271 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 272 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 273 &range 0 1 MUX_M1 /* gpio 10: [0] */ 274 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 275 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 276 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 277 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 278 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 279 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 280 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 281 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 282 &range 122 1 MUX_M1 /* gpio 15: [6] */ 283 &range 126 1 MUX_M1 /* gpio 15: [7] */ 284 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 285 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 286 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 287 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 288 >; 289 range: gpio-range { 290 #pinctrl-single,gpio-range-cells = <3>; 291 }; 292 }; 293 294 pmx1: pinmux@f7010800 { 295 compatible = "pinconf-single"; 296 reg = <0x0 0xf7010800 0x0 0x28c>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 pinctrl-single,register-width = <32>; 300 }; 301 302 pmx2: pinmux@f8001800 { 303 compatible = "pinconf-single"; 304 reg = <0x0 0xf8001800 0x0 0x78>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 pinctrl-single,register-width = <32>; 308 }; 309 310 gpio0: gpio@f8011000 { 311 compatible = "arm,pl061", "arm,primecell"; 312 reg = <0x0 0xf8011000 0x0 0x1000>; 313 interrupts = <0 52 0x4>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 clocks = <&ao_ctrl 2>; 319 clock-names = "apb_pclk"; 320 }; 321 322 gpio1: gpio@f8012000 { 323 compatible = "arm,pl061", "arm,primecell"; 324 reg = <0x0 0xf8012000 0x0 0x1000>; 325 interrupts = <0 53 0x4>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 clocks = <&ao_ctrl 2>; 331 clock-names = "apb_pclk"; 332 }; 333 334 gpio2: gpio@f8013000 { 335 compatible = "arm,pl061", "arm,primecell"; 336 reg = <0x0 0xf8013000 0x0 0x1000>; 337 interrupts = <0 54 0x4>; 338 gpio-controller; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 clocks = <&ao_ctrl 2>; 343 clock-names = "apb_pclk"; 344 }; 345 346 gpio3: gpio@f8014000 { 347 compatible = "arm,pl061", "arm,primecell"; 348 reg = <0x0 0xf8014000 0x0 0x1000>; 349 interrupts = <0 55 0x4>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 gpio-ranges = <&pmx0 0 80 8>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 clocks = <&ao_ctrl 2>; 356 clock-names = "apb_pclk"; 357 }; 358 359 gpio4: gpio@f7020000 { 360 compatible = "arm,pl061", "arm,primecell"; 361 reg = <0x0 0xf7020000 0x0 0x1000>; 362 interrupts = <0 56 0x4>; 363 gpio-controller; 364 #gpio-cells = <2>; 365 gpio-ranges = <&pmx0 0 88 8>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 clocks = <&ao_ctrl 2>; 369 clock-names = "apb_pclk"; 370 }; 371 372 gpio5: gpio@f7021000 { 373 compatible = "arm,pl061", "arm,primecell"; 374 reg = <0x0 0xf7021000 0x0 0x1000>; 375 interrupts = <0 57 0x4>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 gpio-ranges = <&pmx0 0 96 8>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 clocks = <&ao_ctrl 2>; 382 clock-names = "apb_pclk"; 383 }; 384 385 gpio6: gpio@f7022000 { 386 compatible = "arm,pl061", "arm,primecell"; 387 reg = <0x0 0xf7022000 0x0 0x1000>; 388 interrupts = <0 58 0x4>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 gpio-ranges = <&pmx0 0 104 8>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 clocks = <&ao_ctrl 2>; 395 clock-names = "apb_pclk"; 396 }; 397 398 gpio7: gpio@f7023000 { 399 compatible = "arm,pl061", "arm,primecell"; 400 reg = <0x0 0xf7023000 0x0 0x1000>; 401 interrupts = <0 59 0x4>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 gpio-ranges = <&pmx0 0 112 8>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 clocks = <&ao_ctrl 2>; 408 clock-names = "apb_pclk"; 409 }; 410 411 gpio8: gpio@f7024000 { 412 compatible = "arm,pl061", "arm,primecell"; 413 reg = <0x0 0xf7024000 0x0 0x1000>; 414 interrupts = <0 60 0x4>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 clocks = <&ao_ctrl 2>; 421 clock-names = "apb_pclk"; 422 }; 423 424 gpio9: gpio@f7025000 { 425 compatible = "arm,pl061", "arm,primecell"; 426 reg = <0x0 0xf7025000 0x0 0x1000>; 427 interrupts = <0 61 0x4>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 gpio-ranges = <&pmx0 0 8 8>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 clocks = <&ao_ctrl 2>; 434 clock-names = "apb_pclk"; 435 }; 436 437 gpio10: gpio@f7026000 { 438 compatible = "arm,pl061", "arm,primecell"; 439 reg = <0x0 0xf7026000 0x0 0x1000>; 440 interrupts = <0 62 0x4>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 clocks = <&ao_ctrl 2>; 447 clock-names = "apb_pclk"; 448 }; 449 450 gpio11: gpio@f7027000 { 451 compatible = "arm,pl061", "arm,primecell"; 452 reg = <0x0 0xf7027000 0x0 0x1000>; 453 interrupts = <0 63 0x4>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 clocks = <&ao_ctrl 2>; 460 clock-names = "apb_pclk"; 461 }; 462 463 gpio12: gpio@f7028000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0x0 0xf7028000 0x0 0x1000>; 466 interrupts = <0 64 0x4>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 clocks = <&ao_ctrl 2>; 473 clock-names = "apb_pclk"; 474 }; 475 476 gpio13: gpio@f7029000 { 477 compatible = "arm,pl061", "arm,primecell"; 478 reg = <0x0 0xf7029000 0x0 0x1000>; 479 interrupts = <0 65 0x4>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 gpio-ranges = <&pmx0 0 48 8>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 clocks = <&ao_ctrl 2>; 486 clock-names = "apb_pclk"; 487 }; 488 489 gpio14: gpio@f702a000 { 490 compatible = "arm,pl061", "arm,primecell"; 491 reg = <0x0 0xf702a000 0x0 0x1000>; 492 interrupts = <0 66 0x4>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 gpio-ranges = <&pmx0 0 56 8>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 clocks = <&ao_ctrl 2>; 499 clock-names = "apb_pclk"; 500 }; 501 502 gpio15: gpio@f702b000 { 503 compatible = "arm,pl061", "arm,primecell"; 504 reg = <0x0 0xf702b000 0x0 0x1000>; 505 interrupts = <0 67 0x4>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 gpio-ranges = < 509 &pmx0 0 74 6 510 &pmx0 6 122 1 511 &pmx0 7 126 1 512 >; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 clocks = <&ao_ctrl 2>; 516 clock-names = "apb_pclk"; 517 }; 518 519 gpio16: gpio@f702c000 { 520 compatible = "arm,pl061", "arm,primecell"; 521 reg = <0x0 0xf702c000 0x0 0x1000>; 522 interrupts = <0 68 0x4>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 gpio-ranges = <&pmx0 0 127 8>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 clocks = <&ao_ctrl 2>; 529 clock-names = "apb_pclk"; 530 }; 531 532 gpio17: gpio@f702d000 { 533 compatible = "arm,pl061", "arm,primecell"; 534 reg = <0x0 0xf702d000 0x0 0x1000>; 535 interrupts = <0 69 0x4>; 536 gpio-controller; 537 #gpio-cells = <2>; 538 gpio-ranges = <&pmx0 0 135 8>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 clocks = <&ao_ctrl 2>; 542 clock-names = "apb_pclk"; 543 }; 544 545 gpio18: gpio@f702e000 { 546 compatible = "arm,pl061", "arm,primecell"; 547 reg = <0x0 0xf702e000 0x0 0x1000>; 548 interrupts = <0 70 0x4>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 gpio-ranges = <&pmx0 0 143 8>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 clocks = <&ao_ctrl 2>; 555 clock-names = "apb_pclk"; 556 }; 557 558 gpio19: gpio@f702f000 { 559 compatible = "arm,pl061", "arm,primecell"; 560 reg = <0x0 0xf702f000 0x0 0x1000>; 561 interrupts = <0 71 0x4>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 gpio-ranges = <&pmx0 0 151 8>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 clocks = <&ao_ctrl 2>; 568 clock-names = "apb_pclk"; 569 }; 570 571 spi0: spi@f7106000 { 572 compatible = "arm,pl022", "arm,primecell"; 573 reg = <0x0 0xf7106000 0x0 0x1000>; 574 interrupts = <0 50 4>; 575 bus-id = <0>; 576 enable-dma = <0>; 577 clocks = <&sys_ctrl HI6220_SPI_CLK>; 578 clock-names = "apb_pclk"; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 581 num-cs = <1>; 582 cs-gpios = <&gpio6 2 0>; 583 status = "disabled"; 584 }; 585 586 i2c0: i2c@f7100000 { 587 compatible = "snps,designware-i2c"; 588 reg = <0x0 0xf7100000 0x0 0x1000>; 589 interrupts = <0 44 4>; 590 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 591 i2c-sda-hold-time-ns = <300>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 594 status = "disabled"; 595 }; 596 597 i2c1: i2c@f7101000 { 598 compatible = "snps,designware-i2c"; 599 reg = <0x0 0xf7101000 0x0 0x1000>; 600 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 601 interrupts = <0 45 4>; 602 i2c-sda-hold-time-ns = <300>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 605 status = "disabled"; 606 }; 607 608 i2c2: i2c@f7102000 { 609 compatible = "snps,designware-i2c"; 610 reg = <0x0 0xf7102000 0x0 0x1000>; 611 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 612 interrupts = <0 46 4>; 613 i2c-sda-hold-time-ns = <300>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 616 status = "disabled"; 617 }; 618 619 fixed_5v_hub: regulator@0 { 620 compatible = "regulator-fixed"; 621 regulator-name = "fixed_5v_hub"; 622 regulator-min-microvolt = <5000000>; 623 regulator-max-microvolt = <5000000>; 624 regulator-boot-on; 625 gpio = <&gpio0 7 0>; 626 regulator-always-on; 627 }; 628 629 usb_phy: usbphy { 630 compatible = "hisilicon,hi6220-usb-phy"; 631 #phy-cells = <0>; 632 phy-supply = <&fixed_5v_hub>; 633 hisilicon,peripheral-syscon = <&sys_ctrl>; 634 }; 635 636 usb: usb@f72c0000 { 637 compatible = "hisilicon,hi6220-usb"; 638 reg = <0x0 0xf72c0000 0x0 0x40000>; 639 phys = <&usb_phy>; 640 phy-names = "usb2-phy"; 641 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 642 clock-names = "otg"; 643 dr_mode = "otg"; 644 g-use-dma; 645 g-rx-fifo-size = <512>; 646 g-np-tx-fifo-size = <128>; 647 g-tx-fifo-size = <128 128 128 128 128 128>; 648 interrupts = <0 77 0x4>; 649 }; 650 651 mailbox: mailbox@f7510000 { 652 compatible = "hisilicon,hi6220-mbox"; 653 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 654 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 655 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 656 #mbox-cells = <3>; 657 }; 658 }; 659}; 660