1/* 2 * dts file for Hisilicon Hi3660 SoC 3 * 4 * Copyright (C) 2016, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "hisilicon,hi3660"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 psci { 16 compatible = "arm,psci-0.2"; 17 method = "smc"; 18 }; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 cluster1 { 40 core0 { 41 cpu = <&cpu4>; 42 }; 43 core1 { 44 cpu = <&cpu5>; 45 }; 46 core2 { 47 cpu = <&cpu6>; 48 }; 49 core3 { 50 cpu = <&cpu7>; 51 }; 52 }; 53 }; 54 55 cpu0: cpu@0 { 56 compatible = "arm,cortex-a53", "arm,armv8"; 57 device_type = "cpu"; 58 reg = <0x0 0x0>; 59 enable-method = "psci"; 60 }; 61 62 cpu1: cpu@1 { 63 compatible = "arm,cortex-a53", "arm,armv8"; 64 device_type = "cpu"; 65 reg = <0x0 0x1>; 66 enable-method = "psci"; 67 }; 68 69 cpu2: cpu@2 { 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 device_type = "cpu"; 72 reg = <0x0 0x2>; 73 enable-method = "psci"; 74 }; 75 76 cpu3: cpu@3 { 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 device_type = "cpu"; 79 reg = <0x0 0x3>; 80 enable-method = "psci"; 81 }; 82 83 cpu4: cpu@100 { 84 compatible = "arm,cortex-a73", "arm,armv8"; 85 device_type = "cpu"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 }; 89 90 cpu5: cpu@101 { 91 compatible = "arm,cortex-a73", "arm,armv8"; 92 device_type = "cpu"; 93 reg = <0x0 0x101>; 94 enable-method = "psci"; 95 }; 96 97 cpu6: cpu@102 { 98 compatible = "arm,cortex-a73", "arm,armv8"; 99 device_type = "cpu"; 100 reg = <0x0 0x102>; 101 enable-method = "psci"; 102 }; 103 104 cpu7: cpu@103 { 105 compatible = "arm,cortex-a73", "arm,armv8"; 106 device_type = "cpu"; 107 reg = <0x0 0x103>; 108 enable-method = "psci"; 109 }; 110 }; 111 112 gic: interrupt-controller@e82b0000 { 113 compatible = "arm,gic-400"; 114 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 115 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 116 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 117 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 118 #address-cells = <0>; 119 #interrupt-cells = <3>; 120 interrupt-controller; 121 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 122 IRQ_TYPE_LEVEL_HIGH)>; 123 }; 124 125 timer { 126 compatible = "arm,armv8-timer"; 127 interrupt-parent = <&gic>; 128 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 129 IRQ_TYPE_LEVEL_LOW)>, 130 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 131 IRQ_TYPE_LEVEL_LOW)>, 132 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 133 IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 135 IRQ_TYPE_LEVEL_LOW)>; 136 }; 137 138 soc { 139 compatible = "simple-bus"; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 fixed_uart5: fixed_19_2M { 145 compatible = "fixed-clock"; 146 #clock-cells = <0>; 147 clock-frequency = <19200000>; 148 clock-output-names = "fixed:uart5"; 149 }; 150 151 uart5: uart@fdf05000 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x0 0xfdf05000 0x0 0x1000>; 154 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&fixed_uart5 &fixed_uart5>; 156 clock-names = "uartclk", "apb_pclk"; 157 status = "disabled"; 158 }; 159 }; 160}; 161