xref: /linux/arch/arm64/boot/dts/freescale/tqma8xx.dtsi (revision 7255fcc80d4b525cc10cfaaf7f485830d4ed2000) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
2/*
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8/ {
9	memory@80000000 {
10		device_type = "memory";
11		reg = <0x00000000 0x80000000 0 0x40000000>;
12	};
13
14	reg_1v8: regulator-1v8 {
15		compatible = "regulator-fixed";
16		regulator-name = "V_1V8";
17		regulator-min-microvolt = <1800000>;
18		regulator-max-microvolt = <1800000>;
19	};
20
21	reg_3v3: regulator-3v3 {
22		compatible = "regulator-fixed";
23		regulator-name = "V_3V3";
24		regulator-min-microvolt = <3300000>;
25		regulator-max-microvolt = <3300000>;
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		/*
34		 * global autoconfigured region for contiguous allocations
35		 * must not exceed memory size and region
36		 */
37		linux,cma {
38			compatible = "shared-dma-pool";
39			reusable;
40			size = <0 0x20000000>;
41			alloc-ranges = <0 0x96000000 0 0x30000000>;
42			linux,cma-default;
43		};
44	};
45};
46
47/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
48&cpu_alert0 {
49	temperature = <95000>;
50};
51
52&cpu_crit0 {
53	temperature = <100000>;
54};
55/* end of temperature grade adjustments */
56
57&flexspi0 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_flexspi0>;
60	status = "okay";
61
62	flash0: flash@0 {
63		reg = <0>;
64		#address-cells = <1>;
65		#size-cells = <1>;
66		compatible = "jedec,spi-nor";
67		spi-max-frequency = <66000000>;
68		spi-tx-bus-width = <1>;
69		spi-rx-bus-width = <4>;
70	};
71};
72
73/* TODO GPU */
74
75&i2c1 {
76	#address-cells = <1>;
77	#size-cells = <0>;
78	clock-frequency = <100000>;
79	pinctrl-names = "default", "gpio";
80	pinctrl-0 = <&pinctrl_lpi2c1>;
81	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
82	scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
83	sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
84	status = "okay";
85
86	se97: temperature-sensor@1b {
87		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
88		reg = <0x1b>;
89	};
90
91	pcf85063: rtc@51 {
92		compatible = "nxp,pcf85063a";
93		reg = <0x51>;
94		quartz-load-femtofarads = <7000>;
95	};
96
97	at24c02: eeprom@53 {
98		compatible = "nxp,se97b", "atmel,24c02";
99		reg = <0x53>;
100		pagesize = <16>;
101		read-only;
102		vcc-supply = <&reg_3v3>;
103	};
104
105	m24c64: eeprom@57 {
106		compatible = "atmel,24c64";
107		reg = <0x57>;
108		pagesize = <32>;
109		vcc-supply = <&reg_3v3>;
110	};
111};
112
113&mu_m0 {
114	status = "okay";
115};
116
117&mu1_m0 {
118	status = "okay";
119};
120
121&thermal_zones {
122	pmic_thermal: pmic-thermal {
123		polling-delay-passive = <250>;
124		polling-delay = <2000>;
125		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
126
127		trips {
128			pmic_alert0: trip0 {
129				temperature = <110000>;
130				hysteresis = <2000>;
131				type = "passive";
132			};
133
134			pmic_crit0: trip1 {
135				temperature = <125000>;
136				hysteresis = <2000>;
137				type = "critical";
138			};
139		};
140
141		cooling-maps {
142			map0 {
143				trip = <&pmic_alert0>;
144				cooling-device =
145					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
146					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
147					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
148					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149			};
150		};
151	};
152};
153
154&usdhc1 {
155	pinctrl-names = "default", "state_100mhz", "state_200mhz";
156	pinctrl-0 = <&pinctrl_usdhc1>;
157	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
158	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
159	vqmmc-supply = <&reg_1v8>;
160	vmmc-supply = <&reg_3v3>;
161	bus-width = <8>;
162	non-removable;
163	no-sdio;
164	no-sd;
165	status = "okay";
166};
167
168&vpu {
169	compatible = "nxp,imx8qxp-vpu";
170	status = "okay";
171};
172
173&vpu_core0 {
174	memory-region = <&decoder_boot>, <&decoder_rpc>;
175	status = "okay";
176};
177
178&vpu_core1 {
179	memory-region = <&encoder_boot>, <&encoder_rpc>;
180	status = "okay";
181};
182
183&iomuxc {
184	pinctrl_flexspi0: flexspi0grp {
185		fsl,pins = <
186			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004d
187			IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004d
188			IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004d
189			IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004d
190			IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS	0x0600004d
191			IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004d
192			IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004d
193			IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004d
194			IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004d
195			IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004d
196			IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004d
197			IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004d
198			IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS	0x0600004d
199			IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004d
200			IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004d
201		>;
202	};
203
204	pinctrl_lpi2c1: lpi2c1grp {
205		fsl,pins = <
206			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
207			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
208		>;
209	};
210
211	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
212		fsl,pins = <
213			IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27	0x06000021
214			IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28	0x06000021
215		>;
216	};
217
218	pinctrl_usdhc1: usdhc1grp {
219		fsl,pins = <
220			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
221			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
222			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
223			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
224			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
225			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
226			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
227			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
228			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
229			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
230			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
231		>;
232	};
233
234	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
235		fsl,pins = <
236			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
237			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
238			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
239			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
240			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
241			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
242			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
243			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
244			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
245			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
246			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
247		>;
248	};
249
250	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
251		fsl,pins = <
252			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
253			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
254			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
255			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
256			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
257			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
258			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
259			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
260			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
261			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
262			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
263		>;
264	};
265};
266