1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2016-2018 NXP 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/memreserve/ 0x80000000 0x00010000; 10 11/ { 12 compatible = "fsl,s32v234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 serial0 = &uart0; 19 serial1 = &uart1; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53"; 29 reg = <0x0 0x0>; 30 enable-method = "spin-table"; 31 cpu-release-addr = <0x0 0x80000000>; 32 next-level-cache = <&cluster0_l2_cache>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0 0x1>; 39 enable-method = "spin-table"; 40 cpu-release-addr = <0x0 0x80000000>; 41 next-level-cache = <&cluster0_l2_cache>; 42 }; 43 44 cpu2: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x100>; 48 enable-method = "spin-table"; 49 cpu-release-addr = <0x0 0x80000000>; 50 next-level-cache = <&cluster1_l2_cache>; 51 }; 52 53 cpu3: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x0 0x101>; 57 enable-method = "spin-table"; 58 cpu-release-addr = <0x0 0x80000000>; 59 next-level-cache = <&cluster1_l2_cache>; 60 }; 61 62 cluster0_l2_cache: l2-cache0 { 63 compatible = "cache"; 64 cache-level = <2>; 65 }; 66 67 cluster1_l2_cache: l2-cache1 { 68 compatible = "cache"; 69 cache-level = <2>; 70 }; 71 }; 72 73 timer { 74 compatible = "arm,armv8-timer"; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 76 IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 78 IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 80 IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 82 IRQ_TYPE_LEVEL_LOW)>; 83 /* clock-frequency might be modified by u-boot, depending on the 84 * chip version. 85 */ 86 clock-frequency = <10000000>; 87 }; 88 89 gic: interrupt-controller@7d001000 { 90 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 91 #interrupt-cells = <3>; 92 #address-cells = <0>; 93 interrupt-controller; 94 reg = <0 0x7d001000 0 0x1000>, 95 <0 0x7d002000 0 0x2000>, 96 <0 0x7d004000 0 0x2000>, 97 <0 0x7d006000 0 0x2000>; 98 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 99 IRQ_TYPE_LEVEL_HIGH)>; 100 }; 101 102 soc { 103 #address-cells = <2>; 104 #size-cells = <2>; 105 compatible = "simple-bus"; 106 interrupt-parent = <&gic>; 107 ranges; 108 109 aips0: bus@40000000 { 110 compatible = "simple-bus"; 111 #address-cells = <2>; 112 #size-cells = <2>; 113 interrupt-parent = <&gic>; 114 reg = <0x0 0x40000000 0x0 0x7d000>; 115 ranges; 116 117 uart0: serial@40053000 { 118 compatible = "fsl,s32v234-linflexuart"; 119 reg = <0x0 0x40053000 0x0 0x1000>; 120 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; 121 status = "disabled"; 122 }; 123 }; 124 125 aips1: bus@40080000 { 126 compatible = "simple-bus"; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 interrupt-parent = <&gic>; 130 reg = <0x0 0x40080000 0x0 0x70000>; 131 ranges; 132 133 uart1: serial@400bc000 { 134 compatible = "fsl,s32v234-linflexuart"; 135 reg = <0x0 0x400bc000 0x0 0x1000>; 136 interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>; 137 status = "disabled"; 138 }; 139 }; 140 }; 141}; 142