1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright 2021-2024 NXP 4 * 5 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> 6 * Ciprian Costea <ciprianmarian.costea@nxp.com> 7 * Andra-Teodora Ilie <andra.ilie@nxp.com> 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "nxp,s32g3"; 14 interrupt-parent = <&gic>; 15 #address-cells = <0x02>; 16 #size-cells = <0x02>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 50 core2 { 51 cpu = <&cpu6>; 52 }; 53 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0>; 64 enable-method = "psci"; 65 clocks = <&dfs 0>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x1>; 72 enable-method = "psci"; 73 clocks = <&dfs 0>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 clocks = <&dfs 0>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x3>; 88 enable-method = "psci"; 89 clocks = <&dfs 0>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 clocks = <&dfs 0>; 98 }; 99 100 cpu5: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x101>; 104 enable-method = "psci"; 105 clocks = <&dfs 0>; 106 }; 107 108 cpu6: cpu@102 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 enable-method = "psci"; 113 clocks = <&dfs 0>; 114 }; 115 116 cpu7: cpu@103 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x103>; 120 enable-method = "psci"; 121 clocks = <&dfs 0>; 122 }; 123 }; 124 125 firmware { 126 scmi: scmi { 127 compatible = "arm,scmi-smc"; 128 shmem = <&scmi_shmem>; 129 arm,smc-id = <0xc20000fe>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 dfs: protocol@13 { 134 reg = <0x13>; 135 #clock-cells = <1>; 136 }; 137 138 clks: protocol@14 { 139 reg = <0x14>; 140 #clock-cells = <1>; 141 }; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 }; 149 150 151 pmu { 152 compatible = "arm,cortex-a53-pmu"; 153 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 reserved-memory { 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 scmi_shmem: shm@d0000000 { 162 compatible = "arm,scmi-shmem"; 163 reg = <0x0 0xd0000000 0x0 0x80>; 164 no-map; 165 }; 166 }; 167 168 soc@0 { 169 compatible = "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0 0 0 0x80000000>; 173 174 rtc0: rtc@40060000 { 175 compatible = "nxp,s32g3-rtc", 176 "nxp,s32g2-rtc"; 177 reg = <0x40060000 0x1000>; 178 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&clks 54>, <&clks 55>; 180 clock-names = "ipg", "source0"; 181 }; 182 183 pinctrl: pinctrl@4009c240 { 184 compatible = "nxp,s32g2-siul2-pinctrl"; 185 /* MSCR0-MSCR101 registers on siul2_0 */ 186 reg = <0x4009c240 0x198>, 187 /* MSCR112-MSCR122 registers on siul2_1 */ 188 <0x44010400 0x2c>, 189 /* MSCR144-MSCR190 registers on siul2_1 */ 190 <0x44010480 0xbc>, 191 /* IMCR0-IMCR83 registers on siul2_0 */ 192 <0x4009ca40 0x150>, 193 /* IMCR119-IMCR397 registers on siul2_1 */ 194 <0x44010c1c 0x45c>, 195 /* IMCR430-IMCR495 registers on siul2_1 */ 196 <0x440110f8 0x108>; 197 198 jtag_pins: jtag-pins { 199 jtag-grp0 { 200 pinmux = <0x0>; 201 input-enable; 202 bias-pull-up; 203 slew-rate = <166>; 204 }; 205 206 jtag-grp1 { 207 pinmux = <0x11>; 208 slew-rate = <166>; 209 }; 210 211 jtag-grp2 { 212 pinmux = <0x40>; 213 input-enable; 214 bias-pull-down; 215 slew-rate = <166>; 216 }; 217 218 jtag-grp3 { 219 pinmux = <0x23c0>, 220 <0x23d0>, 221 <0x2320>; 222 }; 223 224 jtag-grp4 { 225 pinmux = <0x51>; 226 input-enable; 227 bias-pull-up; 228 slew-rate = <166>; 229 }; 230 }; 231 232 pinctrl_usdhc0: usdhc0grp-pins { 233 usdhc0-grp0 { 234 pinmux = <0x2e1>, 235 <0x381>; 236 output-enable; 237 bias-pull-down; 238 slew-rate = <150>; 239 }; 240 241 usdhc0-grp1 { 242 pinmux = <0x2f1>, 243 <0x301>, 244 <0x311>, 245 <0x321>, 246 <0x331>, 247 <0x341>, 248 <0x351>, 249 <0x361>, 250 <0x371>; 251 output-enable; 252 input-enable; 253 bias-pull-up; 254 slew-rate = <150>; 255 }; 256 257 usdhc0-grp2 { 258 pinmux = <0x391>; 259 output-enable; 260 slew-rate = <150>; 261 }; 262 263 usdhc0-grp3 { 264 pinmux = <0x3a0>; 265 input-enable; 266 slew-rate = <150>; 267 }; 268 269 usdhc0-grp4 { 270 pinmux = <0x2032>, 271 <0x2042>, 272 <0x2052>, 273 <0x2062>, 274 <0x2072>, 275 <0x2082>, 276 <0x2092>, 277 <0x20a2>, 278 <0x20b2>, 279 <0x20c2>; 280 }; 281 }; 282 283 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 284 usdhc0-100mhz-grp0 { 285 pinmux = <0x2e1>, 286 <0x381>; 287 output-enable; 288 bias-pull-down; 289 slew-rate = <150>; 290 }; 291 292 usdhc0-100mhz-grp1 { 293 pinmux = <0x2f1>, 294 <0x301>, 295 <0x311>, 296 <0x321>, 297 <0x331>, 298 <0x341>, 299 <0x351>, 300 <0x361>, 301 <0x371>; 302 output-enable; 303 input-enable; 304 bias-pull-up; 305 slew-rate = <150>; 306 }; 307 308 usdhc0-100mhz-grp2 { 309 pinmux = <0x391>; 310 output-enable; 311 slew-rate = <150>; 312 }; 313 314 usdhc0-100mhz-grp3 { 315 pinmux = <0x3a0>; 316 input-enable; 317 slew-rate = <150>; 318 }; 319 320 usdhc0-100mhz-grp4 { 321 pinmux = <0x2032>, 322 <0x2042>, 323 <0x2052>, 324 <0x2062>, 325 <0x2072>, 326 <0x2082>, 327 <0x2092>, 328 <0x20a2>, 329 <0x20b2>, 330 <0x20c2>; 331 }; 332 }; 333 334 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 335 usdhc0-200mhz-grp0 { 336 pinmux = <0x2e1>, 337 <0x381>; 338 output-enable; 339 bias-pull-down; 340 slew-rate = <208>; 341 }; 342 343 usdhc0-200mhz-grp1 { 344 pinmux = <0x2f1>, 345 <0x301>, 346 <0x311>, 347 <0x321>, 348 <0x331>, 349 <0x341>, 350 <0x351>, 351 <0x361>, 352 <0x371>; 353 output-enable; 354 input-enable; 355 bias-pull-up; 356 slew-rate = <208>; 357 }; 358 359 usdhc0-200mhz-grp2 { 360 pinmux = <0x391>; 361 output-enable; 362 slew-rate = <208>; 363 }; 364 365 usdhc0-200mhz-grp3 { 366 pinmux = <0x3a0>; 367 input-enable; 368 slew-rate = <208>; 369 }; 370 371 usdhc0-200mhz-grp4 { 372 pinmux = <0x2032>, 373 <0x2042>, 374 <0x2052>, 375 <0x2062>, 376 <0x2072>, 377 <0x2082>, 378 <0x2092>, 379 <0x20a2>, 380 <0x20b2>, 381 <0x20c2>; 382 }; 383 }; 384 }; 385 386 edma0: dma-controller@40144000 { 387 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 388 reg = <0x40144000 0x24000>, 389 <0x4012c000 0x3000>, 390 <0x40130000 0x3000>; 391 #dma-cells = <2>; 392 dma-channels = <32>; 393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 396 interrupt-names = "tx-0-15", 397 "tx-16-31", 398 "err"; 399 clocks = <&clks 63>, <&clks 64>; 400 clock-names = "dmamux0", "dmamux1"; 401 }; 402 403 can0: can@401b4000 { 404 compatible = "nxp,s32g3-flexcan", 405 "nxp,s32g2-flexcan"; 406 reg = <0x401b4000 0xa000>; 407 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "mb-0", "state", "berr", "mb-1"; 412 clocks = <&clks 9>, <&clks 11>; 413 clock-names = "ipg", "per"; 414 status = "disabled"; 415 }; 416 417 can1: can@401be000 { 418 compatible = "nxp,s32g3-flexcan", 419 "nxp,s32g2-flexcan"; 420 reg = <0x401be000 0xa000>; 421 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "mb-0", "state", "berr", "mb-1"; 426 clocks = <&clks 9>, <&clks 11>; 427 clock-names = "ipg", "per"; 428 status = "disabled"; 429 }; 430 431 uart0: serial@401c8000 { 432 compatible = "nxp,s32g3-linflexuart", 433 "fsl,s32v234-linflexuart"; 434 reg = <0x401c8000 0x3000>; 435 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 436 status = "disabled"; 437 }; 438 439 uart1: serial@401cc000 { 440 compatible = "nxp,s32g3-linflexuart", 441 "fsl,s32v234-linflexuart"; 442 reg = <0x401cc000 0x3000>; 443 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 444 status = "disabled"; 445 }; 446 447 usbmisc: usbmisc@44064200 { 448 #index-cells = <1>; 449 compatible = "nxp,s32g3-usbmisc"; 450 reg = <0x44064200 0x200>; 451 }; 452 453 usbotg: usb@44064000 { 454 compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; 455 reg = <0x44064000 0x200>; 456 interrupt-parent = <&gic>; 457 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ 458 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ 459 clocks = <&clks 94>, <&clks 95>; 460 fsl,usbmisc = <&usbmisc 0>; 461 ahb-burst-config = <0x3>; 462 tx-burst-size-dword = <0x10>; 463 rx-burst-size-dword = <0x10>; 464 phy_type = "ulpi"; 465 dr_mode = "host"; 466 maximum-speed = "high-speed"; 467 status = "disabled"; 468 }; 469 470 spi0: spi@401d4000 { 471 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 472 reg = <0x401d4000 0x1000>; 473 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clks 26>; 475 clock-names = "dspi"; 476 spi-num-chipselects = <8>; 477 bus-num = <0>; 478 dmas = <&edma0 0 7>, <&edma0 0 8>; 479 dma-names = "tx", "rx"; 480 status = "disabled"; 481 }; 482 483 spi1: spi@401d8000 { 484 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 485 reg = <0x401d8000 0x1000>; 486 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&clks 26>; 488 clock-names = "dspi"; 489 spi-num-chipselects = <5>; 490 bus-num = <1>; 491 dmas = <&edma0 0 10>, <&edma0 0 11>; 492 dma-names = "tx", "rx"; 493 status = "disabled"; 494 }; 495 496 spi2: spi@401dc000 { 497 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 498 reg = <0x401dc000 0x1000>; 499 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clks 26>; 501 clock-names = "dspi"; 502 spi-num-chipselects = <5>; 503 bus-num = <2>; 504 dmas = <&edma0 0 13>, <&edma0 0 14>; 505 dma-names = "tx", "rx"; 506 status = "disabled"; 507 }; 508 509 i2c0: i2c@401e4000 { 510 compatible = "nxp,s32g3-i2c", 511 "nxp,s32g2-i2c"; 512 reg = <0x401e4000 0x1000>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clks 40>; 517 clock-names = "ipg"; 518 status = "disabled"; 519 }; 520 521 i2c1: i2c@401e8000 { 522 compatible = "nxp,s32g3-i2c", 523 "nxp,s32g2-i2c"; 524 reg = <0x401e8000 0x1000>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clks 40>; 529 clock-names = "ipg"; 530 status = "disabled"; 531 }; 532 533 i2c2: i2c@401ec000 { 534 compatible = "nxp,s32g3-i2c", 535 "nxp,s32g2-i2c"; 536 reg = <0x401ec000 0x1000>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clks 40>; 541 clock-names = "ipg"; 542 status = "disabled"; 543 }; 544 545 edma1: dma-controller@40244000 { 546 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 547 reg = <0x40244000 0x24000>, 548 <0x4022c000 0x3000>, 549 <0x40230000 0x3000>; 550 #dma-cells = <2>; 551 dma-channels = <32>; 552 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 555 interrupt-names = "tx-0-15", 556 "tx-16-31", 557 "err"; 558 clocks = <&clks 63>, <&clks 64>; 559 clock-names = "dmamux0", "dmamux1"; 560 }; 561 562 can2: can@402a8000 { 563 compatible = "nxp,s32g3-flexcan", 564 "nxp,s32g2-flexcan"; 565 reg = <0x402a8000 0xa000>; 566 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "mb-0", "state", "berr", "mb-1"; 571 clocks = <&clks 9>, <&clks 11>; 572 clock-names = "ipg", "per"; 573 status = "disabled"; 574 }; 575 576 can3: can@402b2000 { 577 compatible = "nxp,s32g3-flexcan", 578 "nxp,s32g2-flexcan"; 579 reg = <0x402b2000 0xa000>; 580 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "mb-0", "state", "berr", "mb-1"; 585 clocks = <&clks 9>, <&clks 11>; 586 clock-names = "ipg", "per"; 587 status = "disabled"; 588 }; 589 590 uart2: serial@402bc000 { 591 compatible = "nxp,s32g3-linflexuart", 592 "fsl,s32v234-linflexuart"; 593 reg = <0x402bc000 0x3000>; 594 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 595 status = "disabled"; 596 }; 597 598 spi3: spi@402c8000 { 599 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 600 reg = <0x402c8000 0x1000>; 601 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clks 26>; 603 clock-names = "dspi"; 604 spi-num-chipselects = <5>; 605 bus-num = <3>; 606 dmas = <&edma0 1 7>, <&edma0 1 8>; 607 dma-names = "tx", "rx"; 608 status = "disabled"; 609 }; 610 611 spi4: spi@402cc000 { 612 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 613 reg = <0x402cc000 0x1000>; 614 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clks 26>; 616 clock-names = "dspi"; 617 spi-num-chipselects = <5>; 618 bus-num = <4>; 619 dmas = <&edma0 1 10>, <&edma0 1 11>; 620 dma-names = "tx", "rx"; 621 status = "disabled"; 622 }; 623 624 spi5: spi@402d0000 { 625 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 626 reg = <0x402d0000 0x1000>; 627 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clks 26>; 629 clock-names = "dspi"; 630 spi-num-chipselects = <5>; 631 bus-num = <5>; 632 dmas = <&edma0 1 13>, <&edma0 1 14>; 633 dma-names = "tx", "rx"; 634 status = "disabled"; 635 }; 636 637 i2c3: i2c@402d8000 { 638 compatible = "nxp,s32g3-i2c", 639 "nxp,s32g2-i2c"; 640 reg = <0x402d8000 0x1000>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clks 40>; 645 clock-names = "ipg"; 646 status = "disabled"; 647 }; 648 649 i2c4: i2c@402dc000 { 650 compatible = "nxp,s32g3-i2c", 651 "nxp,s32g2-i2c"; 652 reg = <0x402dc000 0x1000>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clks 40>; 657 clock-names = "ipg"; 658 status = "disabled"; 659 }; 660 661 usdhc0: mmc@402f0000 { 662 compatible = "nxp,s32g3-usdhc", 663 "nxp,s32g2-usdhc"; 664 reg = <0x402f0000 0x1000>; 665 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clks 32>, 667 <&clks 31>, 668 <&clks 33>; 669 clock-names = "ipg", "ahb", "per"; 670 status = "disabled"; 671 }; 672 673 gic: interrupt-controller@50800000 { 674 compatible = "arm,gic-v3"; 675 #interrupt-cells = <3>; 676 interrupt-controller; 677 reg = <0x50800000 0x10000>, 678 <0x50900000 0x200000>, 679 <0x50400000 0x2000>, 680 <0x50410000 0x2000>, 681 <0x50420000 0x2000>; 682 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 683 }; 684 }; 685 686 timer { 687 compatible = "arm,armv8-timer"; 688 interrupt-parent = <&gic>; 689 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */ 690 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */ 691 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */ 692 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */ 693 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */ 694 arm,no-tick-in-suspend; 695 }; 696}; 697