1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright 2021-2024 NXP 4 * 5 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> 6 * Ciprian Costea <ciprianmarian.costea@nxp.com> 7 * Andra-Teodora Ilie <andra.ilie@nxp.com> 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "nxp,s32g3"; 14 interrupt-parent = <&gic>; 15 #address-cells = <0x02>; 16 #size-cells = <0x02>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 50 core2 { 51 cpu = <&cpu6>; 52 }; 53 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0>; 64 enable-method = "psci"; 65 clocks = <&dfs 0>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x1>; 72 enable-method = "psci"; 73 clocks = <&dfs 0>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 clocks = <&dfs 0>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x3>; 88 enable-method = "psci"; 89 clocks = <&dfs 0>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 clocks = <&dfs 0>; 98 }; 99 100 cpu5: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x101>; 104 enable-method = "psci"; 105 clocks = <&dfs 0>; 106 }; 107 108 cpu6: cpu@102 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 enable-method = "psci"; 113 clocks = <&dfs 0>; 114 }; 115 116 cpu7: cpu@103 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x103>; 120 enable-method = "psci"; 121 clocks = <&dfs 0>; 122 }; 123 }; 124 125 firmware { 126 scmi: scmi { 127 compatible = "arm,scmi-smc"; 128 shmem = <&scmi_shmem>; 129 arm,smc-id = <0xc20000fe>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 dfs: protocol@13 { 134 reg = <0x13>; 135 #clock-cells = <1>; 136 }; 137 138 clks: protocol@14 { 139 reg = <0x14>; 140 #clock-cells = <1>; 141 }; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 }; 149 150 151 pmu { 152 compatible = "arm,cortex-a53-pmu"; 153 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 154 }; 155 156 reserved-memory { 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 scmi_shmem: shm@d0000000 { 162 compatible = "arm,scmi-shmem"; 163 reg = <0x0 0xd0000000 0x0 0x80>; 164 no-map; 165 }; 166 }; 167 168 soc@0 { 169 compatible = "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0 0 0 0x80000000>; 173 174 rtc0: rtc@40060000 { 175 compatible = "nxp,s32g3-rtc", 176 "nxp,s32g2-rtc"; 177 reg = <0x40060000 0x1000>; 178 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&clks 54>, <&clks 55>; 180 clock-names = "ipg", "source0"; 181 }; 182 183 pinctrl: pinctrl@4009c240 { 184 compatible = "nxp,s32g2-siul2-pinctrl"; 185 /* MSCR0-MSCR101 registers on siul2_0 */ 186 reg = <0x4009c240 0x198>, 187 /* MSCR112-MSCR122 registers on siul2_1 */ 188 <0x44010400 0x2c>, 189 /* MSCR144-MSCR190 registers on siul2_1 */ 190 <0x44010480 0xbc>, 191 /* IMCR0-IMCR83 registers on siul2_0 */ 192 <0x4009ca40 0x150>, 193 /* IMCR119-IMCR397 registers on siul2_1 */ 194 <0x44010c1c 0x45c>, 195 /* IMCR430-IMCR495 registers on siul2_1 */ 196 <0x440110f8 0x108>; 197 198 jtag_pins: jtag-pins { 199 jtag-grp0 { 200 pinmux = <0x0>; 201 input-enable; 202 bias-pull-up; 203 slew-rate = <166>; 204 }; 205 206 jtag-grp1 { 207 pinmux = <0x11>; 208 slew-rate = <166>; 209 }; 210 211 jtag-grp2 { 212 pinmux = <0x40>; 213 input-enable; 214 bias-pull-down; 215 slew-rate = <166>; 216 }; 217 218 jtag-grp3 { 219 pinmux = <0x23c0>, 220 <0x23d0>, 221 <0x2320>; 222 }; 223 224 jtag-grp4 { 225 pinmux = <0x51>; 226 input-enable; 227 bias-pull-up; 228 slew-rate = <166>; 229 }; 230 }; 231 232 pinctrl_usdhc0: usdhc0grp-pins { 233 usdhc0-grp0 { 234 pinmux = <0x2e1>, 235 <0x381>; 236 output-enable; 237 bias-pull-down; 238 slew-rate = <150>; 239 }; 240 241 usdhc0-grp1 { 242 pinmux = <0x2f1>, 243 <0x301>, 244 <0x311>, 245 <0x321>, 246 <0x331>, 247 <0x341>, 248 <0x351>, 249 <0x361>, 250 <0x371>; 251 output-enable; 252 input-enable; 253 bias-pull-up; 254 slew-rate = <150>; 255 }; 256 257 usdhc0-grp2 { 258 pinmux = <0x391>; 259 output-enable; 260 slew-rate = <150>; 261 }; 262 263 usdhc0-grp3 { 264 pinmux = <0x3a0>; 265 input-enable; 266 slew-rate = <150>; 267 }; 268 269 usdhc0-grp4 { 270 pinmux = <0x2032>, 271 <0x2042>, 272 <0x2052>, 273 <0x2062>, 274 <0x2072>, 275 <0x2082>, 276 <0x2092>, 277 <0x20a2>, 278 <0x20b2>, 279 <0x20c2>; 280 }; 281 }; 282 283 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 284 usdhc0-100mhz-grp0 { 285 pinmux = <0x2e1>, 286 <0x381>; 287 output-enable; 288 bias-pull-down; 289 slew-rate = <150>; 290 }; 291 292 usdhc0-100mhz-grp1 { 293 pinmux = <0x2f1>, 294 <0x301>, 295 <0x311>, 296 <0x321>, 297 <0x331>, 298 <0x341>, 299 <0x351>, 300 <0x361>, 301 <0x371>; 302 output-enable; 303 input-enable; 304 bias-pull-up; 305 slew-rate = <150>; 306 }; 307 308 usdhc0-100mhz-grp2 { 309 pinmux = <0x391>; 310 output-enable; 311 slew-rate = <150>; 312 }; 313 314 usdhc0-100mhz-grp3 { 315 pinmux = <0x3a0>; 316 input-enable; 317 slew-rate = <150>; 318 }; 319 320 usdhc0-100mhz-grp4 { 321 pinmux = <0x2032>, 322 <0x2042>, 323 <0x2052>, 324 <0x2062>, 325 <0x2072>, 326 <0x2082>, 327 <0x2092>, 328 <0x20a2>, 329 <0x20b2>, 330 <0x20c2>; 331 }; 332 }; 333 334 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 335 usdhc0-200mhz-grp0 { 336 pinmux = <0x2e1>, 337 <0x381>; 338 output-enable; 339 bias-pull-down; 340 slew-rate = <208>; 341 }; 342 343 usdhc0-200mhz-grp1 { 344 pinmux = <0x2f1>, 345 <0x301>, 346 <0x311>, 347 <0x321>, 348 <0x331>, 349 <0x341>, 350 <0x351>, 351 <0x361>, 352 <0x371>; 353 output-enable; 354 input-enable; 355 bias-pull-up; 356 slew-rate = <208>; 357 }; 358 359 usdhc0-200mhz-grp2 { 360 pinmux = <0x391>; 361 output-enable; 362 slew-rate = <208>; 363 }; 364 365 usdhc0-200mhz-grp3 { 366 pinmux = <0x3a0>; 367 input-enable; 368 slew-rate = <208>; 369 }; 370 371 usdhc0-200mhz-grp4 { 372 pinmux = <0x2032>, 373 <0x2042>, 374 <0x2052>, 375 <0x2062>, 376 <0x2072>, 377 <0x2082>, 378 <0x2092>, 379 <0x20a2>, 380 <0x20b2>, 381 <0x20c2>; 382 }; 383 }; 384 }; 385 386 ocotp: nvmem@400a4000 { 387 compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; 388 reg = <0x400a4000 0x400>; 389 #address-cells = <1>; 390 #size-cells = <1>; 391 }; 392 393 swt0: watchdog@40100000 { 394 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 395 reg = <0x40100000 0x1000>; 396 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 397 clock-names = "counter", "module", "register"; 398 status = "disabled"; 399 }; 400 401 swt1: watchdog@40104000 { 402 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 403 reg = <0x40104000 0x1000>; 404 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 405 clock-names = "counter", "module", "register"; 406 status = "disabled"; 407 }; 408 409 swt2: watchdog@40108000 { 410 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 411 reg = <0x40108000 0x1000>; 412 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 413 clock-names = "counter", "module", "register"; 414 status = "disabled"; 415 }; 416 417 swt3: watchdog@4010c000 { 418 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 419 reg = <0x4010c000 0x1000>; 420 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 421 clock-names = "counter", "module", "register"; 422 status = "disabled"; 423 }; 424 425 stm0: timer@4011c000 { 426 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 427 reg = <0x4011c000 0x3000>; 428 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 429 clock-names = "counter", "module", "register"; 430 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 431 status = "disabled"; 432 }; 433 434 stm1: timer@40120000 { 435 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 436 reg = <0x40120000 0x3000>; 437 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 438 clock-names = "counter", "module", "register"; 439 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 440 status = "disabled"; 441 }; 442 443 stm2: timer@40124000 { 444 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 445 reg = <0x40124000 0x3000>; 446 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 447 clock-names = "counter", "module", "register"; 448 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 449 status = "disabled"; 450 }; 451 452 stm3: timer@40128000 { 453 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 454 reg = <0x40128000 0x3000>; 455 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 456 clock-names = "counter", "module", "register"; 457 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 458 status = "disabled"; 459 }; 460 461 edma0: dma-controller@40144000 { 462 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 463 reg = <0x40144000 0x24000>, 464 <0x4012c000 0x3000>, 465 <0x40130000 0x3000>; 466 #dma-cells = <2>; 467 dma-channels = <32>; 468 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "tx-0-15", 472 "tx-16-31", 473 "err"; 474 clocks = <&clks 63>, <&clks 64>; 475 clock-names = "dmamux0", "dmamux1"; 476 }; 477 478 can0: can@401b4000 { 479 compatible = "nxp,s32g3-flexcan", 480 "nxp,s32g2-flexcan"; 481 reg = <0x401b4000 0xa000>; 482 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "mb-0", "state", "berr", "mb-1"; 487 clocks = <&clks 9>, <&clks 11>; 488 clock-names = "ipg", "per"; 489 status = "disabled"; 490 }; 491 492 can1: can@401be000 { 493 compatible = "nxp,s32g3-flexcan", 494 "nxp,s32g2-flexcan"; 495 reg = <0x401be000 0xa000>; 496 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 500 interrupt-names = "mb-0", "state", "berr", "mb-1"; 501 clocks = <&clks 9>, <&clks 11>; 502 clock-names = "ipg", "per"; 503 status = "disabled"; 504 }; 505 506 uart0: serial@401c8000 { 507 compatible = "nxp,s32g3-linflexuart", 508 "fsl,s32v234-linflexuart"; 509 reg = <0x401c8000 0x3000>; 510 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 511 status = "disabled"; 512 }; 513 514 uart1: serial@401cc000 { 515 compatible = "nxp,s32g3-linflexuart", 516 "fsl,s32v234-linflexuart"; 517 reg = <0x401cc000 0x3000>; 518 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 519 status = "disabled"; 520 }; 521 522 usbmisc: usbmisc@44064200 { 523 #index-cells = <1>; 524 compatible = "nxp,s32g3-usbmisc"; 525 reg = <0x44064200 0x200>; 526 }; 527 528 usbotg: usb@44064000 { 529 compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; 530 reg = <0x44064000 0x200>; 531 interrupt-parent = <&gic>; 532 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ 533 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ 534 clocks = <&clks 94>, <&clks 95>; 535 fsl,usbmisc = <&usbmisc 0>; 536 ahb-burst-config = <0x3>; 537 tx-burst-size-dword = <0x10>; 538 rx-burst-size-dword = <0x10>; 539 phy_type = "ulpi"; 540 dr_mode = "host"; 541 maximum-speed = "high-speed"; 542 status = "disabled"; 543 }; 544 545 spi0: spi@401d4000 { 546 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 547 reg = <0x401d4000 0x1000>; 548 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clks 26>; 550 clock-names = "dspi"; 551 spi-num-chipselects = <8>; 552 bus-num = <0>; 553 dmas = <&edma0 0 7>, <&edma0 0 8>; 554 dma-names = "tx", "rx"; 555 status = "disabled"; 556 }; 557 558 spi1: spi@401d8000 { 559 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 560 reg = <0x401d8000 0x1000>; 561 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clks 26>; 563 clock-names = "dspi"; 564 spi-num-chipselects = <5>; 565 bus-num = <1>; 566 dmas = <&edma0 0 10>, <&edma0 0 11>; 567 dma-names = "tx", "rx"; 568 status = "disabled"; 569 }; 570 571 spi2: spi@401dc000 { 572 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 573 reg = <0x401dc000 0x1000>; 574 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clks 26>; 576 clock-names = "dspi"; 577 spi-num-chipselects = <5>; 578 bus-num = <2>; 579 dmas = <&edma0 0 13>, <&edma0 0 14>; 580 dma-names = "tx", "rx"; 581 status = "disabled"; 582 }; 583 584 i2c0: i2c@401e4000 { 585 compatible = "nxp,s32g3-i2c", 586 "nxp,s32g2-i2c"; 587 reg = <0x401e4000 0x1000>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clks 40>; 592 clock-names = "ipg"; 593 status = "disabled"; 594 }; 595 596 i2c1: i2c@401e8000 { 597 compatible = "nxp,s32g3-i2c", 598 "nxp,s32g2-i2c"; 599 reg = <0x401e8000 0x1000>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&clks 40>; 604 clock-names = "ipg"; 605 status = "disabled"; 606 }; 607 608 i2c2: i2c@401ec000 { 609 compatible = "nxp,s32g3-i2c", 610 "nxp,s32g2-i2c"; 611 reg = <0x401ec000 0x1000>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clks 40>; 616 clock-names = "ipg"; 617 status = "disabled"; 618 }; 619 620 swt4: watchdog@40200000 { 621 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 622 reg = <0x40200000 0x1000>; 623 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 624 clock-names = "counter", "module", "register"; 625 status = "disabled"; 626 }; 627 628 swt5: watchdog@40204000 { 629 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 630 reg = <0x40204000 0x1000>; 631 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 632 clock-names = "counter", "module", "register"; 633 status = "disabled"; 634 }; 635 636 swt6: watchdog@40208000 { 637 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 638 reg = <0x40208000 0x1000>; 639 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 640 clock-names = "counter", "module", "register"; 641 status = "disabled"; 642 }; 643 644 swt7: watchdog@4020C000 { 645 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 646 reg = <0x4020C000 0x1000>; 647 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 648 clock-names = "counter", "module", "register"; 649 status = "disabled"; 650 }; 651 652 stm4: timer@4021c000 { 653 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 654 reg = <0x4021c000 0x3000>; 655 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 656 clock-names = "counter", "module", "register"; 657 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 658 status = "disabled"; 659 }; 660 661 stm5: timer@40220000 { 662 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 663 reg = <0x40220000 0x3000>; 664 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 665 clock-names = "counter", "module", "register"; 666 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 667 status = "disabled"; 668 }; 669 670 stm6: timer@40224000 { 671 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 672 reg = <0x40224000 0x3000>; 673 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 674 clock-names = "counter", "module", "register"; 675 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 676 status = "disabled"; 677 }; 678 679 edma1: dma-controller@40244000 { 680 compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; 681 reg = <0x40244000 0x24000>, 682 <0x4022c000 0x3000>, 683 <0x40230000 0x3000>; 684 #dma-cells = <2>; 685 dma-channels = <32>; 686 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "tx-0-15", 690 "tx-16-31", 691 "err"; 692 clocks = <&clks 63>, <&clks 64>; 693 clock-names = "dmamux0", "dmamux1"; 694 }; 695 696 can2: can@402a8000 { 697 compatible = "nxp,s32g3-flexcan", 698 "nxp,s32g2-flexcan"; 699 reg = <0x402a8000 0xa000>; 700 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "mb-0", "state", "berr", "mb-1"; 705 clocks = <&clks 9>, <&clks 11>; 706 clock-names = "ipg", "per"; 707 status = "disabled"; 708 }; 709 710 can3: can@402b2000 { 711 compatible = "nxp,s32g3-flexcan", 712 "nxp,s32g2-flexcan"; 713 reg = <0x402b2000 0xa000>; 714 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 718 interrupt-names = "mb-0", "state", "berr", "mb-1"; 719 clocks = <&clks 9>, <&clks 11>; 720 clock-names = "ipg", "per"; 721 status = "disabled"; 722 }; 723 724 uart2: serial@402bc000 { 725 compatible = "nxp,s32g3-linflexuart", 726 "fsl,s32v234-linflexuart"; 727 reg = <0x402bc000 0x3000>; 728 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 729 status = "disabled"; 730 }; 731 732 spi3: spi@402c8000 { 733 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 734 reg = <0x402c8000 0x1000>; 735 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clks 26>; 737 clock-names = "dspi"; 738 spi-num-chipselects = <5>; 739 bus-num = <3>; 740 dmas = <&edma0 1 7>, <&edma0 1 8>; 741 dma-names = "tx", "rx"; 742 status = "disabled"; 743 }; 744 745 spi4: spi@402cc000 { 746 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 747 reg = <0x402cc000 0x1000>; 748 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clks 26>; 750 clock-names = "dspi"; 751 spi-num-chipselects = <5>; 752 bus-num = <4>; 753 dmas = <&edma0 1 10>, <&edma0 1 11>; 754 dma-names = "tx", "rx"; 755 status = "disabled"; 756 }; 757 758 spi5: spi@402d0000 { 759 compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; 760 reg = <0x402d0000 0x1000>; 761 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clks 26>; 763 clock-names = "dspi"; 764 spi-num-chipselects = <5>; 765 bus-num = <5>; 766 dmas = <&edma0 1 13>, <&edma0 1 14>; 767 dma-names = "tx", "rx"; 768 status = "disabled"; 769 }; 770 771 i2c3: i2c@402d8000 { 772 compatible = "nxp,s32g3-i2c", 773 "nxp,s32g2-i2c"; 774 reg = <0x402d8000 0x1000>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&clks 40>; 779 clock-names = "ipg"; 780 status = "disabled"; 781 }; 782 783 i2c4: i2c@402dc000 { 784 compatible = "nxp,s32g3-i2c", 785 "nxp,s32g2-i2c"; 786 reg = <0x402dc000 0x1000>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&clks 40>; 791 clock-names = "ipg"; 792 status = "disabled"; 793 }; 794 795 usdhc0: mmc@402f0000 { 796 compatible = "nxp,s32g3-usdhc", 797 "nxp,s32g2-usdhc"; 798 reg = <0x402f0000 0x1000>; 799 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clks 32>, 801 <&clks 31>, 802 <&clks 33>; 803 clock-names = "ipg", "ahb", "per"; 804 status = "disabled"; 805 }; 806 807 swt8: watchdog@40500000 { 808 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 809 reg = <40500000 0x1000>; 810 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 811 clock-names = "counter", "module", "register"; 812 status = "disabled"; 813 }; 814 815 swt9: watchdog@40504000 { 816 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 817 reg = <0x40504000 0x1000>; 818 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 819 clock-names = "counter", "module", "register"; 820 status = "disabled"; 821 }; 822 823 swt10: watchdog@40508000 { 824 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 825 reg = <0x40508000 0x1000>; 826 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 827 clock-names = "counter", "module", "register"; 828 status = "disabled"; 829 }; 830 831 swt11: watchdog@4050c000 { 832 compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; 833 reg = <0x4050c000 0x1000>; 834 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 835 clock-names = "counter", "module", "register"; 836 status = "disabled"; 837 }; 838 839 stm8: timer@40520000 { 840 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 841 reg = <0x40520000 0x3000>; 842 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 843 clock-names = "counter", "module", "register"; 844 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 845 status = "disabled"; 846 }; 847 848 stm9: timer@40524000 { 849 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 850 reg = <0x40524000 0x3000>; 851 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 852 clock-names = "counter", "module", "register"; 853 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 854 status = "disabled"; 855 }; 856 857 stm10: timer@40528000 { 858 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 859 reg = <0x40528000 0x3000>; 860 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 861 clock-names = "counter", "module", "register"; 862 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 }; 865 866 stm11: timer@4052c000 { 867 compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; 868 reg = <0x4052c000 0x3000>; 869 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 870 clock-names = "counter", "module", "register"; 871 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 872 status = "disabled"; 873 }; 874 875 gic: interrupt-controller@50800000 { 876 compatible = "arm,gic-v3"; 877 #interrupt-cells = <3>; 878 interrupt-controller; 879 reg = <0x50800000 0x10000>, 880 <0x50900000 0x200000>, 881 <0x50400000 0x2000>, 882 <0x50410000 0x2000>, 883 <0x50420000 0x2000>; 884 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 885 }; 886 }; 887 888 timer { 889 compatible = "arm,armv8-timer"; 890 interrupt-parent = <&gic>; 891 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */ 892 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */ 893 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */ 894 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */ 895 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */ 896 arm,no-tick-in-suspend; 897 }; 898}; 899