xref: /linux/arch/arm64/boot/dts/freescale/s32g3.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright 2021-2024 NXP
4 *
5 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
6 *          Ciprian Costea <ciprianmarian.costea@nxp.com>
7 *          Andra-Teodora Ilie <andra.ilie@nxp.com>
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "nxp,s32g3";
14	interrupt-parent = <&gic>;
15	#address-cells = <0x02>;
16	#size-cells = <0x02>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27
28				core1 {
29					cpu = <&cpu1>;
30				};
31
32				core2 {
33					cpu = <&cpu2>;
34				};
35
36				core3 {
37					cpu = <&cpu3>;
38				};
39			};
40
41			cluster1 {
42				core0 {
43					cpu = <&cpu4>;
44				};
45
46				core1 {
47					cpu = <&cpu5>;
48				};
49
50				core2 {
51					cpu = <&cpu6>;
52				};
53
54				core3 {
55					cpu = <&cpu7>;
56				};
57			};
58		};
59
60		cpu0: cpu@0 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			reg = <0x0>;
64			enable-method = "psci";
65			clocks = <&dfs 0>;
66		};
67
68		cpu1: cpu@1 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53";
71			reg = <0x1>;
72			enable-method = "psci";
73			clocks = <&dfs 0>;
74		};
75
76		cpu2: cpu@2 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a53";
79			reg = <0x2>;
80			enable-method = "psci";
81			clocks = <&dfs 0>;
82		};
83
84		cpu3: cpu@3 {
85			device_type = "cpu";
86			compatible = "arm,cortex-a53";
87			reg = <0x3>;
88			enable-method = "psci";
89			clocks = <&dfs 0>;
90		};
91
92		cpu4: cpu@100 {
93			device_type = "cpu";
94			compatible = "arm,cortex-a53";
95			reg = <0x100>;
96			enable-method = "psci";
97			clocks = <&dfs 0>;
98		};
99
100		cpu5: cpu@101 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a53";
103			reg = <0x101>;
104			enable-method = "psci";
105			clocks = <&dfs 0>;
106		};
107
108		cpu6: cpu@102 {
109			device_type = "cpu";
110			compatible = "arm,cortex-a53";
111			reg = <0x102>;
112			enable-method = "psci";
113			clocks = <&dfs 0>;
114		};
115
116		cpu7: cpu@103 {
117			device_type = "cpu";
118			compatible = "arm,cortex-a53";
119			reg = <0x103>;
120			enable-method = "psci";
121			clocks = <&dfs 0>;
122		};
123	};
124
125	firmware {
126		scmi: scmi {
127			compatible = "arm,scmi-smc";
128			shmem = <&scmi_shmem>;
129			arm,smc-id = <0xc20000fe>;
130			#address-cells = <1>;
131			#size-cells = <0>;
132
133			dfs: protocol@13 {
134				reg = <0x13>;
135				#clock-cells = <1>;
136			};
137
138			clks: protocol@14 {
139				reg = <0x14>;
140				#clock-cells = <1>;
141			};
142		};
143
144		psci: psci {
145			compatible = "arm,psci-1.0";
146			method = "smc";
147		};
148	};
149
150
151	pmu {
152		compatible = "arm,cortex-a53-pmu";
153		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
154	};
155
156	reserved-memory  {
157		#address-cells = <2>;
158		#size-cells = <2>;
159		ranges;
160
161		scmi_shmem: shm@d0000000 {
162			compatible = "arm,scmi-shmem";
163			reg = <0x0 0xd0000000 0x0 0x80>;
164			no-map;
165		};
166	};
167
168	soc@0 {
169		compatible = "simple-bus";
170		#address-cells = <1>;
171		#size-cells = <1>;
172		ranges = <0 0 0 0x80000000>;
173
174		pinctrl: pinctrl@4009c240 {
175			compatible = "nxp,s32g2-siul2-pinctrl";
176				/* MSCR0-MSCR101 registers on siul2_0 */
177			reg = <0x4009c240 0x198>,
178				/* MSCR112-MSCR122 registers on siul2_1 */
179			      <0x44010400 0x2c>,
180				/* MSCR144-MSCR190 registers on siul2_1 */
181			      <0x44010480 0xbc>,
182				/* IMCR0-IMCR83 registers on siul2_0 */
183			      <0x4009ca40 0x150>,
184				/* IMCR119-IMCR397 registers on siul2_1 */
185			      <0x44010c1c 0x45c>,
186				/* IMCR430-IMCR495 registers on siul2_1 */
187			      <0x440110f8 0x108>;
188
189			jtag_pins: jtag-pins {
190				jtag-grp0 {
191					pinmux = <0x0>;
192					input-enable;
193					bias-pull-up;
194					slew-rate = <166>;
195				};
196
197				jtag-grp1 {
198					pinmux = <0x11>;
199					slew-rate = <166>;
200				};
201
202				jtag-grp2 {
203					pinmux = <0x40>;
204					input-enable;
205					bias-pull-down;
206					slew-rate = <166>;
207				};
208
209				jtag-grp3 {
210					pinmux = <0x23c0>,
211						 <0x23d0>,
212						 <0x2320>;
213				};
214
215				jtag-grp4 {
216					pinmux = <0x51>;
217					input-enable;
218					bias-pull-up;
219					slew-rate = <166>;
220				};
221			};
222
223			pinctrl_usdhc0: usdhc0grp-pins {
224				usdhc0-grp0 {
225					pinmux = <0x2e1>,
226						 <0x381>;
227					output-enable;
228					bias-pull-down;
229					slew-rate = <150>;
230				};
231
232				usdhc0-grp1 {
233					pinmux = <0x2f1>,
234						 <0x301>,
235						 <0x311>,
236						 <0x321>,
237						 <0x331>,
238						 <0x341>,
239						 <0x351>,
240						 <0x361>,
241						 <0x371>;
242					output-enable;
243					input-enable;
244					bias-pull-up;
245					slew-rate = <150>;
246				};
247
248				usdhc0-grp2 {
249					pinmux = <0x391>;
250					output-enable;
251					slew-rate = <150>;
252				};
253
254				usdhc0-grp3 {
255					pinmux = <0x3a0>;
256					input-enable;
257					slew-rate = <150>;
258				};
259
260				usdhc0-grp4 {
261					pinmux = <0x2032>,
262						 <0x2042>,
263						 <0x2052>,
264						 <0x2062>,
265						 <0x2072>,
266						 <0x2082>,
267						 <0x2092>,
268						 <0x20a2>,
269						 <0x20b2>,
270						 <0x20c2>;
271				};
272			};
273
274			pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
275				usdhc0-100mhz-grp0 {
276					pinmux = <0x2e1>,
277						 <0x381>;
278					output-enable;
279					bias-pull-down;
280					slew-rate = <150>;
281				};
282
283				usdhc0-100mhz-grp1 {
284					pinmux = <0x2f1>,
285						 <0x301>,
286						 <0x311>,
287						 <0x321>,
288						 <0x331>,
289						 <0x341>,
290						 <0x351>,
291						 <0x361>,
292						 <0x371>;
293					output-enable;
294					input-enable;
295					bias-pull-up;
296					slew-rate = <150>;
297				};
298
299				usdhc0-100mhz-grp2 {
300					pinmux = <0x391>;
301					output-enable;
302					slew-rate = <150>;
303				};
304
305				usdhc0-100mhz-grp3 {
306					pinmux = <0x3a0>;
307					input-enable;
308					slew-rate = <150>;
309				};
310
311				usdhc0-100mhz-grp4 {
312					pinmux = <0x2032>,
313						 <0x2042>,
314						 <0x2052>,
315						 <0x2062>,
316						 <0x2072>,
317						 <0x2082>,
318						 <0x2092>,
319						 <0x20a2>,
320						 <0x20b2>,
321						 <0x20c2>;
322				};
323			};
324
325			pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
326				usdhc0-200mhz-grp0 {
327					pinmux = <0x2e1>,
328						 <0x381>;
329					output-enable;
330					bias-pull-down;
331					slew-rate = <208>;
332				};
333
334				usdhc0-200mhz-grp1 {
335					pinmux = <0x2f1>,
336						 <0x301>,
337						 <0x311>,
338						 <0x321>,
339						 <0x331>,
340						 <0x341>,
341						 <0x351>,
342						 <0x361>,
343						 <0x371>;
344					output-enable;
345					input-enable;
346					bias-pull-up;
347					slew-rate = <208>;
348				};
349
350				usdhc0-200mhz-grp2 {
351					pinmux = <0x391>;
352					output-enable;
353					slew-rate = <208>;
354				};
355
356				usdhc0-200mhz-grp3 {
357					pinmux = <0x3a0>;
358					input-enable;
359					slew-rate = <208>;
360				};
361
362				usdhc0-200mhz-grp4 {
363					pinmux = <0x2032>,
364						 <0x2042>,
365						 <0x2052>,
366						 <0x2062>,
367						 <0x2072>,
368						 <0x2082>,
369						 <0x2092>,
370						 <0x20a2>,
371						 <0x20b2>,
372						 <0x20c2>;
373				};
374			};
375		};
376
377		uart0: serial@401c8000 {
378			compatible = "nxp,s32g3-linflexuart",
379				     "fsl,s32v234-linflexuart";
380			reg = <0x401c8000 0x3000>;
381			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
382			status = "disabled";
383		};
384
385		uart1: serial@401cc000 {
386			compatible = "nxp,s32g3-linflexuart",
387				     "fsl,s32v234-linflexuart";
388			reg = <0x401cc000 0x3000>;
389			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
390			status = "disabled";
391		};
392
393		uart2: serial@402bc000 {
394			compatible = "nxp,s32g3-linflexuart",
395				     "fsl,s32v234-linflexuart";
396			reg = <0x402bc000 0x3000>;
397			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
398			status = "disabled";
399		};
400
401		usdhc0: mmc@402f0000 {
402			compatible = "nxp,s32g3-usdhc",
403				     "nxp,s32g2-usdhc";
404			reg = <0x402f0000 0x1000>;
405			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
406			clocks = <&clks 32>,
407				 <&clks 31>,
408				 <&clks 33>;
409			clock-names = "ipg", "ahb", "per";
410			status = "disabled";
411		};
412
413		gic: interrupt-controller@50800000 {
414			compatible = "arm,gic-v3";
415			#interrupt-cells = <3>;
416			interrupt-controller;
417			reg = <0x50800000 0x10000>,
418			      <0x50900000 0x200000>,
419			      <0x50400000 0x2000>,
420			      <0x50410000 0x2000>,
421			      <0x50420000 0x2000>;
422			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
423		};
424	};
425
426	timer {
427		compatible = "arm,armv8-timer";
428		interrupt-parent = <&gic>;
429		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
430			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
431			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
432			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
433			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
434		arm,no-tick-in-suspend;
435	};
436};
437