1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright 2017-2021, 2024 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 scmi_buf: shm@d0000000 { 23 compatible = "arm,scmi-shmem"; 24 reg = <0x0 0xd0000000 0x0 0x80>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&cluster0_l2>; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x1>; 45 enable-method = "psci"; 46 next-level-cache = <&cluster0_l2>; 47 }; 48 49 cpu2: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x100>; 53 enable-method = "psci"; 54 next-level-cache = <&cluster1_l2>; 55 }; 56 57 cpu3: cpu@101 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x101>; 61 enable-method = "psci"; 62 next-level-cache = <&cluster1_l2>; 63 }; 64 65 cluster0_l2: l2-cache0 { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 71 cluster1_l2: l2-cache1 { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 }; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 89 }; 90 91 firmware { 92 scmi { 93 compatible = "arm,scmi-smc"; 94 arm,smc-id = <0xc20000fe>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 shmem = <&scmi_buf>; 98 99 clks: protocol@14 { 100 reg = <0x14>; 101 #clock-cells = <1>; 102 }; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 }; 110 111 soc@0 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0 0 0x80000000>; 116 117 rtc0: rtc@40060000 { 118 compatible = "nxp,s32g2-rtc"; 119 reg = <0x40060000 0x1000>; 120 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clks 54>, <&clks 55>; 122 clock-names = "ipg", "source0"; 123 }; 124 125 pinctrl: pinctrl@4009c240 { 126 compatible = "nxp,s32g2-siul2-pinctrl"; 127 /* MSCR0-MSCR101 registers on siul2_0 */ 128 reg = <0x4009c240 0x198>, 129 /* MSCR112-MSCR122 registers on siul2_1 */ 130 <0x44010400 0x2c>, 131 /* MSCR144-MSCR190 registers on siul2_1 */ 132 <0x44010480 0xbc>, 133 /* IMCR0-IMCR83 registers on siul2_0 */ 134 <0x4009ca40 0x150>, 135 /* IMCR119-IMCR397 registers on siul2_1 */ 136 <0x44010c1c 0x45c>, 137 /* IMCR430-IMCR495 registers on siul2_1 */ 138 <0x440110f8 0x108>; 139 140 jtag_pins: jtag-pins { 141 jtag-grp0 { 142 pinmux = <0x0>; 143 input-enable; 144 bias-pull-up; 145 slew-rate = <166>; 146 }; 147 148 jtag-grp1 { 149 pinmux = <0x11>; 150 slew-rate = <166>; 151 }; 152 153 jtag-grp2 { 154 pinmux = <0x40>; 155 input-enable; 156 bias-pull-down; 157 slew-rate = <166>; 158 }; 159 160 jtag-grp3 { 161 pinmux = <0x23c0>, 162 <0x23d0>, 163 <0x2320>; 164 }; 165 166 jtag-grp4 { 167 pinmux = <0x51>; 168 input-enable; 169 bias-pull-up; 170 slew-rate = <166>; 171 }; 172 }; 173 174 pinctrl_usdhc0: usdhc0grp-pins { 175 usdhc0-grp0 { 176 pinmux = <0x2e1>, 177 <0x381>; 178 output-enable; 179 bias-pull-down; 180 slew-rate = <150>; 181 }; 182 183 usdhc0-grp1 { 184 pinmux = <0x2f1>, 185 <0x301>, 186 <0x311>, 187 <0x321>, 188 <0x331>, 189 <0x341>, 190 <0x351>, 191 <0x361>, 192 <0x371>; 193 output-enable; 194 input-enable; 195 bias-pull-up; 196 slew-rate = <150>; 197 }; 198 199 usdhc0-grp2 { 200 pinmux = <0x391>; 201 output-enable; 202 slew-rate = <150>; 203 }; 204 205 usdhc0-grp3 { 206 pinmux = <0x3a0>; 207 input-enable; 208 slew-rate = <150>; 209 }; 210 211 usdhc0-grp4 { 212 pinmux = <0x2032>, 213 <0x2042>, 214 <0x2052>, 215 <0x2062>, 216 <0x2072>, 217 <0x2082>, 218 <0x2092>, 219 <0x20a2>, 220 <0x20b2>, 221 <0x20c2>; 222 }; 223 }; 224 225 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 226 usdhc0-100mhz-grp0 { 227 pinmux = <0x2e1>, 228 <0x381>; 229 output-enable; 230 bias-pull-down; 231 slew-rate = <150>; 232 }; 233 234 usdhc0-100mhz-grp1 { 235 pinmux = <0x2f1>, 236 <0x301>, 237 <0x311>, 238 <0x321>, 239 <0x331>, 240 <0x341>, 241 <0x351>, 242 <0x361>, 243 <0x371>; 244 output-enable; 245 input-enable; 246 bias-pull-up; 247 slew-rate = <150>; 248 }; 249 250 usdhc0-100mhz-grp2 { 251 pinmux = <0x391>; 252 output-enable; 253 slew-rate = <150>; 254 }; 255 256 usdhc0-100mhz-grp3 { 257 pinmux = <0x3a0>; 258 input-enable; 259 slew-rate = <150>; 260 }; 261 262 usdhc0-100mhz-grp4 { 263 pinmux = <0x2032>, 264 <0x2042>, 265 <0x2052>, 266 <0x2062>, 267 <0x2072>, 268 <0x2082>, 269 <0x2092>, 270 <0x20a2>, 271 <0x20b2>, 272 <0x20c2>; 273 }; 274 }; 275 276 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 277 usdhc0-200mhz-grp0 { 278 pinmux = <0x2e1>, 279 <0x381>; 280 output-enable; 281 bias-pull-down; 282 slew-rate = <208>; 283 }; 284 285 usdhc0-200mhz-grp1 { 286 pinmux = <0x2f1>, 287 <0x301>, 288 <0x311>, 289 <0x321>, 290 <0x331>, 291 <0x341>, 292 <0x351>, 293 <0x361>, 294 <0x371>; 295 output-enable; 296 input-enable; 297 bias-pull-up; 298 slew-rate = <208>; 299 }; 300 301 usdhc0-200mhz-grp2 { 302 pinmux = <0x391>; 303 output-enable; 304 slew-rate = <208>; 305 }; 306 307 usdhc0-200mhz-grp3 { 308 pinmux = <0x3a0>; 309 input-enable; 310 slew-rate = <208>; 311 }; 312 313 usdhc0-200mhz-grp4 { 314 pinmux = <0x2032>, 315 <0x2042>, 316 <0x2052>, 317 <0x2062>, 318 <0x2072>, 319 <0x2082>, 320 <0x2092>, 321 <0x20a2>, 322 <0x20b2>, 323 <0x20c2>; 324 }; 325 }; 326 }; 327 328 ocotp: nvmem@400a4000 { 329 compatible = "nxp,s32g2-ocotp"; 330 reg = <0x400a4000 0x400>; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 }; 334 335 swt0: watchdog@40100000 { 336 compatible = "nxp,s32g2-swt"; 337 reg = <0x40100000 0x1000>; 338 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 339 clock-names = "counter", "module", "register"; 340 status = "disabled"; 341 }; 342 343 swt1: watchdog@40104000 { 344 compatible = "nxp,s32g2-swt"; 345 reg = <0x40104000 0x1000>; 346 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 347 clock-names = "counter", "module", "register"; 348 status = "disabled"; 349 }; 350 351 swt2: watchdog@40108000 { 352 compatible = "nxp,s32g2-swt"; 353 reg = <0x40108000 0x1000>; 354 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 355 clock-names = "counter", "module", "register"; 356 status = "disabled"; 357 }; 358 359 swt3: watchdog@4010c000 { 360 compatible = "nxp,s32g2-swt"; 361 reg = <0x4010c000 0x1000>; 362 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 363 clock-names = "counter", "module", "register"; 364 status = "disabled"; 365 }; 366 367 stm0: timer@4011c000 { 368 compatible = "nxp,s32g2-stm"; 369 reg = <0x4011c000 0x3000>; 370 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 372 clock-names = "counter", "module", "register"; 373 status = "disabled"; 374 }; 375 376 stm1: timer@40120000 { 377 compatible = "nxp,s32g2-stm"; 378 reg = <0x40120000 0x3000>; 379 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 381 clock-names = "counter", "module", "register"; 382 status = "disabled"; 383 }; 384 385 stm2: timer@40124000 { 386 compatible = "nxp,s32g2-stm"; 387 reg = <0x40124000 0x3000>; 388 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 390 clock-names = "counter", "module", "register"; 391 status = "disabled"; 392 }; 393 394 stm3: timer@40128000 { 395 compatible = "nxp,s32g2-stm"; 396 reg = <0x40128000 0x3000>; 397 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 399 clock-names = "counter", "module", "register"; 400 status = "disabled"; 401 }; 402 403 edma0: dma-controller@40144000 { 404 compatible = "nxp,s32g2-edma"; 405 reg = <0x40144000 0x24000>, 406 <0x4012c000 0x3000>, 407 <0x40130000 0x3000>; 408 #dma-cells = <2>; 409 dma-channels = <32>; 410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "tx-0-15", 414 "tx-16-31", 415 "err"; 416 clocks = <&clks 63>, <&clks 64>; 417 clock-names = "dmamux0", "dmamux1"; 418 }; 419 420 can0: can@401b4000 { 421 compatible = "nxp,s32g2-flexcan"; 422 reg = <0x401b4000 0xa000>; 423 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 427 interrupt-names = "mb-0", "state", "berr", "mb-1"; 428 clocks = <&clks 9>, <&clks 11>; 429 clock-names = "ipg", "per"; 430 status = "disabled"; 431 }; 432 433 can1: can@401be000 { 434 compatible = "nxp,s32g2-flexcan"; 435 reg = <0x401be000 0xa000>; 436 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "mb-0", "state", "berr", "mb-1"; 441 clocks = <&clks 9>, <&clks 11>; 442 clock-names = "ipg", "per"; 443 status = "disabled"; 444 }; 445 446 uart0: serial@401c8000 { 447 compatible = "nxp,s32g2-linflexuart", 448 "fsl,s32v234-linflexuart"; 449 reg = <0x401c8000 0x3000>; 450 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 451 status = "disabled"; 452 }; 453 454 uart1: serial@401cc000 { 455 compatible = "nxp,s32g2-linflexuart", 456 "fsl,s32v234-linflexuart"; 457 reg = <0x401cc000 0x3000>; 458 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 459 status = "disabled"; 460 }; 461 462 usbmisc: usbmisc@44064200 { 463 #index-cells = <1>; 464 compatible = "nxp,s32g2-usbmisc"; 465 reg = <0x44064200 0x200>; 466 }; 467 468 usbotg: usb@44064000 { 469 compatible = "nxp,s32g2-usb"; 470 reg = <0x44064000 0x200>; 471 interrupt-parent = <&gic>; 472 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ 473 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ 474 clocks = <&clks 94>, <&clks 95>; 475 fsl,usbmisc = <&usbmisc 0>; 476 ahb-burst-config = <0x3>; 477 tx-burst-size-dword = <0x10>; 478 rx-burst-size-dword = <0x10>; 479 phy_type = "ulpi"; 480 dr_mode = "host"; 481 maximum-speed = "high-speed"; 482 status = "disabled"; 483 }; 484 485 spi0: spi@401d4000 { 486 compatible = "nxp,s32g2-dspi"; 487 reg = <0x401d4000 0x1000>; 488 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clks 26>; 490 clock-names = "dspi"; 491 spi-num-chipselects = <8>; 492 bus-num = <0>; 493 dmas = <&edma0 0 7>, <&edma0 0 8>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 spi1: spi@401d8000 { 499 compatible = "nxp,s32g2-dspi"; 500 reg = <0x401d8000 0x1000>; 501 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clks 26>; 503 clock-names = "dspi"; 504 spi-num-chipselects = <5>; 505 bus-num = <1>; 506 dmas = <&edma0 0 10>, <&edma0 0 11>; 507 dma-names = "tx", "rx"; 508 status = "disabled"; 509 }; 510 511 spi2: spi@401dc000 { 512 compatible = "nxp,s32g2-dspi"; 513 reg = <0x401dc000 0x1000>; 514 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clks 26>; 516 clock-names = "dspi"; 517 spi-num-chipselects = <5>; 518 bus-num = <2>; 519 dmas = <&edma0 0 13>, <&edma0 0 14>; 520 dma-names = "tx", "rx"; 521 status = "disabled"; 522 }; 523 524 i2c0: i2c@401e4000 { 525 compatible = "nxp,s32g2-i2c"; 526 reg = <0x401e4000 0x1000>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clks 40>; 531 clock-names = "ipg"; 532 status = "disabled"; 533 }; 534 535 i2c1: i2c@401e8000 { 536 compatible = "nxp,s32g2-i2c"; 537 reg = <0x401e8000 0x1000>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clks 40>; 542 clock-names = "ipg"; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@401ec000 { 547 compatible = "nxp,s32g2-i2c"; 548 reg = <0x401ec000 0x1000>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clks 40>; 553 clock-names = "ipg"; 554 status = "disabled"; 555 }; 556 557 swt4: watchdog@40200000 { 558 compatible = "nxp,s32g2-swt"; 559 reg = <0x40200000 0x1000>; 560 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 561 clock-names = "counter", "module", "register"; 562 status = "disabled"; 563 }; 564 565 swt5: watchdog@40204000 { 566 compatible = "nxp,s32g2-swt"; 567 reg = <0x40204000 0x1000>; 568 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 569 clock-names = "counter", "module", "register"; 570 status = "disabled"; 571 }; 572 573 swt6: watchdog@40208000 { 574 compatible = "nxp,s32g2-swt"; 575 reg = <0x40208000 0x1000>; 576 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 577 clock-names = "counter", "module", "register"; 578 status = "disabled"; 579 }; 580 581 stm4: timer@4021c000 { 582 compatible = "nxp,s32g2-stm"; 583 reg = <0x4021c000 0x3000>; 584 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 585 clock-names = "counter", "module", "register"; 586 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 587 status = "disabled"; 588 }; 589 590 stm5: timer@40220000 { 591 compatible = "nxp,s32g2-stm"; 592 reg = <0x40220000 0x3000>; 593 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 594 clock-names = "counter", "module", "register"; 595 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 596 status = "disabled"; 597 }; 598 599 stm6: timer@40224000 { 600 compatible = "nxp,s32g2-stm"; 601 reg = <0x40224000 0x3000>; 602 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 603 clock-names = "counter", "module", "register"; 604 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 605 status = "disabled"; 606 }; 607 608 edma1: dma-controller@40244000 { 609 compatible = "nxp,s32g2-edma"; 610 reg = <0x40244000 0x24000>, 611 <0x4022c000 0x3000>, 612 <0x40230000 0x3000>; 613 #dma-cells = <2>; 614 dma-channels = <32>; 615 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "tx-0-15", 619 "tx-16-31", 620 "err"; 621 clocks = <&clks 63>, <&clks 64>; 622 clock-names = "dmamux0", "dmamux1"; 623 }; 624 625 can2: can@402a8000 { 626 compatible = "nxp,s32g2-flexcan"; 627 reg = <0x402a8000 0xa000>; 628 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 632 interrupt-names = "mb-0", "state", "berr", "mb-1"; 633 clocks = <&clks 9>, <&clks 11>; 634 clock-names = "ipg", "per"; 635 status = "disabled"; 636 }; 637 638 can3: can@402b2000 { 639 compatible = "nxp,s32g2-flexcan"; 640 reg = <0x402b2000 0xa000>; 641 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "mb-0", "state", "berr", "mb-1"; 646 clocks = <&clks 9>, <&clks 11>; 647 clock-names = "ipg", "per"; 648 status = "disabled"; 649 }; 650 651 uart2: serial@402bc000 { 652 compatible = "nxp,s32g2-linflexuart", 653 "fsl,s32v234-linflexuart"; 654 reg = <0x402bc000 0x3000>; 655 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 656 status = "disabled"; 657 }; 658 659 spi3: spi@402c8000 { 660 compatible = "nxp,s32g2-dspi"; 661 reg = <0x402c8000 0x1000>; 662 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&clks 26>; 664 clock-names = "dspi"; 665 spi-num-chipselects = <5>; 666 bus-num = <3>; 667 dmas = <&edma0 1 7>, <&edma0 1 8>; 668 dma-names = "tx", "rx"; 669 status = "disabled"; 670 }; 671 672 spi4: spi@402cc000 { 673 compatible = "nxp,s32g2-dspi"; 674 reg = <0x402cc000 0x1000>; 675 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clks 26>; 677 clock-names = "dspi"; 678 spi-num-chipselects = <5>; 679 bus-num = <4>; 680 dmas = <&edma0 1 10>, <&edma0 1 11>; 681 dma-names = "tx", "rx"; 682 status = "disabled"; 683 }; 684 685 spi5: spi@402d0000 { 686 compatible = "nxp,s32g2-dspi"; 687 reg = <0x402d0000 0x1000>; 688 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clks 26>; 690 clock-names = "dspi"; 691 spi-num-chipselects = <5>; 692 bus-num = <5>; 693 dmas = <&edma0 1 13>, <&edma0 1 14>; 694 dma-names = "tx", "rx"; 695 status = "disabled"; 696 }; 697 698 i2c3: i2c@402d8000 { 699 compatible = "nxp,s32g2-i2c"; 700 reg = <0x402d8000 0x1000>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clks 40>; 705 clock-names = "ipg"; 706 status = "disabled"; 707 }; 708 709 i2c4: i2c@402dc000 { 710 compatible = "nxp,s32g2-i2c"; 711 reg = <0x402dc000 0x1000>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clks 40>; 716 clock-names = "ipg"; 717 status = "disabled"; 718 }; 719 720 usdhc0: mmc@402f0000 { 721 compatible = "nxp,s32g2-usdhc"; 722 reg = <0x402f0000 0x1000>; 723 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clks 32>, <&clks 31>, <&clks 33>; 725 clock-names = "ipg", "ahb", "per"; 726 bus-width = <8>; 727 status = "disabled"; 728 }; 729 730 gic: interrupt-controller@50800000 { 731 compatible = "arm,gic-v3"; 732 reg = <0x50800000 0x10000>, 733 <0x50880000 0x80000>, 734 <0x50400000 0x2000>, 735 <0x50410000 0x2000>, 736 <0x50420000 0x2000>; 737 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-controller; 739 #interrupt-cells = <3>; 740 }; 741 }; 742}; 743