1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright 2017-2021, 2024 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 scmi_buf: shm@d0000000 { 23 compatible = "arm,scmi-shmem"; 24 reg = <0x0 0xd0000000 0x0 0x80>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&cluster0_l2>; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x1>; 45 enable-method = "psci"; 46 next-level-cache = <&cluster0_l2>; 47 }; 48 49 cpu2: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x100>; 53 enable-method = "psci"; 54 next-level-cache = <&cluster1_l2>; 55 }; 56 57 cpu3: cpu@101 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x101>; 61 enable-method = "psci"; 62 next-level-cache = <&cluster1_l2>; 63 }; 64 65 cluster0_l2: l2-cache0 { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 71 cluster1_l2: l2-cache1 { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 }; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 89 }; 90 91 firmware { 92 scmi { 93 compatible = "arm,scmi-smc"; 94 arm,smc-id = <0xc20000fe>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 shmem = <&scmi_buf>; 98 99 clks: protocol@14 { 100 reg = <0x14>; 101 #clock-cells = <1>; 102 }; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 }; 110 111 soc@0 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0 0 0x80000000>; 116 117 rtc0: rtc@40060000 { 118 compatible = "nxp,s32g2-rtc"; 119 reg = <0x40060000 0x1000>; 120 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clks 54>, <&clks 55>; 122 clock-names = "ipg", "source0"; 123 }; 124 125 pinctrl: pinctrl@4009c240 { 126 compatible = "nxp,s32g2-siul2-pinctrl"; 127 /* MSCR0-MSCR101 registers on siul2_0 */ 128 reg = <0x4009c240 0x198>, 129 /* MSCR112-MSCR122 registers on siul2_1 */ 130 <0x44010400 0x2c>, 131 /* MSCR144-MSCR190 registers on siul2_1 */ 132 <0x44010480 0xbc>, 133 /* IMCR0-IMCR83 registers on siul2_0 */ 134 <0x4009ca40 0x150>, 135 /* IMCR119-IMCR397 registers on siul2_1 */ 136 <0x44010c1c 0x45c>, 137 /* IMCR430-IMCR495 registers on siul2_1 */ 138 <0x440110f8 0x108>; 139 140 jtag_pins: jtag-pins { 141 jtag-grp0 { 142 pinmux = <0x0>; 143 input-enable; 144 bias-pull-up; 145 slew-rate = <166>; 146 }; 147 148 jtag-grp1 { 149 pinmux = <0x11>; 150 slew-rate = <166>; 151 }; 152 153 jtag-grp2 { 154 pinmux = <0x40>; 155 input-enable; 156 bias-pull-down; 157 slew-rate = <166>; 158 }; 159 160 jtag-grp3 { 161 pinmux = <0x23c0>, 162 <0x23d0>, 163 <0x2320>; 164 }; 165 166 jtag-grp4 { 167 pinmux = <0x51>; 168 input-enable; 169 bias-pull-up; 170 slew-rate = <166>; 171 }; 172 }; 173 174 pinctrl_usdhc0: usdhc0grp-pins { 175 usdhc0-grp0 { 176 pinmux = <0x2e1>, 177 <0x381>; 178 output-enable; 179 bias-pull-down; 180 slew-rate = <150>; 181 }; 182 183 usdhc0-grp1 { 184 pinmux = <0x2f1>, 185 <0x301>, 186 <0x311>, 187 <0x321>, 188 <0x331>, 189 <0x341>, 190 <0x351>, 191 <0x361>, 192 <0x371>; 193 output-enable; 194 input-enable; 195 bias-pull-up; 196 slew-rate = <150>; 197 }; 198 199 usdhc0-grp2 { 200 pinmux = <0x391>; 201 output-enable; 202 slew-rate = <150>; 203 }; 204 205 usdhc0-grp3 { 206 pinmux = <0x3a0>; 207 input-enable; 208 slew-rate = <150>; 209 }; 210 211 usdhc0-grp4 { 212 pinmux = <0x2032>, 213 <0x2042>, 214 <0x2052>, 215 <0x2062>, 216 <0x2072>, 217 <0x2082>, 218 <0x2092>, 219 <0x20a2>, 220 <0x20b2>, 221 <0x20c2>; 222 }; 223 }; 224 225 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 226 usdhc0-100mhz-grp0 { 227 pinmux = <0x2e1>, 228 <0x381>; 229 output-enable; 230 bias-pull-down; 231 slew-rate = <150>; 232 }; 233 234 usdhc0-100mhz-grp1 { 235 pinmux = <0x2f1>, 236 <0x301>, 237 <0x311>, 238 <0x321>, 239 <0x331>, 240 <0x341>, 241 <0x351>, 242 <0x361>, 243 <0x371>; 244 output-enable; 245 input-enable; 246 bias-pull-up; 247 slew-rate = <150>; 248 }; 249 250 usdhc0-100mhz-grp2 { 251 pinmux = <0x391>; 252 output-enable; 253 slew-rate = <150>; 254 }; 255 256 usdhc0-100mhz-grp3 { 257 pinmux = <0x3a0>; 258 input-enable; 259 slew-rate = <150>; 260 }; 261 262 usdhc0-100mhz-grp4 { 263 pinmux = <0x2032>, 264 <0x2042>, 265 <0x2052>, 266 <0x2062>, 267 <0x2072>, 268 <0x2082>, 269 <0x2092>, 270 <0x20a2>, 271 <0x20b2>, 272 <0x20c2>; 273 }; 274 }; 275 276 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 277 usdhc0-200mhz-grp0 { 278 pinmux = <0x2e1>, 279 <0x381>; 280 output-enable; 281 bias-pull-down; 282 slew-rate = <208>; 283 }; 284 285 usdhc0-200mhz-grp1 { 286 pinmux = <0x2f1>, 287 <0x301>, 288 <0x311>, 289 <0x321>, 290 <0x331>, 291 <0x341>, 292 <0x351>, 293 <0x361>, 294 <0x371>; 295 output-enable; 296 input-enable; 297 bias-pull-up; 298 slew-rate = <208>; 299 }; 300 301 usdhc0-200mhz-grp2 { 302 pinmux = <0x391>; 303 output-enable; 304 slew-rate = <208>; 305 }; 306 307 usdhc0-200mhz-grp3 { 308 pinmux = <0x3a0>; 309 input-enable; 310 slew-rate = <208>; 311 }; 312 313 usdhc0-200mhz-grp4 { 314 pinmux = <0x2032>, 315 <0x2042>, 316 <0x2052>, 317 <0x2062>, 318 <0x2072>, 319 <0x2082>, 320 <0x2092>, 321 <0x20a2>, 322 <0x20b2>, 323 <0x20c2>; 324 }; 325 }; 326 }; 327 328 edma0: dma-controller@40144000 { 329 compatible = "nxp,s32g2-edma"; 330 reg = <0x40144000 0x24000>, 331 <0x4012c000 0x3000>, 332 <0x40130000 0x3000>; 333 #dma-cells = <2>; 334 dma-channels = <32>; 335 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-names = "tx-0-15", 339 "tx-16-31", 340 "err"; 341 clocks = <&clks 63>, <&clks 64>; 342 clock-names = "dmamux0", "dmamux1"; 343 }; 344 345 can0: can@401b4000 { 346 compatible = "nxp,s32g2-flexcan"; 347 reg = <0x401b4000 0xa000>; 348 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 352 interrupt-names = "mb-0", "state", "berr", "mb-1"; 353 clocks = <&clks 9>, <&clks 11>; 354 clock-names = "ipg", "per"; 355 status = "disabled"; 356 }; 357 358 can1: can@401be000 { 359 compatible = "nxp,s32g2-flexcan"; 360 reg = <0x401be000 0xa000>; 361 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "mb-0", "state", "berr", "mb-1"; 366 clocks = <&clks 9>, <&clks 11>; 367 clock-names = "ipg", "per"; 368 status = "disabled"; 369 }; 370 371 uart0: serial@401c8000 { 372 compatible = "nxp,s32g2-linflexuart", 373 "fsl,s32v234-linflexuart"; 374 reg = <0x401c8000 0x3000>; 375 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 376 status = "disabled"; 377 }; 378 379 uart1: serial@401cc000 { 380 compatible = "nxp,s32g2-linflexuart", 381 "fsl,s32v234-linflexuart"; 382 reg = <0x401cc000 0x3000>; 383 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 384 status = "disabled"; 385 }; 386 387 usbmisc: usbmisc@44064200 { 388 #index-cells = <1>; 389 compatible = "nxp,s32g2-usbmisc"; 390 reg = <0x44064200 0x200>; 391 }; 392 393 usbotg: usb@44064000 { 394 compatible = "nxp,s32g2-usb"; 395 reg = <0x44064000 0x200>; 396 interrupt-parent = <&gic>; 397 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ 398 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ 399 clocks = <&clks 94>, <&clks 95>; 400 fsl,usbmisc = <&usbmisc 0>; 401 ahb-burst-config = <0x3>; 402 tx-burst-size-dword = <0x10>; 403 rx-burst-size-dword = <0x10>; 404 phy_type = "ulpi"; 405 dr_mode = "host"; 406 maximum-speed = "high-speed"; 407 status = "disabled"; 408 }; 409 410 spi0: spi@401d4000 { 411 compatible = "nxp,s32g2-dspi"; 412 reg = <0x401d4000 0x1000>; 413 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clks 26>; 415 clock-names = "dspi"; 416 spi-num-chipselects = <8>; 417 bus-num = <0>; 418 dmas = <&edma0 0 7>, <&edma0 0 8>; 419 dma-names = "tx", "rx"; 420 status = "disabled"; 421 }; 422 423 spi1: spi@401d8000 { 424 compatible = "nxp,s32g2-dspi"; 425 reg = <0x401d8000 0x1000>; 426 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clks 26>; 428 clock-names = "dspi"; 429 spi-num-chipselects = <5>; 430 bus-num = <1>; 431 dmas = <&edma0 0 10>, <&edma0 0 11>; 432 dma-names = "tx", "rx"; 433 status = "disabled"; 434 }; 435 436 spi2: spi@401dc000 { 437 compatible = "nxp,s32g2-dspi"; 438 reg = <0x401dc000 0x1000>; 439 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clks 26>; 441 clock-names = "dspi"; 442 spi-num-chipselects = <5>; 443 bus-num = <2>; 444 dmas = <&edma0 0 13>, <&edma0 0 14>; 445 dma-names = "tx", "rx"; 446 status = "disabled"; 447 }; 448 449 i2c0: i2c@401e4000 { 450 compatible = "nxp,s32g2-i2c"; 451 reg = <0x401e4000 0x1000>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&clks 40>; 456 clock-names = "ipg"; 457 status = "disabled"; 458 }; 459 460 i2c1: i2c@401e8000 { 461 compatible = "nxp,s32g2-i2c"; 462 reg = <0x401e8000 0x1000>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clks 40>; 467 clock-names = "ipg"; 468 status = "disabled"; 469 }; 470 471 i2c2: i2c@401ec000 { 472 compatible = "nxp,s32g2-i2c"; 473 reg = <0x401ec000 0x1000>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clks 40>; 478 clock-names = "ipg"; 479 status = "disabled"; 480 }; 481 482 edma1: dma-controller@40244000 { 483 compatible = "nxp,s32g2-edma"; 484 reg = <0x40244000 0x24000>, 485 <0x4022c000 0x3000>, 486 <0x40230000 0x3000>; 487 #dma-cells = <2>; 488 dma-channels = <32>; 489 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "tx-0-15", 493 "tx-16-31", 494 "err"; 495 clocks = <&clks 63>, <&clks 64>; 496 clock-names = "dmamux0", "dmamux1"; 497 }; 498 499 can2: can@402a8000 { 500 compatible = "nxp,s32g2-flexcan"; 501 reg = <0x402a8000 0xa000>; 502 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "mb-0", "state", "berr", "mb-1"; 507 clocks = <&clks 9>, <&clks 11>; 508 clock-names = "ipg", "per"; 509 status = "disabled"; 510 }; 511 512 can3: can@402b2000 { 513 compatible = "nxp,s32g2-flexcan"; 514 reg = <0x402b2000 0xa000>; 515 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "mb-0", "state", "berr", "mb-1"; 520 clocks = <&clks 9>, <&clks 11>; 521 clock-names = "ipg", "per"; 522 status = "disabled"; 523 }; 524 525 uart2: serial@402bc000 { 526 compatible = "nxp,s32g2-linflexuart", 527 "fsl,s32v234-linflexuart"; 528 reg = <0x402bc000 0x3000>; 529 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 530 status = "disabled"; 531 }; 532 533 spi3: spi@402c8000 { 534 compatible = "nxp,s32g2-dspi"; 535 reg = <0x402c8000 0x1000>; 536 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&clks 26>; 538 clock-names = "dspi"; 539 spi-num-chipselects = <5>; 540 bus-num = <3>; 541 dmas = <&edma0 1 7>, <&edma0 1 8>; 542 dma-names = "tx", "rx"; 543 status = "disabled"; 544 }; 545 546 spi4: spi@402cc000 { 547 compatible = "nxp,s32g2-dspi"; 548 reg = <0x402cc000 0x1000>; 549 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clks 26>; 551 clock-names = "dspi"; 552 spi-num-chipselects = <5>; 553 bus-num = <4>; 554 dmas = <&edma0 1 10>, <&edma0 1 11>; 555 dma-names = "tx", "rx"; 556 status = "disabled"; 557 }; 558 559 spi5: spi@402d0000 { 560 compatible = "nxp,s32g2-dspi"; 561 reg = <0x402d0000 0x1000>; 562 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&clks 26>; 564 clock-names = "dspi"; 565 spi-num-chipselects = <5>; 566 bus-num = <5>; 567 dmas = <&edma0 1 13>, <&edma0 1 14>; 568 dma-names = "tx", "rx"; 569 status = "disabled"; 570 }; 571 572 i2c3: i2c@402d8000 { 573 compatible = "nxp,s32g2-i2c"; 574 reg = <0x402d8000 0x1000>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&clks 40>; 579 clock-names = "ipg"; 580 status = "disabled"; 581 }; 582 583 i2c4: i2c@402dc000 { 584 compatible = "nxp,s32g2-i2c"; 585 reg = <0x402dc000 0x1000>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clks 40>; 590 clock-names = "ipg"; 591 status = "disabled"; 592 }; 593 594 usdhc0: mmc@402f0000 { 595 compatible = "nxp,s32g2-usdhc"; 596 reg = <0x402f0000 0x1000>; 597 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&clks 32>, <&clks 31>, <&clks 33>; 599 clock-names = "ipg", "ahb", "per"; 600 bus-width = <8>; 601 status = "disabled"; 602 }; 603 604 gic: interrupt-controller@50800000 { 605 compatible = "arm,gic-v3"; 606 reg = <0x50800000 0x10000>, 607 <0x50880000 0x80000>, 608 <0x50400000 0x2000>, 609 <0x50410000 0x2000>, 610 <0x50420000 0x2000>; 611 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-controller; 613 #interrupt-cells = <3>; 614 }; 615 }; 616}; 617