xref: /linux/arch/arm64/boot/dts/freescale/mba8xx.dtsi (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
2/*
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/net/ti-dp83867.h>
11
12/ {
13	adc {
14		compatible = "iio-hwmon";
15		io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
16	};
17
18	aliases {
19		rtc0 = &pcf85063;
20		rtc1 = &rtc;
21	};
22
23	backlight_lvds: backlight-lvds {
24		compatible = "pwm-backlight";
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_bl_lvds>;
27		pwms = <&adma_pwm 0 5000000 0>;
28		brightness-levels = <0 4 8 16 32 64 128 255>;
29		default-brightness-level = <7>;
30		power-supply = <&reg_12v0>;
31		enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
32		status = "disabled";
33	};
34
35	chosen {
36		stdout-path = &lpuart1;
37	};
38
39	/* Non-controllable PCIe reference clock generator */
40	pcie_refclk: clock-pcie-ref {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <100000000>;
44	};
45
46	gpio-keys {
47		compatible = "gpio-keys";
48		pinctrl-names = "default";
49		pinctrl-0 = <&pinctrl_gpiobuttons>;
50		autorepeat;
51
52		switch-a {
53			label = "switcha";
54			linux,code = <BTN_0>;
55			gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
56		};
57
58		switch-b {
59			label = "switchb";
60			linux,code = <BTN_1>;
61			gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
62		};
63	};
64
65	gpio-leds {
66		compatible = "gpio-leds";
67
68		led1 {
69			color = <LED_COLOR_ID_GREEN>;
70			function = LED_FUNCTION_STATUS;
71			gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
72			linux,default-trigger = "default-on";
73		};
74
75		led2 {
76			color = <LED_COLOR_ID_GREEN>;
77			function = LED_FUNCTION_HEARTBEAT;
78			gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
79			linux,default-trigger = "heartbeat";
80		};
81	};
82
83	/* TODO LVDS panels */
84
85	reg_12v0: regulator-12v0 {
86		compatible = "regulator-fixed";
87		regulator-name = "V_12V";
88		regulator-min-microvolt = <12000000>;
89		regulator-max-microvolt = <12000000>;
90		gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
91		enable-active-high;
92	};
93
94	reg_pcie_1v5: regulator-pcie-1v5 {
95		compatible = "regulator-fixed";
96		regulator-name = "MBA8XX_PCIE_1V5";
97		pinctrl-names = "default";
98		pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
99		regulator-min-microvolt = <1500000>;
100		regulator-max-microvolt = <1500000>;
101		gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
102		startup-delay-us = <1000>;
103		enable-active-high;
104	};
105
106	reg_pcie_3v3: regulator-pcie-3v3 {
107		compatible = "regulator-fixed";
108		regulator-name = "MBA8XX_PCIE_3V3";
109		pinctrl-names = "default";
110		pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
114		startup-delay-us = <1000>;
115		enable-active-high;
116		regulator-always-on;
117	};
118
119	reg_3v3_mb: regulator-usdhc2-vmmc {
120		compatible = "regulator-fixed";
121		regulator-name = "V_3V3_MB";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124	};
125
126	sound {
127		compatible = "fsl,imx-audio-tlv320aic32x4";
128		model = "tqm-tlv320aic32";
129		audio-codec = <&tlv320aic3x04>;
130		ssi-controller = <&sai1>;
131	};
132};
133
134&adc0 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_adc0>;
137	vref-supply = <&reg_1v8>;
138	#io-channel-cells = <1>;
139	status = "okay";
140};
141
142&adma_pwm {
143	pinctrl-names = "default";
144	pinctrl-0 = <&pinctrl_admapwm>;
145};
146
147&fec1 {
148	pinctrl-names = "default";
149	pinctrl-0 = <&pinctrl_fec1>;
150	phy-mode = "rgmii-id";
151	phy-handle = <&ethphy0>;
152	status = "okay";
153
154	mdio {
155		#address-cells = <1>;
156		#size-cells = <0>;
157
158		ethphy0: ethernet-phy@0 {
159			compatible = "ethernet-phy-ieee802.3-c22";
160			reg = <0>;
161			pinctrl-names = "default";
162			pinctrl-0 = <&pinctrl_ethphy0>;
163			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
164			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
165			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
166			ti,dp83867-rxctrl-strap-quirk;
167			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
168			reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
169			reset-assert-us = <500000>;
170			reset-deassert-us = <50000>;
171			enet-phy-lane-no-swap;
172			interrupt-parent = <&lsio_gpio3>;
173			interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
174		};
175
176		ethphy3: ethernet-phy@3 {
177			compatible = "ethernet-phy-ieee802.3-c22";
178			reg = <3>;
179			pinctrl-names = "default";
180			pinctrl-0 = <&pinctrl_ethphy3>;
181			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
182			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
183			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
184			ti,dp83867-rxctrl-strap-quirk;
185			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
186			reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
187			reset-assert-us = <500000>;
188			reset-deassert-us = <50000>;
189			enet-phy-lane-no-swap;
190			interrupt-parent = <&lsio_gpio3>;
191			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
192		};
193	};
194};
195
196&fec2 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_fec2>;
199	phy-mode = "rgmii-id";
200	phy-handle = <&ethphy3>;
201	status = "okay";
202};
203
204&flexcan1 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_can0>;
207	xceiver-supply = <&reg_3v3>;
208	status = "okay";
209};
210
211&flexcan2 {
212	pinctrl-names = "default";
213	pinctrl-0 = <&pinctrl_can1>;
214	xceiver-supply = <&reg_3v3>;
215	status = "okay";
216};
217
218&hsio_phy {
219	fsl,hsio-cfg = "pciea-x2-pcieb";
220	fsl,refclk-pad-mode = "input";
221	status = "okay";
222};
223
224&i2c1 {
225	tlv320aic3x04: audio-codec@18 {
226		compatible = "ti,tlv320aic32x4";
227		reg = <0x18>;
228		clocks = <&mclkout0_lpcg 0>;
229		clock-names = "mclk";
230		iov-supply = <&reg_1v8>;
231		ldoin-supply = <&reg_3v3>;
232	};
233
234	se97b_1c: temperature-sensor@1c {
235		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
236		reg = <0x1c>;
237	};
238
239	at24c02_54: eeprom@54 {
240		compatible = "nxp,se97b", "atmel,24c02";
241		reg = <0x54>;
242		pagesize = <16>;
243		vcc-supply = <&reg_3v3>;
244	};
245
246	expander: gpio@70 {
247		compatible = "nxp,pca9538";
248		reg = <0x70>;
249		pinctrl-names = "default";
250		pinctrl-0 = <&pinctrl_pca9538>;
251		gpio-controller;
252		#gpio-cells = <2>;
253		interrupt-parent = <&lsio_gpio4>;
254		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
255		interrupt-controller;
256		#interrupt-cells = <2>;
257		vcc-supply = <&reg_1v8>;
258
259		gpio-line-names = "", "LED_A",
260				  "LED_B", "",
261				  "DSI_EN", "USB_RESET#",
262				  "V_12V_EN", "PCIE_DIS#";
263	};
264};
265
266&i2c2 {
267	clock-frequency = <100000>;
268	pinctrl-names = "default", "gpio";
269	pinctrl-0 = <&pinctrl_lpi2c2>;
270	pinctrl-1 = <&pinctrl_lpi2c2gpio>;
271	scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
272	sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
273	status = "okay";
274};
275
276/* TODO LDB */
277
278&lpspi1 {
279	pinctrl-names = "default";
280	pinctrl-0 = <&pinctrl_spi1>;
281	cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
282	status = "okay";
283};
284
285&lpspi2 {
286	pinctrl-names = "default";
287	pinctrl-0 = <&pinctrl_spi2>;
288	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
289	status = "okay";
290};
291
292&lpspi3 {
293	pinctrl-names = "default";
294	pinctrl-0 = <&pinctrl_spi3>;
295	num-cs = <2>;
296	cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
297	status = "okay";
298};
299
300&lpuart1 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_lpuart1>;
303	status = "okay";
304};
305
306&lpuart3 {
307	pinctrl-names = "default";
308	pinctrl-0 = <&pinctrl_lpuart3>;
309	status = "okay";
310};
311
312&lsio_gpio3 {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_lsgpio3>;
315	gpio-line-names = "", "", "", "",
316			  "", "", "", "",
317			  "", "", "", "",
318			  "", "", "", "X4_15",
319			  "", "", "", "",
320			  "", "", "", "",
321			  "", "", "", "",
322			  "", "", "", "";
323};
324
325&pcieb {
326	phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
327	phy-names = "pcie-phy";
328	pinctrl-0 = <&pinctrl_pcieb>;
329	pinctrl-names = "default";
330	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
331	vpcie-supply = <&reg_pcie_1v5>;
332	status = "okay";
333};
334
335&sai1 {
336	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
337			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
338			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
339			  <&sai1_lpcg 0>;
340	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
341	pinctrl-names = "default";
342	pinctrl-0 = <&pinctrl_sai1>;
343	status = "okay";
344};
345
346&usbotg1 {
347	pinctrl-names = "default";
348	pinctrl-0 = <&pinctrl_usbotg1>;
349	srp-disable;
350	hnp-disable;
351	adp-disable;
352	power-active-high;
353	over-current-active-low;
354	dr_mode = "otg";
355	status = "okay";
356};
357
358&usbotg3 {
359	status = "okay";
360};
361
362&usbotg3_cdns3 {
363	dr_mode = "host";
364	status = "okay";
365};
366
367&usbphy1 {
368	status = "okay";
369};
370
371&usb3_phy {
372	status = "okay";
373};
374
375&usdhc2 {
376	pinctrl-names = "default", "state_100mhz", "state_200mhz";
377	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
378	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
379	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
380	bus-width = <4>;
381	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
382	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
383	vmmc-supply = <&reg_3v3_mb>;
384	no-1-8-v;
385	no-sdio;
386	no-mmc;
387	status = "okay";
388};
389
390&iomuxc {
391	pinctrl_adc0: adc0grp {
392		fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0	0x02000060>,
393			   <IMX8QXP_ADC_IN1_ADMA_ADC_IN1	0x02000060>,
394			   <IMX8QXP_ADC_IN2_ADMA_ADC_IN2	0x02000060>,
395			   <IMX8QXP_ADC_IN3_ADMA_ADC_IN3	0x02000060>;
396	};
397
398	pinctrl_admapwm: admapwmgrp {
399		fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT	0x00000021>;
400	};
401
402	pinctrl_bl_lvds: bllvdsgrp {
403		fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30	0x00000021>;
404	};
405
406	pinctrl_can0: can0grp {
407		fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX		0x00000021>,
408			   <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX		0x00000021>;
409	};
410
411	pinctrl_can1: can1grp {
412		fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX		0x00000021>,
413			   <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX		0x00000021>;
414	};
415
416	pinctrl_ethphy0: ethphy0grp {
417		fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02		0x00000040>,
418			   <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x00000040>;
419	};
420
421	pinctrl_ethphy3: ethphy3grp {
422		fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x00000040>,
423			   <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x00000040>;
424	};
425
426	pinctrl_fec1: fec1grp {
427		fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000041>,
428			   <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000041>,
429			   <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000040>,
430			   <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000040>,
431			   <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000040>,
432			   <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000040>,
433			   <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000040>,
434			   <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000040>,
435			   <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000040>,
436			   <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000040>,
437			   <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000040>,
438			   <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000040>,
439			   <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000040>,
440			   <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000040>;
441	};
442
443	pinctrl_fec2: fec2grp {
444		fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000040>,
445			   <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000040>,
446			   <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0		0x00000040>,
447			   <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1		0x00000040>,
448			   <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000040>,
449			   <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000040>,
450			   <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000040>,
451			   <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000040>,
452			   <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000040>,
453			   <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1		0x00000040>,
454			   <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2		0x00000040>,
455			   <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000040>;
456	};
457
458	pinctrl_gpiobuttons: gpiobuttonsgrp {
459		fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13	0x00000020>,
460			   <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14	0x00000020>;
461	};
462
463	pinctrl_lpi2c2: lpi2c2grp {
464		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL	0x06000021>,
465			   <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA	0x06000021>;
466	};
467
468	pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
469		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31	0x06000021>,
470			   <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x06000021>;
471	};
472
473	pinctrl_lpuart1: lpuart1grp {
474		fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX	0x06000020>,
475			   <IMX8QXP_UART1_TX_ADMA_UART1_TX	0x06000020>;
476	};
477
478	pinctrl_lpuart3: lpuart3grp {
479		fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020>,
480			   <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020>;
481	};
482
483	pinctrl_lsgpio3: lsgpio3grp {
484		fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000021>;
485	};
486
487	pinctrl_pca9538: pca9538grp {
488		fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000020>;
489	};
490
491	pinctrl_pcieb: pciebgrp {
492		fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000041>,
493			   <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B	0x06000041>,
494			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000041>;
495	};
496
497	pinctrl_reg_pcie_1v5: regpcie1v5grp {
498		fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30	0x00000021>;
499	};
500
501	pinctrl_reg_pcie_3v3: regpcie3v3grp {
502		fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31	0x00000021>;
503	};
504
505	pinctrl_sai1: sai1grp {
506		fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x06000041>,
507			   <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC		0x06000041>,
508			   <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS		0x06000041>,
509			   <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD		0x06000041>,
510			   <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD		0x06000041>;
511	};
512
513	pinctrl_spi1: spi1grp {
514		fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI	0x00000041>,
515			   <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO	0x00000041>,
516			   <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK	0x00000041>,
517			   <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27	0x00000021>,
518			   <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29	0x00000021>;
519	};
520
521	pinctrl_spi2: spi2grp {
522		fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK	0x00000041>,
523			   <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI	0x00000041>,
524			   <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO	0x00000041>,
525			   <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00	0x00000021>;
526	};
527
528	pinctrl_spi3: spi3grp {
529		fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK	0x00000041>,
530			   <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI	0x00000041>,
531			   <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO	0x00000041>,
532			   <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16	0x00000021>,
533			   <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1	0x00000021>;
534	};
535
536	pinctrl_usbotg1: usbotg1grp {
537		fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR	0x00000021>,
538			   <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC	0x00000021>;
539	};
540
541	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
542		fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021>,
543			   <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x00000021>;
544	};
545
546	pinctrl_usdhc2: usdhc2grp {
547		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041>,
548			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021>,
549			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021>,
550			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021>,
551			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021>,
552			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021>,
553			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021>;
554	};
555
556	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
557		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040>,
558			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020>,
559			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020>,
560			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020>,
561			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020>,
562			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020>,
563			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020>;
564	};
565
566	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
567		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040>,
568			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020>,
569			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020>,
570			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020>,
571			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020>,
572			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020>,
573			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020>;
574	};
575};
576