1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "imx95-clock.h" 12#include "imx95-pinfunc.h" 13#include "imx95-power.h" 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 A55_0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a55"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 #cooling-cells = <2>; 30 power-domains = <&scmi_perf IMX95_PERF_A55>; 31 power-domain-names = "perf"; 32 i-cache-size = <32768>; 33 i-cache-line-size = <64>; 34 i-cache-sets = <128>; 35 d-cache-size = <32768>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 next-level-cache = <&l2_cache_l0>; 39 }; 40 41 A55_1: cpu@100 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a55"; 44 reg = <0x100>; 45 enable-method = "psci"; 46 #cooling-cells = <2>; 47 power-domains = <&scmi_perf IMX95_PERF_A55>; 48 power-domain-names = "perf"; 49 i-cache-size = <32768>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <128>; 52 d-cache-size = <32768>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_cache_l1>; 56 }; 57 58 A55_2: cpu@200 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x200>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; 64 power-domains = <&scmi_perf IMX95_PERF_A55>; 65 power-domain-names = "perf"; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l2>; 73 }; 74 75 A55_3: cpu@300 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x300>; 79 enable-method = "psci"; 80 #cooling-cells = <2>; 81 power-domains = <&scmi_perf IMX95_PERF_A55>; 82 power-domain-names = "perf"; 83 i-cache-size = <32768>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <128>; 86 d-cache-size = <32768>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_cache_l3>; 90 }; 91 92 A55_4: cpu@400 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a55"; 95 reg = <0x400>; 96 power-domains = <&scmi_perf IMX95_PERF_A55>; 97 power-domain-names = "perf"; 98 enable-method = "psci"; 99 #cooling-cells = <2>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l4>; 107 }; 108 109 A55_5: cpu@500 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x500>; 113 power-domains = <&scmi_perf IMX95_PERF_A55>; 114 power-domain-names = "perf"; 115 enable-method = "psci"; 116 #cooling-cells = <2>; 117 i-cache-size = <32768>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <128>; 120 d-cache-size = <32768>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 next-level-cache = <&l2_cache_l5>; 124 }; 125 126 l2_cache_l0: l2-cache-l0 { 127 compatible = "cache"; 128 cache-size = <65536>; 129 cache-line-size = <64>; 130 cache-sets = <256>; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_cache>; 134 }; 135 136 l2_cache_l1: l2-cache-l1 { 137 compatible = "cache"; 138 cache-size = <65536>; 139 cache-line-size = <64>; 140 cache-sets = <256>; 141 cache-level = <2>; 142 cache-unified; 143 next-level-cache = <&l3_cache>; 144 }; 145 146 l2_cache_l2: l2-cache-l2 { 147 compatible = "cache"; 148 cache-size = <65536>; 149 cache-line-size = <64>; 150 cache-sets = <256>; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_cache>; 154 }; 155 156 l2_cache_l3: l2-cache-l3 { 157 compatible = "cache"; 158 cache-size = <65536>; 159 cache-line-size = <64>; 160 cache-sets = <256>; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&l3_cache>; 164 }; 165 166 l2_cache_l4: l2-cache-l4 { 167 compatible = "cache"; 168 cache-size = <65536>; 169 cache-line-size = <64>; 170 cache-sets = <256>; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_cache>; 174 }; 175 176 l2_cache_l5: l2-cache-l5 { 177 compatible = "cache"; 178 cache-size = <65536>; 179 cache-line-size = <64>; 180 cache-sets = <256>; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&l3_cache>; 184 }; 185 186 l3_cache: l3-cache { 187 compatible = "cache"; 188 cache-size = <524288>; 189 cache-line-size = <64>; 190 cache-sets = <512>; 191 cache-level = <3>; 192 cache-unified; 193 }; 194 195 cpu-map { 196 cluster0 { 197 core0 { 198 cpu = <&A55_0>; 199 }; 200 201 core1 { 202 cpu = <&A55_1>; 203 }; 204 205 core2 { 206 cpu = <&A55_2>; 207 }; 208 209 core3 { 210 cpu = <&A55_3>; 211 }; 212 213 core4 { 214 cpu = <&A55_4>; 215 }; 216 217 core5 { 218 cpu = <&A55_5>; 219 }; 220 }; 221 }; 222 }; 223 224 clk_ext1: clock-ext1 { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <133000000>; 228 clock-output-names = "clk_ext1"; 229 }; 230 231 sai1_mclk: clock-sai-mclk1 { 232 compatible = "fixed-clock"; 233 #clock-cells = <0>; 234 clock-frequency= <0>; 235 clock-output-names = "sai1_mclk"; 236 }; 237 238 sai2_mclk: clock-sai-mclk2 { 239 compatible = "fixed-clock"; 240 #clock-cells = <0>; 241 clock-frequency= <0>; 242 clock-output-names = "sai2_mclk"; 243 }; 244 245 sai3_mclk: clock-sai-mclk3 { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency= <0>; 249 clock-output-names = "sai3_mclk"; 250 }; 251 252 sai4_mclk: clock-sai-mclk4 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency= <0>; 256 clock-output-names = "sai4_mclk"; 257 }; 258 259 sai5_mclk: clock-sai-mclk5 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency= <0>; 263 clock-output-names = "sai5_mclk"; 264 }; 265 266 osc_24m: clock-24m { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 clock-frequency = <24000000>; 270 clock-output-names = "osc_24m"; 271 }; 272 273 sram1: sram@204c0000 { 274 compatible = "mmio-sram"; 275 reg = <0x0 0x204c0000 0x0 0x18000>; 276 ranges = <0x0 0x0 0x204c0000 0x18000>; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 }; 280 281 firmware { 282 scmi { 283 compatible = "arm,scmi"; 284 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; 285 shmem = <&scmi_buf0>, <&scmi_buf1>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 scmi_devpd: protocol@11 { 290 reg = <0x11>; 291 #power-domain-cells = <1>; 292 }; 293 294 scmi_perf: protocol@13 { 295 reg = <0x13>; 296 #power-domain-cells = <1>; 297 }; 298 299 scmi_clk: protocol@14 { 300 reg = <0x14>; 301 #clock-cells = <1>; 302 }; 303 304 scmi_sensor: protocol@15 { 305 reg = <0x15>; 306 #thermal-sensor-cells = <1>; 307 }; 308 309 scmi_iomuxc: protocol@19 { 310 reg = <0x19>; 311 }; 312 313 }; 314 }; 315 316 pmu { 317 compatible = "arm,cortex-a55-pmu"; 318 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 319 }; 320 321 thermal-zones { 322 a55-thermal { 323 polling-delay-passive = <250>; 324 polling-delay = <2000>; 325 thermal-sensors = <&scmi_sensor 1>; 326 327 trips { 328 cpu_alert0: trip0 { 329 temperature = <85000>; 330 hysteresis = <2000>; 331 type = "passive"; 332 }; 333 334 cpu_crit0: trip1 { 335 temperature = <95000>; 336 hysteresis = <2000>; 337 type = "critical"; 338 }; 339 }; 340 341 cooling-maps { 342 map0 { 343 trip = <&cpu_alert0>; 344 cooling-device = 345 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 346 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 347 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 348 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 349 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 351 }; 352 }; 353 }; 354 }; 355 356 psci { 357 compatible = "arm,psci-1.0"; 358 method = "smc"; 359 }; 360 361 timer { 362 compatible = "arm,armv8-timer"; 363 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 364 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 365 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 366 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 367 clock-frequency = <24000000>; 368 arm,no-tick-in-suspend; 369 interrupt-parent = <&gic>; 370 }; 371 372 gic: interrupt-controller@48000000 { 373 compatible = "arm,gic-v3"; 374 reg = <0 0x48000000 0 0x10000>, 375 <0 0x48060000 0 0xc0000>; 376 #address-cells = <2>; 377 #size-cells = <2>; 378 #interrupt-cells = <3>; 379 interrupt-controller; 380 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-parent = <&gic>; 382 dma-noncoherent; 383 ranges; 384 385 its: msi-controller@48040000 { 386 compatible = "arm,gic-v3-its"; 387 reg = <0 0x48040000 0 0x20000>; 388 msi-controller; 389 #msi-cells = <1>; 390 dma-noncoherent; 391 }; 392 }; 393 394 soc { 395 compatible = "simple-bus"; 396 #address-cells = <2>; 397 #size-cells = <2>; 398 ranges; 399 400 aips2: bus@42000000 { 401 compatible = "fsl,aips-bus", "simple-bus"; 402 reg = <0x0 0x42000000 0x0 0x800000>; 403 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 404 <0x28000000 0x0 0x28000000 0x10000000>; 405 #address-cells = <1>; 406 #size-cells = <1>; 407 408 mu7: mailbox@42430000 { 409 compatible = "fsl,imx95-mu"; 410 reg = <0x42430000 0x10000>; 411 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 413 #mbox-cells = <2>; 414 status = "disabled"; 415 }; 416 417 wdog3: watchdog@42490000 { 418 compatible = "fsl,imx93-wdt"; 419 reg = <0x42490000 0x10000>; 420 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 422 timeout-sec = <40>; 423 status = "disabled"; 424 }; 425 426 tpm3: pwm@424e0000 { 427 compatible = "fsl,imx7ulp-pwm"; 428 reg = <0x424e0000 0x1000>; 429 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 430 #pwm-cells = <3>; 431 status = "disabled"; 432 }; 433 434 tpm4: pwm@424f0000 { 435 compatible = "fsl,imx7ulp-pwm"; 436 reg = <0x424f0000 0x1000>; 437 clocks = <&scmi_clk IMX95_CLK_TPM4>; 438 #pwm-cells = <3>; 439 status = "disabled"; 440 }; 441 442 tpm5: pwm@42500000 { 443 compatible = "fsl,imx7ulp-pwm"; 444 reg = <0x42500000 0x1000>; 445 clocks = <&scmi_clk IMX95_CLK_TPM5>; 446 #pwm-cells = <3>; 447 status = "disabled"; 448 }; 449 450 tpm6: pwm@42510000 { 451 compatible = "fsl,imx7ulp-pwm"; 452 reg = <0x42510000 0x1000>; 453 clocks = <&scmi_clk IMX95_CLK_TPM6>; 454 #pwm-cells = <3>; 455 status = "disabled"; 456 }; 457 458 lpi2c3: i2c@42530000 { 459 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 460 reg = <0x42530000 0x10000>; 461 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 463 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 464 clock-names = "per", "ipg"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 lpi2c4: i2c@42540000 { 471 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 472 reg = <0x42540000 0x10000>; 473 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 475 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 476 clock-names = "per", "ipg"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 lpspi3: spi@42550000 { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 486 reg = <0x42550000 0x10000>; 487 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 489 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 490 clock-names = "per", "ipg"; 491 status = "disabled"; 492 }; 493 494 lpspi4: spi@42560000 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 498 reg = <0x42560000 0x10000>; 499 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 501 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 502 clock-names = "per", "ipg"; 503 status = "disabled"; 504 }; 505 506 lpuart3: serial@42570000 { 507 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 508 "fsl,imx7ulp-lpuart"; 509 reg = <0x42570000 0x1000>; 510 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 512 clock-names = "ipg"; 513 status = "disabled"; 514 }; 515 516 lpuart4: serial@42580000 { 517 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 518 "fsl,imx7ulp-lpuart"; 519 reg = <0x42580000 0x1000>; 520 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 522 clock-names = "ipg"; 523 status = "disabled"; 524 }; 525 526 lpuart5: serial@42590000 { 527 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 528 "fsl,imx7ulp-lpuart"; 529 reg = <0x42590000 0x1000>; 530 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 532 clock-names = "ipg"; 533 status = "disabled"; 534 }; 535 536 lpuart6: serial@425a0000 { 537 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 538 "fsl,imx7ulp-lpuart"; 539 reg = <0x425a0000 0x1000>; 540 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 542 clock-names = "ipg"; 543 status = "disabled"; 544 }; 545 546 lpuart7: serial@42690000 { 547 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 548 "fsl,imx7ulp-lpuart"; 549 reg = <0x42690000 0x1000>; 550 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 552 clock-names = "ipg"; 553 status = "disabled"; 554 }; 555 556 lpuart8: serial@426a0000 { 557 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 558 "fsl,imx7ulp-lpuart"; 559 reg = <0x426a0000 0x1000>; 560 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 562 clock-names = "ipg"; 563 status = "disabled"; 564 }; 565 566 lpi2c5: i2c@426b0000 { 567 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 568 reg = <0x426b0000 0x10000>; 569 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 571 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 572 clock-names = "per", "ipg"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 lpi2c6: i2c@426c0000 { 579 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 580 reg = <0x426c0000 0x10000>; 581 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 583 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 584 clock-names = "per", "ipg"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 lpi2c7: i2c@426d0000 { 591 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 592 reg = <0x426d0000 0x10000>; 593 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 595 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 596 clock-names = "per", "ipg"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 lpi2c8: i2c@426e0000 { 603 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 604 reg = <0x426e0000 0x10000>; 605 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 607 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 608 clock-names = "per", "ipg"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 lpspi5: spi@426f0000 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 618 reg = <0x426f0000 0x10000>; 619 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 621 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 622 clock-names = "per", "ipg"; 623 status = "disabled"; 624 }; 625 626 lpspi6: spi@42700000 { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 630 reg = <0x42700000 0x10000>; 631 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 633 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 634 clock-names = "per", "ipg"; 635 status = "disabled"; 636 }; 637 638 lpspi7: spi@42710000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 642 reg = <0x42710000 0x10000>; 643 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 645 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 646 clock-names = "per", "ipg"; 647 status = "disabled"; 648 }; 649 650 lpspi8: spi@42720000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 654 reg = <0x42720000 0x10000>; 655 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 657 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 658 clock-names = "per", "ipg"; 659 status = "disabled"; 660 }; 661 662 mu8: mailbox@42730000 { 663 compatible = "fsl,imx95-mu"; 664 reg = <0x42730000 0x10000>; 665 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 667 #mbox-cells = <2>; 668 status = "disabled"; 669 }; 670 }; 671 672 aips3: bus@42800000 { 673 compatible = "fsl,aips-bus", "simple-bus"; 674 reg = <0 0x42800000 0 0x800000>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges = <0x42800000 0x0 0x42800000 0x800000>; 678 679 usdhc1: mmc@42850000 { 680 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 681 reg = <0x42850000 0x10000>; 682 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 684 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 685 <&scmi_clk IMX95_CLK_USDHC1>; 686 clock-names = "ipg", "ahb", "per"; 687 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 688 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 689 assigned-clock-rates = <400000000>; 690 bus-width = <8>; 691 fsl,tuning-start-tap = <1>; 692 fsl,tuning-step= <2>; 693 status = "disabled"; 694 }; 695 696 usdhc2: mmc@42860000 { 697 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 698 reg = <0x42860000 0x10000>; 699 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 701 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 702 <&scmi_clk IMX95_CLK_USDHC2>; 703 clock-names = "ipg", "ahb", "per"; 704 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 705 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 706 assigned-clock-rates = <400000000>; 707 bus-width = <4>; 708 fsl,tuning-start-tap = <1>; 709 fsl,tuning-step= <2>; 710 status = "disabled"; 711 }; 712 713 usdhc3: mmc@428b0000 { 714 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 715 reg = <0x428b0000 0x10000>; 716 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 718 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 719 <&scmi_clk IMX95_CLK_USDHC3>; 720 clock-names = "ipg", "ahb", "per"; 721 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 722 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 723 assigned-clock-rates = <400000000>; 724 bus-width = <4>; 725 fsl,tuning-start-tap = <1>; 726 fsl,tuning-step= <2>; 727 status = "disabled"; 728 }; 729 }; 730 731 gpio2: gpio@43810000 { 732 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 733 reg = <0x0 0x43810000 0x0 0x1000>; 734 gpio-controller; 735 #gpio-cells = <2>; 736 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 741 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 742 clock-names = "gpio", "port"; 743 gpio-ranges = <&scmi_iomuxc 0 4 32>; 744 }; 745 746 gpio3: gpio@43820000 { 747 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 748 reg = <0x0 0x43820000 0x0 0x1000>; 749 gpio-controller; 750 #gpio-cells = <2>; 751 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-controller; 754 #interrupt-cells = <2>; 755 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 756 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 757 clock-names = "gpio", "port"; 758 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 759 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 760 }; 761 762 gpio4: gpio@43840000 { 763 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 764 reg = <0x0 0x43840000 0x0 0x1000>; 765 gpio-controller; 766 #gpio-cells = <2>; 767 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 772 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 773 clock-names = "gpio", "port"; 774 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 775 }; 776 777 gpio5: gpio@43850000 { 778 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 779 reg = <0x0 0x43850000 0x0 0x1000>; 780 gpio-controller; 781 #gpio-cells = <2>; 782 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 787 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 788 clock-names = "gpio", "port"; 789 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 790 }; 791 792 aips1: bus@44000000 { 793 compatible = "fsl,aips-bus", "simple-bus"; 794 reg = <0x0 0x44000000 0x0 0x800000>; 795 ranges = <0x44000000 0x0 0x44000000 0x800000>; 796 #address-cells = <1>; 797 #size-cells = <1>; 798 799 mu1: mailbox@44220000 { 800 compatible = "fsl,imx95-mu"; 801 reg = <0x44220000 0x10000>; 802 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 804 #mbox-cells = <2>; 805 status = "disabled"; 806 }; 807 808 tpm1: pwm@44310000 { 809 compatible = "fsl,imx7ulp-pwm"; 810 reg = <0x44310000 0x1000>; 811 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 812 #pwm-cells = <3>; 813 status = "disabled"; 814 }; 815 816 tpm2: pwm@44320000 { 817 compatible = "fsl,imx7ulp-pwm"; 818 reg = <0x44320000 0x1000>; 819 clocks = <&scmi_clk IMX95_CLK_TPM2>; 820 #pwm-cells = <3>; 821 status = "disabled"; 822 }; 823 824 lpi2c1: i2c@44340000 { 825 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 826 reg = <0x44340000 0x10000>; 827 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 829 <&scmi_clk IMX95_CLK_BUSAON>; 830 clock-names = "per", "ipg"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 lpi2c2: i2c@44350000 { 837 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 838 reg = <0x44350000 0x10000>; 839 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 841 <&scmi_clk IMX95_CLK_BUSAON>; 842 clock-names = "per", "ipg"; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 848 lpspi1: spi@44360000 { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 852 reg = <0x44360000 0x10000>; 853 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 855 <&scmi_clk IMX95_CLK_BUSAON>; 856 clock-names = "per", "ipg"; 857 status = "disabled"; 858 }; 859 860 lpspi2: spi@44370000 { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 864 reg = <0x44370000 0x10000>; 865 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 867 <&scmi_clk IMX95_CLK_BUSAON>; 868 clock-names = "per", "ipg"; 869 status = "disabled"; 870 }; 871 872 lpuart1: serial@44380000 { 873 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 874 "fsl,imx7ulp-lpuart"; 875 reg = <0x44380000 0x1000>; 876 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 878 clock-names = "ipg"; 879 status = "disabled"; 880 }; 881 882 lpuart2: serial@44390000 { 883 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 884 "fsl,imx7ulp-lpuart"; 885 reg = <0x44390000 0x1000>; 886 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 888 clock-names = "ipg"; 889 status = "disabled"; 890 }; 891 892 adc1: adc@44530000 { 893 compatible = "nxp,imx93-adc"; 894 reg = <0x44530000 0x10000>; 895 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&scmi_clk IMX95_CLK_ADC>; 899 clock-names = "ipg"; 900 status = "disabled"; 901 }; 902 903 mu2: mailbox@445b0000 { 904 compatible = "fsl,imx95-mu"; 905 reg = <0x445b0000 0x1000>; 906 ranges; 907 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 #mbox-cells = <2>; 911 912 sram0: sram@445b1000 { 913 compatible = "mmio-sram"; 914 reg = <0x445b1000 0x400>; 915 ranges = <0x0 0x445b1000 0x400>; 916 #address-cells = <1>; 917 #size-cells = <1>; 918 919 scmi_buf0: scmi-sram-section@0 { 920 compatible = "arm,scmi-shmem"; 921 reg = <0x0 0x80>; 922 }; 923 924 scmi_buf1: scmi-sram-section@80 { 925 compatible = "arm,scmi-shmem"; 926 reg = <0x80 0x80>; 927 }; 928 }; 929 930 }; 931 932 mu3: mailbox@445d0000 { 933 compatible = "fsl,imx95-mu"; 934 reg = <0x445d0000 0x10000>; 935 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 937 #mbox-cells = <2>; 938 status = "disabled"; 939 }; 940 941 mu4: mailbox@445f0000 { 942 compatible = "fsl,imx95-mu"; 943 reg = <0x445f0000 0x10000>; 944 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 946 #mbox-cells = <2>; 947 status = "disabled"; 948 }; 949 950 mu6: mailbox@44630000 { 951 compatible = "fsl,imx95-mu"; 952 reg = <0x44630000 0x10000>; 953 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 955 #mbox-cells = <2>; 956 status = "disabled"; 957 }; 958 }; 959 960 mailbox@47320000 { 961 compatible = "fsl,imx95-mu-v2x"; 962 reg = <0x0 0x47320000 0x0 0x10000>; 963 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 964 #mbox-cells = <2>; 965 }; 966 967 mailbox@47350000 { 968 compatible = "fsl,imx95-mu-v2x"; 969 reg = <0x0 0x47350000 0x0 0x10000>; 970 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 971 #mbox-cells = <2>; 972 }; 973 974 /* GPIO1 is under exclusive control of System Manager */ 975 gpio1: gpio@47400000 { 976 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 977 reg = <0x0 0x47400000 0x0 0x1000>; 978 gpio-controller; 979 #gpio-cells = <2>; 980 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-controller; 983 #interrupt-cells = <2>; 984 clocks = <&scmi_clk IMX95_CLK_M33>, 985 <&scmi_clk IMX95_CLK_M33>; 986 clock-names = "gpio", "port"; 987 gpio-ranges = <&scmi_iomuxc 0 112 16>; 988 status = "disabled"; 989 }; 990 991 elemu0: mailbox@47520000 { 992 compatible = "fsl,imx95-mu-ele"; 993 reg = <0x0 0x47520000 0x0 0x10000>; 994 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 995 #mbox-cells = <2>; 996 status = "disabled"; 997 }; 998 999 elemu1: mailbox@47530000 { 1000 compatible = "fsl,imx95-mu-ele"; 1001 reg = <0x0 0x47530000 0x0 0x10000>; 1002 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1003 #mbox-cells = <2>; 1004 status = "disabled"; 1005 }; 1006 1007 elemu2: mailbox@47540000 { 1008 compatible = "fsl,imx95-mu-ele"; 1009 reg = <0x0 0x47540000 0x0 0x10000>; 1010 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1011 #mbox-cells = <2>; 1012 status = "disabled"; 1013 }; 1014 1015 elemu3: mailbox@47550000 { 1016 compatible = "fsl,imx95-mu-ele"; 1017 reg = <0x0 0x47550000 0x0 0x10000>; 1018 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1019 #mbox-cells = <2>; 1020 }; 1021 1022 elemu4: mailbox@47560000 { 1023 compatible = "fsl,imx95-mu-ele"; 1024 reg = <0x0 0x47560000 0x0 0x10000>; 1025 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1026 #mbox-cells = <2>; 1027 status = "disabled"; 1028 }; 1029 1030 elemu5: mailbox@47570000 { 1031 compatible = "fsl,imx95-mu-ele"; 1032 reg = <0x0 0x47570000 0x0 0x10000>; 1033 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1034 #mbox-cells = <2>; 1035 status = "disabled"; 1036 }; 1037 1038 aips4: bus@49000000 { 1039 compatible = "fsl,aips-bus", "simple-bus"; 1040 reg = <0x0 0x49000000 0x0 0x800000>; 1041 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1042 #address-cells = <1>; 1043 #size-cells = <1>; 1044 1045 smmu: iommu@490d0000 { 1046 compatible = "arm,smmu-v3"; 1047 reg = <0x490d0000 0x100000>; 1048 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1049 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1050 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1051 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1052 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1053 #iommu-cells = <1>; 1054 status = "disabled"; 1055 }; 1056 }; 1057 1058 pcie0: pcie@4c300000 { 1059 compatible = "fsl,imx95-pcie"; 1060 reg = <0 0x4c300000 0 0x10000>, 1061 <0 0x60100000 0 0xfe00000>, 1062 <0 0x4c360000 0 0x10000>, 1063 <0 0x4c340000 0 0x2000>; 1064 reg-names = "dbi", "config", "atu", "app"; 1065 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1066 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1067 #address-cells = <3>; 1068 #size-cells = <2>; 1069 device_type = "pci"; 1070 linux,pci-domain = <0>; 1071 bus-range = <0x00 0xff>; 1072 num-lanes = <1>; 1073 num-viewport = <8>; 1074 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1075 interrupt-names = "msi"; 1076 #interrupt-cells = <1>; 1077 interrupt-map-mask = <0 0 0 0x7>; 1078 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1079 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1080 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1081 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1083 <&scmi_clk IMX95_CLK_HSIOPLL>, 1084 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1085 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1086 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1087 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1088 <&scmi_clk IMX95_CLK_HSIOPLL>, 1089 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1090 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1091 assigned-clock-parents = <0>, <0>, 1092 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1093 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1094 fsl,max-link-speed = <3>; 1095 status = "disabled"; 1096 }; 1097 1098 pcie0_ep: pcie-ep@4c300000 { 1099 compatible = "fsl,imx95-pcie-ep"; 1100 reg = <0 0x4c300000 0 0x10000>, 1101 <0 0x4c360000 0 0x1000>, 1102 <0 0x4c320000 0 0x1000>, 1103 <0 0x4c340000 0 0x2000>, 1104 <0 0x4c370000 0 0x10000>, 1105 <0x9 0 1 0>; 1106 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1107 num-lanes = <1>; 1108 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1109 interrupt-names = "dma"; 1110 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1111 <&scmi_clk IMX95_CLK_HSIOPLL>, 1112 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1113 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1114 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1115 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1116 <&scmi_clk IMX95_CLK_HSIOPLL>, 1117 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1118 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1119 assigned-clock-parents = <0>, <0>, 1120 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1121 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1122 status = "disabled"; 1123 }; 1124 1125 pcie1: pcie@4c380000 { 1126 compatible = "fsl,imx95-pcie"; 1127 reg = <0 0x4c380000 0 0x10000>, 1128 <8 0x80100000 0 0xfe00000>, 1129 <0 0x4c3e0000 0 0x10000>, 1130 <0 0x4c3c0000 0 0x2000>; 1131 reg-names = "dbi", "config", "atu", "app"; 1132 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1133 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1134 #address-cells = <3>; 1135 #size-cells = <2>; 1136 device_type = "pci"; 1137 linux,pci-domain = <1>; 1138 bus-range = <0x00 0xff>; 1139 num-lanes = <1>; 1140 num-viewport = <8>; 1141 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1142 interrupt-names = "msi"; 1143 #interrupt-cells = <1>; 1144 interrupt-map-mask = <0 0 0 0x7>; 1145 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1146 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1147 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1148 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1150 <&scmi_clk IMX95_CLK_HSIOPLL>, 1151 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1152 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1153 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1154 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1155 <&scmi_clk IMX95_CLK_HSIOPLL>, 1156 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1157 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1158 assigned-clock-parents = <0>, <0>, 1159 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1160 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1161 fsl,max-link-speed = <3>; 1162 status = "disabled"; 1163 }; 1164 1165 pcie1_ep: pcie-ep@4c380000 { 1166 compatible = "fsl,imx95-pcie-ep"; 1167 reg = <0 0x4c380000 0 0x10000>, 1168 <0 0x4c3e0000 0 0x1000>, 1169 <0 0x4c3a0000 0 0x1000>, 1170 <0 0x4c3c0000 0 0x2000>, 1171 <0 0x4c3f0000 0 0x10000>, 1172 <0xa 0 1 0>; 1173 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1174 num-lanes = <1>; 1175 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-names = "dma"; 1177 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1178 <&scmi_clk IMX95_CLK_HSIOPLL>, 1179 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1180 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1181 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1182 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1183 <&scmi_clk IMX95_CLK_HSIOPLL>, 1184 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1185 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1186 assigned-clock-parents = <0>, <0>, 1187 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1188 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1189 status = "disabled"; 1190 }; 1191 }; 1192}; 1193