1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx95-clock.h" 13#include "imx95-pinfunc.h" 14#include "imx95-power.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 idle-states { 26 entry-method = "psci"; 27 28 cpu_pd_wait: cpu-pd-wait { 29 compatible = "arm,idle-state"; 30 arm,psci-suspend-param = <0x0010033>; 31 local-timer-stop; 32 entry-latency-us = <10000>; 33 exit-latency-us = <7000>; 34 min-residency-us = <27000>; 35 wakeup-latency-us = <15000>; 36 }; 37 }; 38 39 A55_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x0>; 43 enable-method = "psci"; 44 #cooling-cells = <2>; 45 cpu-idle-states = <&cpu_pd_wait>; 46 power-domains = <&scmi_perf IMX95_PERF_A55>; 47 power-domain-names = "perf"; 48 i-cache-size = <32768>; 49 i-cache-line-size = <64>; 50 i-cache-sets = <128>; 51 d-cache-size = <32768>; 52 d-cache-line-size = <64>; 53 d-cache-sets = <128>; 54 next-level-cache = <&l2_cache_l0>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 cpu-idle-states = <&cpu_pd_wait>; 64 power-domains = <&scmi_perf IMX95_PERF_A55>; 65 power-domain-names = "perf"; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l1>; 73 }; 74 75 A55_2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x200>; 79 enable-method = "psci"; 80 #cooling-cells = <2>; 81 cpu-idle-states = <&cpu_pd_wait>; 82 power-domains = <&scmi_perf IMX95_PERF_A55>; 83 power-domain-names = "perf"; 84 i-cache-size = <32768>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <128>; 87 d-cache-size = <32768>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&l2_cache_l2>; 91 }; 92 93 A55_3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 enable-method = "psci"; 98 #cooling-cells = <2>; 99 cpu-idle-states = <&cpu_pd_wait>; 100 power-domains = <&scmi_perf IMX95_PERF_A55>; 101 power-domain-names = "perf"; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_cache_l3>; 109 }; 110 111 A55_4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 power-domains = <&scmi_perf IMX95_PERF_A55>; 116 power-domain-names = "perf"; 117 enable-method = "psci"; 118 #cooling-cells = <2>; 119 cpu-idle-states = <&cpu_pd_wait>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l4>; 127 }; 128 129 A55_5: cpu@500 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a55"; 132 reg = <0x500>; 133 power-domains = <&scmi_perf IMX95_PERF_A55>; 134 power-domain-names = "perf"; 135 enable-method = "psci"; 136 #cooling-cells = <2>; 137 cpu-idle-states = <&cpu_pd_wait>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l5>; 145 }; 146 147 l2_cache_l0: l2-cache-l0 { 148 compatible = "cache"; 149 cache-size = <65536>; 150 cache-line-size = <64>; 151 cache-sets = <256>; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_cache>; 155 }; 156 157 l2_cache_l1: l2-cache-l1 { 158 compatible = "cache"; 159 cache-size = <65536>; 160 cache-line-size = <64>; 161 cache-sets = <256>; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_cache>; 165 }; 166 167 l2_cache_l2: l2-cache-l2 { 168 compatible = "cache"; 169 cache-size = <65536>; 170 cache-line-size = <64>; 171 cache-sets = <256>; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_cache>; 175 }; 176 177 l2_cache_l3: l2-cache-l3 { 178 compatible = "cache"; 179 cache-size = <65536>; 180 cache-line-size = <64>; 181 cache-sets = <256>; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&l3_cache>; 185 }; 186 187 l2_cache_l4: l2-cache-l4 { 188 compatible = "cache"; 189 cache-size = <65536>; 190 cache-line-size = <64>; 191 cache-sets = <256>; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_cache>; 195 }; 196 197 l2_cache_l5: l2-cache-l5 { 198 compatible = "cache"; 199 cache-size = <65536>; 200 cache-line-size = <64>; 201 cache-sets = <256>; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&l3_cache>; 205 }; 206 207 l3_cache: l3-cache { 208 compatible = "cache"; 209 cache-size = <524288>; 210 cache-line-size = <64>; 211 cache-sets = <512>; 212 cache-level = <3>; 213 cache-unified; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&A55_0>; 220 }; 221 222 core1 { 223 cpu = <&A55_1>; 224 }; 225 226 core2 { 227 cpu = <&A55_2>; 228 }; 229 230 core3 { 231 cpu = <&A55_3>; 232 }; 233 234 core4 { 235 cpu = <&A55_4>; 236 }; 237 238 core5 { 239 cpu = <&A55_5>; 240 }; 241 }; 242 }; 243 }; 244 245 dummy: clock-dummy { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <0>; 249 clock-output-names = "dummy"; 250 }; 251 252 clk_ext1: clock-ext1 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <133000000>; 256 clock-output-names = "clk_ext1"; 257 }; 258 259 sai1_mclk: clock-sai-mclk1 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency= <0>; 263 clock-output-names = "sai1_mclk"; 264 }; 265 266 sai2_mclk: clock-sai-mclk2 { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 clock-frequency= <0>; 270 clock-output-names = "sai2_mclk"; 271 }; 272 273 sai3_mclk: clock-sai-mclk3 { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 clock-frequency= <0>; 277 clock-output-names = "sai3_mclk"; 278 }; 279 280 sai4_mclk: clock-sai-mclk4 { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency= <0>; 284 clock-output-names = "sai4_mclk"; 285 }; 286 287 sai5_mclk: clock-sai-mclk5 { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency= <0>; 291 clock-output-names = "sai5_mclk"; 292 }; 293 294 osc_24m: clock-24m { 295 compatible = "fixed-clock"; 296 #clock-cells = <0>; 297 clock-frequency = <24000000>; 298 clock-output-names = "osc_24m"; 299 }; 300 301 sram1: sram@204c0000 { 302 compatible = "mmio-sram"; 303 reg = <0x0 0x204c0000 0x0 0x18000>; 304 ranges = <0x0 0x0 0x204c0000 0x18000>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 }; 308 309 firmware { 310 scmi { 311 compatible = "arm,scmi"; 312 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 313 shmem = <&scmi_buf0>, <&scmi_buf1>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 arm,max-rx-timeout-ms = <5000>; 317 318 scmi_devpd: protocol@11 { 319 reg = <0x11>; 320 #power-domain-cells = <1>; 321 }; 322 323 scmi_sys_power: protocol@12 { 324 reg = <0x12>; 325 }; 326 327 scmi_perf: protocol@13 { 328 reg = <0x13>; 329 #power-domain-cells = <1>; 330 }; 331 332 scmi_clk: protocol@14 { 333 reg = <0x14>; 334 #clock-cells = <1>; 335 }; 336 337 scmi_sensor: protocol@15 { 338 reg = <0x15>; 339 #thermal-sensor-cells = <1>; 340 }; 341 342 scmi_iomuxc: protocol@19 { 343 reg = <0x19>; 344 }; 345 346 scmi_bbm: protocol@81 { 347 reg = <0x81>; 348 }; 349 350 scmi_misc: protocol@84 { 351 reg = <0x84>; 352 }; 353 }; 354 }; 355 356 pmu { 357 compatible = "arm,cortex-a55-pmu"; 358 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 359 }; 360 361 thermal_zones: thermal-zones { 362 a55-thermal { 363 polling-delay-passive = <250>; 364 polling-delay = <2000>; 365 thermal-sensors = <&scmi_sensor 1>; 366 367 trips { 368 cpu_alert0: trip0 { 369 temperature = <105000>; 370 hysteresis = <2000>; 371 type = "passive"; 372 }; 373 374 cpu_crit0: trip1 { 375 temperature = <125000>; 376 hysteresis = <2000>; 377 type = "critical"; 378 }; 379 }; 380 381 cooling-maps { 382 map0 { 383 trip = <&cpu_alert0>; 384 cooling-device = 385 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 388 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 389 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 390 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 391 }; 392 }; 393 }; 394 395 ana-thermal { 396 polling-delay-passive = <250>; 397 polling-delay = <2000>; 398 thermal-sensors = <&scmi_sensor 0>; 399 trips { 400 ana_alert: trip0 { 401 temperature = <105000>; 402 hysteresis = <2000>; 403 type = "passive"; 404 }; 405 406 ana_crit0: trip1 { 407 temperature = <125000>; 408 hysteresis = <2000>; 409 type = "critical"; 410 }; 411 }; 412 413 cooling-maps { 414 map0 { 415 trip = <&ana_alert>; 416 cooling-device = 417 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 418 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 419 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 420 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 421 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 422 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 423 }; 424 }; 425 }; 426 }; 427 428 psci { 429 compatible = "arm,psci-1.0"; 430 method = "smc"; 431 }; 432 433 timer { 434 compatible = "arm,armv8-timer"; 435 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 436 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 437 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 438 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 439 clock-frequency = <24000000>; 440 arm,no-tick-in-suspend; 441 interrupt-parent = <&gic>; 442 }; 443 444 gic: interrupt-controller@48000000 { 445 compatible = "arm,gic-v3"; 446 reg = <0 0x48000000 0 0x10000>, 447 <0 0x48060000 0 0xc0000>; 448 #address-cells = <2>; 449 #size-cells = <2>; 450 #interrupt-cells = <3>; 451 interrupt-controller; 452 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-parent = <&gic>; 454 dma-noncoherent; 455 ranges; 456 457 its: msi-controller@48040000 { 458 compatible = "arm,gic-v3-its"; 459 reg = <0 0x48040000 0 0x20000>; 460 msi-controller; 461 #msi-cells = <1>; 462 dma-noncoherent; 463 }; 464 }; 465 466 soc { 467 compatible = "simple-bus"; 468 #address-cells = <2>; 469 #size-cells = <2>; 470 ranges; 471 472 aips2: bus@42000000 { 473 compatible = "fsl,aips-bus", "simple-bus"; 474 reg = <0x0 0x42000000 0x0 0x800000>; 475 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 476 <0x28000000 0x0 0x28000000 0x10000000>; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 480 edma2: dma-controller@42000000 { 481 compatible = "fsl,imx95-edma5"; 482 reg = <0x42000000 0x210000>; 483 #dma-cells = <3>; 484 dma-channels = <64>; 485 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 550 clock-names = "dma"; 551 }; 552 553 edma3: dma-controller@42210000 { 554 compatible = "fsl,imx95-edma5"; 555 reg = <0x42210000 0x210000>; 556 #dma-cells = <3>; 557 dma-channels = <64>; 558 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 623 clock-names = "dma"; 624 }; 625 626 mu7: mailbox@42430000 { 627 compatible = "fsl,imx95-mu"; 628 reg = <0x42430000 0x10000>; 629 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 631 #mbox-cells = <2>; 632 status = "disabled"; 633 }; 634 635 wdog3: watchdog@42490000 { 636 compatible = "fsl,imx93-wdt"; 637 reg = <0x42490000 0x10000>; 638 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 640 timeout-sec = <40>; 641 status = "disabled"; 642 }; 643 644 tpm3: pwm@424e0000 { 645 compatible = "fsl,imx7ulp-pwm"; 646 reg = <0x424e0000 0x1000>; 647 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 648 #pwm-cells = <3>; 649 status = "disabled"; 650 }; 651 652 tpm4: pwm@424f0000 { 653 compatible = "fsl,imx7ulp-pwm"; 654 reg = <0x424f0000 0x1000>; 655 clocks = <&scmi_clk IMX95_CLK_TPM4>; 656 #pwm-cells = <3>; 657 status = "disabled"; 658 }; 659 660 tpm5: pwm@42500000 { 661 compatible = "fsl,imx7ulp-pwm"; 662 reg = <0x42500000 0x1000>; 663 clocks = <&scmi_clk IMX95_CLK_TPM5>; 664 #pwm-cells = <3>; 665 status = "disabled"; 666 }; 667 668 tpm6: pwm@42510000 { 669 compatible = "fsl,imx7ulp-pwm"; 670 reg = <0x42510000 0x1000>; 671 clocks = <&scmi_clk IMX95_CLK_TPM6>; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 lpi2c3: i2c@42530000 { 677 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 678 reg = <0x42530000 0x10000>; 679 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 681 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 682 clock-names = "per", "ipg"; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 686 dma-names = "tx", "rx"; 687 status = "disabled"; 688 }; 689 690 lpi2c4: i2c@42540000 { 691 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 692 reg = <0x42540000 0x10000>; 693 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 695 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 696 clock-names = "per", "ipg"; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 700 dma-names = "tx", "rx"; 701 status = "disabled"; 702 }; 703 704 lpspi3: spi@42550000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 708 reg = <0x42550000 0x10000>; 709 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 711 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 712 clock-names = "per", "ipg"; 713 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 714 dma-names = "tx", "rx"; 715 status = "disabled"; 716 }; 717 718 lpspi4: spi@42560000 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 722 reg = <0x42560000 0x10000>; 723 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 725 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 726 clock-names = "per", "ipg"; 727 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 728 dma-names = "tx", "rx"; 729 status = "disabled"; 730 }; 731 732 lpuart3: serial@42570000 { 733 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 734 "fsl,imx7ulp-lpuart"; 735 reg = <0x42570000 0x1000>; 736 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 738 clock-names = "ipg"; 739 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 740 dma-names = "rx", "tx"; 741 status = "disabled"; 742 }; 743 744 lpuart4: serial@42580000 { 745 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 746 "fsl,imx7ulp-lpuart"; 747 reg = <0x42580000 0x1000>; 748 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 750 clock-names = "ipg"; 751 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 752 dma-names = "rx", "tx"; 753 status = "disabled"; 754 }; 755 756 lpuart5: serial@42590000 { 757 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 758 "fsl,imx7ulp-lpuart"; 759 reg = <0x42590000 0x1000>; 760 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 762 clock-names = "ipg"; 763 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 764 dma-names = "rx", "tx"; 765 status = "disabled"; 766 }; 767 768 lpuart6: serial@425a0000 { 769 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 770 "fsl,imx7ulp-lpuart"; 771 reg = <0x425a0000 0x1000>; 772 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 774 clock-names = "ipg"; 775 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 776 dma-names = "rx", "tx"; 777 status = "disabled"; 778 }; 779 780 flexcan2: can@425b0000 { 781 compatible = "fsl,imx95-flexcan"; 782 reg = <0x425b0000 0x10000>; 783 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 785 <&scmi_clk IMX95_CLK_CAN2>; 786 clock-names = "ipg", "per"; 787 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 788 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 789 assigned-clock-rates = <40000000>; 790 fsl,clk-source = /bits/ 8 <0>; 791 status = "disabled"; 792 }; 793 794 flexcan3: can@42600000 { 795 compatible = "fsl,imx95-flexcan"; 796 reg = <0x42600000 0x10000>; 797 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 799 <&scmi_clk IMX95_CLK_CAN3>; 800 clock-names = "ipg", "per"; 801 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 802 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 803 assigned-clock-rates = <40000000>; 804 fsl,clk-source = /bits/ 8 <0>; 805 status = "disabled"; 806 }; 807 808 flexspi1: spi@425e0000 { 809 compatible = "nxp,imx8mm-fspi"; 810 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 811 reg-names = "fspi_base", "fspi_mmap"; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 816 <&scmi_clk IMX95_CLK_FLEXSPI1>; 817 clock-names = "fspi_en", "fspi"; 818 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 819 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 820 assigned-clock-rates = <200000000>; 821 status = "disabled"; 822 }; 823 824 sai3: sai@42650000 { 825 compatible = "fsl,imx95-sai"; 826 reg = <0x42650000 0x10000>; 827 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 829 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 830 <&dummy>; 831 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 832 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 833 dma-names = "rx", "tx"; 834 status = "disabled"; 835 }; 836 837 sai4: sai@42660000 { 838 compatible = "fsl,imx95-sai"; 839 reg = <0x42660000 0x10000>; 840 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 842 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 843 <&dummy>; 844 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 845 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 sai5: sai@42670000 { 851 compatible = "fsl,imx95-sai"; 852 reg = <0x42670000 0x10000>; 853 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 855 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 856 <&dummy>; 857 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 858 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 xcvr: xcvr@42680000 { 864 compatible = "fsl,imx95-xcvr"; 865 reg = <0x42680000 0x800>, <0x42680800 0x400>, 866 <0x42680c00 0x080>, <0x42680e00 0x080>; 867 reg-names = "ram", "regs", "rxfifo", "txfifo"; 868 interrupts = /* XCVR IRQ 0 */ 869 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 870 /* XCVR IRQ 1 */ 871 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 873 <&scmi_clk IMX95_CLK_SPDIF>, 874 <&dummy>, 875 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 876 clock-names = "ipg", "phy", "spba", "pll_ipg"; 877 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 878 dma-names = "rx", "tx"; 879 status = "disabled"; 880 }; 881 882 lpuart7: serial@42690000 { 883 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 884 "fsl,imx7ulp-lpuart"; 885 reg = <0x42690000 0x1000>; 886 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 888 clock-names = "ipg"; 889 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; 890 dma-names = "rx", "tx"; 891 status = "disabled"; 892 }; 893 894 lpuart8: serial@426a0000 { 895 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 896 "fsl,imx7ulp-lpuart"; 897 reg = <0x426a0000 0x1000>; 898 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 900 clock-names = "ipg"; 901 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; 902 dma-names = "rx", "tx"; 903 status = "disabled"; 904 }; 905 906 lpi2c5: i2c@426b0000 { 907 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 908 reg = <0x426b0000 0x10000>; 909 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 911 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 912 clock-names = "per", "ipg"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 916 dma-names = "tx", "rx"; 917 status = "disabled"; 918 }; 919 920 lpi2c6: i2c@426c0000 { 921 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 922 reg = <0x426c0000 0x10000>; 923 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 925 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 926 clock-names = "per", "ipg"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 930 dma-names = "tx", "rx"; 931 status = "disabled"; 932 }; 933 934 lpi2c7: i2c@426d0000 { 935 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 936 reg = <0x426d0000 0x10000>; 937 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 939 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 940 clock-names = "per", "ipg"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 944 dma-names = "tx", "rx"; 945 status = "disabled"; 946 }; 947 948 lpi2c8: i2c@426e0000 { 949 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 950 reg = <0x426e0000 0x10000>; 951 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 953 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 954 clock-names = "per", "ipg"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 958 dma-names = "tx", "rx"; 959 status = "disabled"; 960 }; 961 962 lpspi5: spi@426f0000 { 963 #address-cells = <1>; 964 #size-cells = <0>; 965 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 966 reg = <0x426f0000 0x10000>; 967 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 969 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 970 clock-names = "per", "ipg"; 971 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 972 dma-names = "tx", "rx"; 973 status = "disabled"; 974 }; 975 976 lpspi6: spi@42700000 { 977 #address-cells = <1>; 978 #size-cells = <0>; 979 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 980 reg = <0x42700000 0x10000>; 981 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 983 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 984 clock-names = "per", "ipg"; 985 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 986 dma-names = "tx", "rx"; 987 status = "disabled"; 988 }; 989 990 lpspi7: spi@42710000 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 994 reg = <0x42710000 0x10000>; 995 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 997 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 998 clock-names = "per", "ipg"; 999 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1000 dma-names = "tx", "rx"; 1001 status = "disabled"; 1002 }; 1003 1004 lpspi8: spi@42720000 { 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1008 reg = <0x42720000 0x10000>; 1009 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1011 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1012 clock-names = "per", "ipg"; 1013 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1014 dma-names = "tx", "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 mu8: mailbox@42730000 { 1019 compatible = "fsl,imx95-mu"; 1020 reg = <0x42730000 0x10000>; 1021 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1023 #mbox-cells = <2>; 1024 status = "disabled"; 1025 }; 1026 1027 flexcan4: can@427c0000 { 1028 compatible = "fsl,imx95-flexcan"; 1029 reg = <0x427c0000 0x10000>; 1030 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1032 <&scmi_clk IMX95_CLK_CAN4>; 1033 clock-names = "ipg", "per"; 1034 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1035 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1036 assigned-clock-rates = <40000000>; 1037 fsl,clk-source = /bits/ 8 <0>; 1038 status = "disabled"; 1039 }; 1040 1041 flexcan5: can@427d0000 { 1042 compatible = "fsl,imx95-flexcan"; 1043 reg = <0x427d0000 0x10000>; 1044 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1046 <&scmi_clk IMX95_CLK_CAN5>; 1047 clock-names = "ipg", "per"; 1048 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1049 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1050 assigned-clock-rates = <40000000>; 1051 fsl,clk-source = /bits/ 8 <0>; 1052 status = "disabled"; 1053 }; 1054 }; 1055 1056 aips3: bus@42800000 { 1057 compatible = "fsl,aips-bus", "simple-bus"; 1058 reg = <0 0x42800000 0 0x800000>; 1059 #address-cells = <1>; 1060 #size-cells = <1>; 1061 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1062 1063 usdhc1: mmc@42850000 { 1064 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1065 reg = <0x42850000 0x10000>; 1066 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1068 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1069 <&scmi_clk IMX95_CLK_USDHC1>; 1070 clock-names = "ipg", "ahb", "per"; 1071 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1072 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1073 assigned-clock-rates = <400000000>; 1074 bus-width = <8>; 1075 fsl,tuning-start-tap = <1>; 1076 fsl,tuning-step= <2>; 1077 status = "disabled"; 1078 }; 1079 1080 usdhc2: mmc@42860000 { 1081 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1082 reg = <0x42860000 0x10000>; 1083 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1085 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1086 <&scmi_clk IMX95_CLK_USDHC2>; 1087 clock-names = "ipg", "ahb", "per"; 1088 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1089 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1090 assigned-clock-rates = <400000000>; 1091 bus-width = <4>; 1092 fsl,tuning-start-tap = <1>; 1093 fsl,tuning-step= <2>; 1094 status = "disabled"; 1095 }; 1096 1097 usdhc3: mmc@428b0000 { 1098 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1099 reg = <0x428b0000 0x10000>; 1100 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1102 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1103 <&scmi_clk IMX95_CLK_USDHC3>; 1104 clock-names = "ipg", "ahb", "per"; 1105 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1106 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1107 assigned-clock-rates = <400000000>; 1108 bus-width = <4>; 1109 fsl,tuning-start-tap = <1>; 1110 fsl,tuning-step= <2>; 1111 status = "disabled"; 1112 }; 1113 }; 1114 1115 gpio2: gpio@43810000 { 1116 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1117 reg = <0x0 0x43810000 0x0 0x1000>; 1118 gpio-controller; 1119 #gpio-cells = <2>; 1120 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-controller; 1123 #interrupt-cells = <2>; 1124 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1125 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1126 clock-names = "gpio", "port"; 1127 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1128 }; 1129 1130 gpio3: gpio@43820000 { 1131 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1132 reg = <0x0 0x43820000 0x0 0x1000>; 1133 gpio-controller; 1134 #gpio-cells = <2>; 1135 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1137 interrupt-controller; 1138 #interrupt-cells = <2>; 1139 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1140 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1141 clock-names = "gpio", "port"; 1142 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1143 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1144 }; 1145 1146 gpio4: gpio@43840000 { 1147 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1148 reg = <0x0 0x43840000 0x0 0x1000>; 1149 gpio-controller; 1150 #gpio-cells = <2>; 1151 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1153 interrupt-controller; 1154 #interrupt-cells = <2>; 1155 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1156 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1157 clock-names = "gpio", "port"; 1158 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1159 }; 1160 1161 gpio5: gpio@43850000 { 1162 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1163 reg = <0x0 0x43850000 0x0 0x1000>; 1164 gpio-controller; 1165 #gpio-cells = <2>; 1166 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1168 interrupt-controller; 1169 #interrupt-cells = <2>; 1170 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1171 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1172 clock-names = "gpio", "port"; 1173 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1174 }; 1175 1176 aips1: bus@44000000 { 1177 compatible = "fsl,aips-bus", "simple-bus"; 1178 reg = <0x0 0x44000000 0x0 0x800000>; 1179 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1180 #address-cells = <1>; 1181 #size-cells = <1>; 1182 1183 edma1: dma-controller@44000000 { 1184 compatible = "fsl,imx93-edma3"; 1185 reg = <0x44000000 0x200000>; 1186 #dma-cells = <3>; 1187 dma-channels = <31>; 1188 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1220 clock-names = "dma"; 1221 }; 1222 1223 mu1: mailbox@44220000 { 1224 compatible = "fsl,imx95-mu"; 1225 reg = <0x44220000 0x10000>; 1226 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1228 #mbox-cells = <2>; 1229 status = "disabled"; 1230 }; 1231 1232 tpm1: pwm@44310000 { 1233 compatible = "fsl,imx7ulp-pwm"; 1234 reg = <0x44310000 0x1000>; 1235 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1236 #pwm-cells = <3>; 1237 status = "disabled"; 1238 }; 1239 1240 tpm2: pwm@44320000 { 1241 compatible = "fsl,imx7ulp-pwm"; 1242 reg = <0x44320000 0x1000>; 1243 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1244 #pwm-cells = <3>; 1245 status = "disabled"; 1246 }; 1247 1248 lpi2c1: i2c@44340000 { 1249 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1250 reg = <0x44340000 0x10000>; 1251 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1253 <&scmi_clk IMX95_CLK_BUSAON>; 1254 clock-names = "per", "ipg"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1258 dma-names = "tx", "rx"; 1259 status = "disabled"; 1260 }; 1261 1262 lpi2c2: i2c@44350000 { 1263 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1264 reg = <0x44350000 0x10000>; 1265 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1267 <&scmi_clk IMX95_CLK_BUSAON>; 1268 clock-names = "per", "ipg"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1272 dma-names = "tx", "rx"; 1273 status = "disabled"; 1274 }; 1275 1276 lpspi1: spi@44360000 { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1280 reg = <0x44360000 0x10000>; 1281 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1283 <&scmi_clk IMX95_CLK_BUSAON>; 1284 clock-names = "per", "ipg"; 1285 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1286 dma-names = "tx", "rx"; 1287 status = "disabled"; 1288 }; 1289 1290 lpspi2: spi@44370000 { 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1294 reg = <0x44370000 0x10000>; 1295 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1297 <&scmi_clk IMX95_CLK_BUSAON>; 1298 clock-names = "per", "ipg"; 1299 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1300 dma-names = "tx", "rx"; 1301 status = "disabled"; 1302 }; 1303 1304 lpuart1: serial@44380000 { 1305 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1306 "fsl,imx7ulp-lpuart"; 1307 reg = <0x44380000 0x1000>; 1308 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1310 clock-names = "ipg"; 1311 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1312 dma-names = "rx", "tx"; 1313 status = "disabled"; 1314 }; 1315 1316 lpuart2: serial@44390000 { 1317 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1318 "fsl,imx7ulp-lpuart"; 1319 reg = <0x44390000 0x1000>; 1320 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1322 clock-names = "ipg"; 1323 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1324 dma-names = "rx", "tx"; 1325 status = "disabled"; 1326 }; 1327 1328 flexcan1: can@443a0000 { 1329 compatible = "fsl,imx95-flexcan"; 1330 reg = <0x443a0000 0x10000>; 1331 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1333 <&scmi_clk IMX95_CLK_CAN1>; 1334 clock-names = "ipg", "per"; 1335 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1336 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1337 assigned-clock-rates = <40000000>; 1338 fsl,clk-source = /bits/ 8 <0>; 1339 status = "disabled"; 1340 }; 1341 1342 sai1: sai@443b0000 { 1343 compatible = "fsl,imx95-sai"; 1344 reg = <0x443b0000 0x10000>; 1345 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1346 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1347 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1348 <&dummy>; 1349 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1350 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1351 dma-names = "rx", "tx"; 1352 status = "disabled"; 1353 }; 1354 1355 micfil: micfil@44520000 { 1356 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1357 reg = <0x44520000 0x10000>; 1358 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1363 <&scmi_clk IMX95_CLK_PDM>, 1364 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1365 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1366 <&dummy>; 1367 clock-names = "ipg_clk", "ipg_clk_app", 1368 "pll8k", "pll11k", "clkext3"; 1369 dmas = <&edma1 6 0 5>; 1370 dma-names = "rx"; 1371 status = "disabled"; 1372 }; 1373 1374 adc1: adc@44530000 { 1375 compatible = "nxp,imx93-adc"; 1376 reg = <0x44530000 0x10000>; 1377 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&scmi_clk IMX95_CLK_ADC>; 1381 clock-names = "ipg"; 1382 status = "disabled"; 1383 }; 1384 1385 mu2: mailbox@445b0000 { 1386 compatible = "fsl,imx95-mu"; 1387 reg = <0x445b0000 0x1000>; 1388 ranges; 1389 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <1>; 1392 #mbox-cells = <2>; 1393 1394 sram0: sram@445b1000 { 1395 compatible = "mmio-sram"; 1396 reg = <0x445b1000 0x400>; 1397 ranges = <0x0 0x445b1000 0x400>; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 1401 scmi_buf0: scmi-sram-section@0 { 1402 compatible = "arm,scmi-shmem"; 1403 reg = <0x0 0x80>; 1404 }; 1405 1406 scmi_buf1: scmi-sram-section@80 { 1407 compatible = "arm,scmi-shmem"; 1408 reg = <0x80 0x80>; 1409 }; 1410 }; 1411 1412 }; 1413 1414 mu3: mailbox@445d0000 { 1415 compatible = "fsl,imx95-mu"; 1416 reg = <0x445d0000 0x10000>; 1417 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1419 #mbox-cells = <2>; 1420 status = "disabled"; 1421 }; 1422 1423 mu4: mailbox@445f0000 { 1424 compatible = "fsl,imx95-mu"; 1425 reg = <0x445f0000 0x10000>; 1426 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1428 #mbox-cells = <2>; 1429 status = "disabled"; 1430 }; 1431 1432 mu6: mailbox@44630000 { 1433 compatible = "fsl,imx95-mu"; 1434 reg = <0x44630000 0x10000>; 1435 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1437 #mbox-cells = <2>; 1438 status = "disabled"; 1439 }; 1440 }; 1441 1442 mailbox@47320000 { 1443 compatible = "fsl,imx95-mu-v2x"; 1444 reg = <0x0 0x47320000 0x0 0x10000>; 1445 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1446 #mbox-cells = <2>; 1447 }; 1448 1449 mailbox@47350000 { 1450 compatible = "fsl,imx95-mu-v2x"; 1451 reg = <0x0 0x47350000 0x0 0x10000>; 1452 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1453 #mbox-cells = <2>; 1454 }; 1455 1456 /* GPIO1 is under exclusive control of System Manager */ 1457 gpio1: gpio@47400000 { 1458 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1459 reg = <0x0 0x47400000 0x0 0x1000>; 1460 gpio-controller; 1461 #gpio-cells = <2>; 1462 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1464 interrupt-controller; 1465 #interrupt-cells = <2>; 1466 clocks = <&scmi_clk IMX95_CLK_M33>, 1467 <&scmi_clk IMX95_CLK_M33>; 1468 clock-names = "gpio", "port"; 1469 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1470 status = "disabled"; 1471 }; 1472 1473 elemu0: mailbox@47520000 { 1474 compatible = "fsl,imx95-mu-ele"; 1475 reg = <0x0 0x47520000 0x0 0x10000>; 1476 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1477 #mbox-cells = <2>; 1478 status = "disabled"; 1479 }; 1480 1481 elemu1: mailbox@47530000 { 1482 compatible = "fsl,imx95-mu-ele"; 1483 reg = <0x0 0x47530000 0x0 0x10000>; 1484 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1485 #mbox-cells = <2>; 1486 status = "disabled"; 1487 }; 1488 1489 elemu2: mailbox@47540000 { 1490 compatible = "fsl,imx95-mu-ele"; 1491 reg = <0x0 0x47540000 0x0 0x10000>; 1492 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1493 #mbox-cells = <2>; 1494 status = "disabled"; 1495 }; 1496 1497 elemu3: mailbox@47550000 { 1498 compatible = "fsl,imx95-mu-ele"; 1499 reg = <0x0 0x47550000 0x0 0x10000>; 1500 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1501 #mbox-cells = <2>; 1502 }; 1503 1504 elemu4: mailbox@47560000 { 1505 compatible = "fsl,imx95-mu-ele"; 1506 reg = <0x0 0x47560000 0x0 0x10000>; 1507 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1508 #mbox-cells = <2>; 1509 status = "disabled"; 1510 }; 1511 1512 elemu5: mailbox@47570000 { 1513 compatible = "fsl,imx95-mu-ele"; 1514 reg = <0x0 0x47570000 0x0 0x10000>; 1515 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1516 #mbox-cells = <2>; 1517 status = "disabled"; 1518 }; 1519 1520 aips4: bus@49000000 { 1521 compatible = "fsl,aips-bus", "simple-bus"; 1522 reg = <0x0 0x49000000 0x0 0x800000>; 1523 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1524 #address-cells = <1>; 1525 #size-cells = <1>; 1526 1527 smmu: iommu@490d0000 { 1528 compatible = "arm,smmu-v3"; 1529 reg = <0x490d0000 0x100000>; 1530 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1531 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1532 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1533 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1534 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1535 #iommu-cells = <1>; 1536 status = "disabled"; 1537 }; 1538 }; 1539 1540 pcie0: pcie@4c300000 { 1541 compatible = "fsl,imx95-pcie"; 1542 reg = <0 0x4c300000 0 0x10000>, 1543 <0 0x60100000 0 0xfe00000>, 1544 <0 0x4c360000 0 0x10000>, 1545 <0 0x4c340000 0 0x2000>; 1546 reg-names = "dbi", "config", "atu", "app"; 1547 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1548 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1549 #address-cells = <3>; 1550 #size-cells = <2>; 1551 device_type = "pci"; 1552 linux,pci-domain = <0>; 1553 bus-range = <0x00 0xff>; 1554 num-lanes = <1>; 1555 num-viewport = <8>; 1556 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1557 interrupt-names = "msi"; 1558 #interrupt-cells = <1>; 1559 interrupt-map-mask = <0 0 0 0x7>; 1560 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1561 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1562 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1563 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1565 <&scmi_clk IMX95_CLK_HSIOPLL>, 1566 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1567 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1568 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1569 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1570 <&scmi_clk IMX95_CLK_HSIOPLL>, 1571 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1572 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1573 assigned-clock-parents = <0>, <0>, 1574 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1575 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1576 fsl,max-link-speed = <3>; 1577 status = "disabled"; 1578 }; 1579 1580 pcie0_ep: pcie-ep@4c300000 { 1581 compatible = "fsl,imx95-pcie-ep"; 1582 reg = <0 0x4c300000 0 0x10000>, 1583 <0 0x4c360000 0 0x1000>, 1584 <0 0x4c320000 0 0x1000>, 1585 <0 0x4c340000 0 0x2000>, 1586 <0 0x4c370000 0 0x10000>, 1587 <0x9 0 1 0>; 1588 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1589 num-lanes = <1>; 1590 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1591 interrupt-names = "dma"; 1592 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1593 <&scmi_clk IMX95_CLK_HSIOPLL>, 1594 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1595 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1596 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1597 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1598 <&scmi_clk IMX95_CLK_HSIOPLL>, 1599 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1600 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1601 assigned-clock-parents = <0>, <0>, 1602 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1603 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1604 status = "disabled"; 1605 }; 1606 1607 pcie1: pcie@4c380000 { 1608 compatible = "fsl,imx95-pcie"; 1609 reg = <0 0x4c380000 0 0x10000>, 1610 <8 0x80100000 0 0xfe00000>, 1611 <0 0x4c3e0000 0 0x10000>, 1612 <0 0x4c3c0000 0 0x2000>; 1613 reg-names = "dbi", "config", "atu", "app"; 1614 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1615 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1616 #address-cells = <3>; 1617 #size-cells = <2>; 1618 device_type = "pci"; 1619 linux,pci-domain = <1>; 1620 bus-range = <0x00 0xff>; 1621 num-lanes = <1>; 1622 num-viewport = <8>; 1623 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1624 interrupt-names = "msi"; 1625 #interrupt-cells = <1>; 1626 interrupt-map-mask = <0 0 0 0x7>; 1627 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1628 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1629 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1630 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1632 <&scmi_clk IMX95_CLK_HSIOPLL>, 1633 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1634 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1635 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1636 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1637 <&scmi_clk IMX95_CLK_HSIOPLL>, 1638 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1639 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1640 assigned-clock-parents = <0>, <0>, 1641 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1642 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1643 fsl,max-link-speed = <3>; 1644 status = "disabled"; 1645 }; 1646 1647 pcie1_ep: pcie-ep@4c380000 { 1648 compatible = "fsl,imx95-pcie-ep"; 1649 reg = <0 0x4c380000 0 0x10000>, 1650 <0 0x4c3e0000 0 0x1000>, 1651 <0 0x4c3a0000 0 0x1000>, 1652 <0 0x4c3c0000 0 0x2000>, 1653 <0 0x4c3f0000 0 0x10000>, 1654 <0xa 0 1 0>; 1655 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1656 num-lanes = <1>; 1657 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-names = "dma"; 1659 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1660 <&scmi_clk IMX95_CLK_HSIOPLL>, 1661 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1662 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1663 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1664 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1665 <&scmi_clk IMX95_CLK_HSIOPLL>, 1666 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1667 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1668 assigned-clock-parents = <0>, <0>, 1669 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1670 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1671 status = "disabled"; 1672 }; 1673 1674 netcmix_blk_ctrl: syscon@4c810000 { 1675 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 1676 reg = <0x0 0x4c810000 0x0 0x10000>; 1677 #clock-cells = <1>; 1678 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1679 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1680 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1681 assigned-clock-rates = <133333333>; 1682 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1683 status = "disabled"; 1684 }; 1685 1686 sai2: sai@4c880000 { 1687 compatible = "fsl,imx95-sai"; 1688 reg = <0x0 0x4c880000 0x0 0x10000>; 1689 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 1691 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 1692 <&dummy>; 1693 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1694 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1695 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1696 dma-names = "rx", "tx"; 1697 status = "disabled"; 1698 }; 1699 1700 ddr-pmu@4e090dc0 { 1701 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 1702 reg = <0x0 0x4e090dc0 0x0 0x200>; 1703 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1704 }; 1705 }; 1706}; 1707