1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx95-clock.h" 13#include "imx95-pinfunc.h" 14#include "imx95-power.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 A55_0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 #cooling-cells = <2>; 31 power-domains = <&scmi_devpd IMX95_PERF_A55>; 32 power-domain-names = "perf"; 33 i-cache-size = <32768>; 34 i-cache-line-size = <64>; 35 i-cache-sets = <128>; 36 d-cache-size = <32768>; 37 d-cache-line-size = <64>; 38 d-cache-sets = <128>; 39 next-level-cache = <&l2_cache_l0>; 40 }; 41 42 A55_1: cpu@100 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a55"; 45 reg = <0x100>; 46 enable-method = "psci"; 47 #cooling-cells = <2>; 48 power-domains = <&scmi_devpd IMX95_PERF_A55>; 49 power-domain-names = "perf"; 50 i-cache-size = <32768>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <128>; 53 d-cache-size = <32768>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache_l1>; 57 }; 58 59 A55_2: cpu@200 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x200>; 63 enable-method = "psci"; 64 #cooling-cells = <2>; 65 power-domains = <&scmi_devpd IMX95_PERF_A55>; 66 power-domain-names = "perf"; 67 i-cache-size = <32768>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <128>; 70 d-cache-size = <32768>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_cache_l2>; 74 }; 75 76 A55_3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x300>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 power-domains = <&scmi_devpd IMX95_PERF_A55>; 83 power-domain-names = "perf"; 84 i-cache-size = <32768>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <128>; 87 d-cache-size = <32768>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&l2_cache_l3>; 91 }; 92 93 A55_4: cpu@400 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x400>; 97 power-domains = <&scmi_devpd IMX95_PERF_A55>; 98 power-domain-names = "perf"; 99 enable-method = "psci"; 100 #cooling-cells = <2>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l4>; 108 }; 109 110 A55_5: cpu@500 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x500>; 114 power-domains = <&scmi_devpd IMX95_PERF_A55>; 115 power-domain-names = "perf"; 116 enable-method = "psci"; 117 #cooling-cells = <2>; 118 i-cache-size = <32768>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <128>; 121 d-cache-size = <32768>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <128>; 124 next-level-cache = <&l2_cache_l5>; 125 }; 126 127 l2_cache_l0: l2-cache-l0 { 128 compatible = "cache"; 129 cache-size = <65536>; 130 cache-line-size = <64>; 131 cache-sets = <256>; 132 cache-level = <2>; 133 cache-unified; 134 next-level-cache = <&l3_cache>; 135 }; 136 137 l2_cache_l1: l2-cache-l1 { 138 compatible = "cache"; 139 cache-size = <65536>; 140 cache-line-size = <64>; 141 cache-sets = <256>; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_cache>; 145 }; 146 147 l2_cache_l2: l2-cache-l2 { 148 compatible = "cache"; 149 cache-size = <65536>; 150 cache-line-size = <64>; 151 cache-sets = <256>; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_cache>; 155 }; 156 157 l2_cache_l3: l2-cache-l3 { 158 compatible = "cache"; 159 cache-size = <65536>; 160 cache-line-size = <64>; 161 cache-sets = <256>; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_cache>; 165 }; 166 167 l2_cache_l4: l2-cache-l4 { 168 compatible = "cache"; 169 cache-size = <65536>; 170 cache-line-size = <64>; 171 cache-sets = <256>; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_cache>; 175 }; 176 177 l2_cache_l5: l2-cache-l5 { 178 compatible = "cache"; 179 cache-size = <65536>; 180 cache-line-size = <64>; 181 cache-sets = <256>; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&l3_cache>; 185 }; 186 187 l3_cache: l3-cache { 188 compatible = "cache"; 189 cache-size = <524288>; 190 cache-line-size = <64>; 191 cache-sets = <1024>; 192 cache-level = <3>; 193 cache-unified; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&A55_0>; 200 }; 201 202 core1 { 203 cpu = <&A55_1>; 204 }; 205 206 core2 { 207 cpu = <&A55_2>; 208 }; 209 210 core3 { 211 cpu = <&A55_3>; 212 }; 213 214 core4 { 215 cpu = <&A55_4>; 216 }; 217 218 core5 { 219 cpu = <&A55_5>; 220 }; 221 }; 222 }; 223 }; 224 225 dummy: clock-dummy { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 clock-frequency = <0>; 229 clock-output-names = "dummy"; 230 }; 231 232 clk_ext1: clock-ext1 { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 clock-frequency = <133000000>; 236 clock-output-names = "clk_ext1"; 237 }; 238 239 sai1_mclk: clock-sai-mclk1 { 240 compatible = "fixed-clock"; 241 #clock-cells = <0>; 242 clock-frequency= <0>; 243 clock-output-names = "sai1_mclk"; 244 }; 245 246 sai2_mclk: clock-sai-mclk2 { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency= <0>; 250 clock-output-names = "sai2_mclk"; 251 }; 252 253 sai3_mclk: clock-sai-mclk3 { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency= <0>; 257 clock-output-names = "sai3_mclk"; 258 }; 259 260 sai4_mclk: clock-sai-mclk4 { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency= <0>; 264 clock-output-names = "sai4_mclk"; 265 }; 266 267 sai5_mclk: clock-sai-mclk5 { 268 compatible = "fixed-clock"; 269 #clock-cells = <0>; 270 clock-frequency= <0>; 271 clock-output-names = "sai5_mclk"; 272 }; 273 274 osc_24m: clock-24m { 275 compatible = "fixed-clock"; 276 #clock-cells = <0>; 277 clock-frequency = <24000000>; 278 clock-output-names = "osc_24m"; 279 }; 280 281 sram1: sram@204c0000 { 282 compatible = "mmio-sram"; 283 reg = <0x0 0x204c0000 0x0 0x18000>; 284 ranges = <0x0 0x0 0x204c0000 0x18000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 }; 288 289 firmware { 290 scmi { 291 compatible = "arm,scmi"; 292 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 293 shmem = <&scmi_buf0>, <&scmi_buf1>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 scmi_devpd: protocol@11 { 298 reg = <0x11>; 299 #power-domain-cells = <1>; 300 }; 301 302 scmi_perf: protocol@13 { 303 reg = <0x13>; 304 #power-domain-cells = <1>; 305 }; 306 307 scmi_clk: protocol@14 { 308 reg = <0x14>; 309 #clock-cells = <1>; 310 }; 311 312 scmi_sensor: protocol@15 { 313 reg = <0x15>; 314 #thermal-sensor-cells = <1>; 315 }; 316 317 scmi_iomuxc: protocol@19 { 318 reg = <0x19>; 319 }; 320 321 }; 322 }; 323 324 pmu { 325 compatible = "arm,cortex-a55-pmu"; 326 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 327 }; 328 329 thermal_zones: thermal-zones { 330 a55-thermal { 331 polling-delay-passive = <250>; 332 polling-delay = <2000>; 333 thermal-sensors = <&scmi_sensor 1>; 334 335 trips { 336 cpu_alert0: trip0 { 337 temperature = <85000>; 338 hysteresis = <2000>; 339 type = "passive"; 340 }; 341 342 cpu_crit0: trip1 { 343 temperature = <95000>; 344 hysteresis = <2000>; 345 type = "critical"; 346 }; 347 }; 348 349 cooling-maps { 350 map0 { 351 trip = <&cpu_alert0>; 352 cooling-device = 353 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 354 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 357 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 358 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 359 }; 360 }; 361 }; 362 }; 363 364 psci { 365 compatible = "arm,psci-1.0"; 366 method = "smc"; 367 }; 368 369 timer { 370 compatible = "arm,armv8-timer"; 371 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 372 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 373 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 374 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 375 clock-frequency = <24000000>; 376 arm,no-tick-in-suspend; 377 interrupt-parent = <&gic>; 378 }; 379 380 gic: interrupt-controller@48000000 { 381 compatible = "arm,gic-v3"; 382 reg = <0 0x48000000 0 0x10000>, 383 <0 0x48060000 0 0xc0000>; 384 #address-cells = <2>; 385 #size-cells = <2>; 386 #interrupt-cells = <3>; 387 interrupt-controller; 388 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-parent = <&gic>; 390 dma-noncoherent; 391 ranges; 392 393 its: msi-controller@48040000 { 394 compatible = "arm,gic-v3-its"; 395 reg = <0 0x48040000 0 0x20000>; 396 msi-controller; 397 #msi-cells = <1>; 398 dma-noncoherent; 399 }; 400 }; 401 402 soc { 403 compatible = "simple-bus"; 404 #address-cells = <2>; 405 #size-cells = <2>; 406 ranges; 407 408 aips2: bus@42000000 { 409 compatible = "fsl,aips-bus", "simple-bus"; 410 reg = <0x0 0x42000000 0x0 0x800000>; 411 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 412 <0x28000000 0x0 0x28000000 0x10000000>; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 416 edma2: dma-controller@42000000 { 417 compatible = "fsl,imx95-edma5"; 418 reg = <0x42000000 0x210000>; 419 #dma-cells = <3>; 420 dma-channels = <64>; 421 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 486 clock-names = "dma"; 487 }; 488 489 edma3: dma-controller@42210000 { 490 compatible = "fsl,imx95-edma5"; 491 reg = <0x42210000 0x210000>; 492 #dma-cells = <3>; 493 dma-channels = <64>; 494 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 559 clock-names = "dma"; 560 }; 561 562 mu7: mailbox@42430000 { 563 compatible = "fsl,imx95-mu"; 564 reg = <0x42430000 0x10000>; 565 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 567 #mbox-cells = <2>; 568 status = "disabled"; 569 }; 570 571 wdog3: watchdog@42490000 { 572 compatible = "fsl,imx93-wdt"; 573 reg = <0x42490000 0x10000>; 574 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 576 timeout-sec = <40>; 577 status = "disabled"; 578 }; 579 580 tpm3: pwm@424e0000 { 581 compatible = "fsl,imx7ulp-pwm"; 582 reg = <0x424e0000 0x1000>; 583 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 584 #pwm-cells = <3>; 585 status = "disabled"; 586 }; 587 588 tpm4: pwm@424f0000 { 589 compatible = "fsl,imx7ulp-pwm"; 590 reg = <0x424f0000 0x1000>; 591 clocks = <&scmi_clk IMX95_CLK_TPM4>; 592 #pwm-cells = <3>; 593 status = "disabled"; 594 }; 595 596 tpm5: pwm@42500000 { 597 compatible = "fsl,imx7ulp-pwm"; 598 reg = <0x42500000 0x1000>; 599 clocks = <&scmi_clk IMX95_CLK_TPM5>; 600 #pwm-cells = <3>; 601 status = "disabled"; 602 }; 603 604 tpm6: pwm@42510000 { 605 compatible = "fsl,imx7ulp-pwm"; 606 reg = <0x42510000 0x1000>; 607 clocks = <&scmi_clk IMX95_CLK_TPM6>; 608 #pwm-cells = <3>; 609 status = "disabled"; 610 }; 611 612 lpi2c3: i2c@42530000 { 613 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 614 reg = <0x42530000 0x10000>; 615 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 617 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 618 clock-names = "per", "ipg"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 622 dma-names = "tx", "rx"; 623 status = "disabled"; 624 }; 625 626 lpi2c4: i2c@42540000 { 627 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 628 reg = <0x42540000 0x10000>; 629 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 631 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 632 clock-names = "per", "ipg"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 636 dma-names = "tx", "rx"; 637 status = "disabled"; 638 }; 639 640 lpspi3: spi@42550000 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 644 reg = <0x42550000 0x10000>; 645 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 647 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 648 clock-names = "per", "ipg"; 649 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 650 dma-names = "tx", "rx"; 651 status = "disabled"; 652 }; 653 654 lpspi4: spi@42560000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 658 reg = <0x42560000 0x10000>; 659 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 661 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 662 clock-names = "per", "ipg"; 663 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 664 dma-names = "tx", "rx"; 665 status = "disabled"; 666 }; 667 668 lpuart3: serial@42570000 { 669 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 670 "fsl,imx7ulp-lpuart"; 671 reg = <0x42570000 0x1000>; 672 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 674 clock-names = "ipg"; 675 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 676 dma-names = "rx", "tx"; 677 status = "disabled"; 678 }; 679 680 lpuart4: serial@42580000 { 681 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 682 "fsl,imx7ulp-lpuart"; 683 reg = <0x42580000 0x1000>; 684 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 686 clock-names = "ipg"; 687 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 688 dma-names = "rx", "tx"; 689 status = "disabled"; 690 }; 691 692 lpuart5: serial@42590000 { 693 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 694 "fsl,imx7ulp-lpuart"; 695 reg = <0x42590000 0x1000>; 696 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 698 clock-names = "ipg"; 699 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 700 dma-names = "rx", "tx"; 701 status = "disabled"; 702 }; 703 704 lpuart6: serial@425a0000 { 705 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 706 "fsl,imx7ulp-lpuart"; 707 reg = <0x425a0000 0x1000>; 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 710 clock-names = "ipg"; 711 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 712 dma-names = "rx", "tx"; 713 status = "disabled"; 714 }; 715 716 flexcan2: can@425b0000 { 717 compatible = "fsl,imx95-flexcan"; 718 reg = <0x425b0000 0x10000>; 719 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 721 <&scmi_clk IMX95_CLK_CAN2>; 722 clock-names = "ipg", "per"; 723 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 724 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 725 assigned-clock-rates = <40000000>; 726 fsl,clk-source = /bits/ 8 <0>; 727 status = "disabled"; 728 }; 729 730 flexcan3: can@42600000 { 731 compatible = "fsl,imx95-flexcan"; 732 reg = <0x42600000 0x10000>; 733 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 735 <&scmi_clk IMX95_CLK_CAN3>; 736 clock-names = "ipg", "per"; 737 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 738 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 739 assigned-clock-rates = <40000000>; 740 fsl,clk-source = /bits/ 8 <0>; 741 status = "disabled"; 742 }; 743 744 flexspi1: spi@425e0000 { 745 compatible = "nxp,imx8mm-fspi"; 746 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 747 reg-names = "fspi_base", "fspi_mmap"; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 752 <&scmi_clk IMX95_CLK_FLEXSPI1>; 753 clock-names = "fspi_en", "fspi"; 754 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 755 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 756 assigned-clock-rates = <200000000>; 757 status = "disabled"; 758 }; 759 760 sai3: sai@42650000 { 761 compatible = "fsl,imx95-sai"; 762 reg = <0x42650000 0x10000>; 763 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 765 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 766 <&dummy>; 767 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 768 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 769 dma-names = "rx", "tx"; 770 status = "disabled"; 771 }; 772 773 sai4: sai@42660000 { 774 compatible = "fsl,imx95-sai"; 775 reg = <0x42660000 0x10000>; 776 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 778 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 779 <&dummy>; 780 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 781 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 sai5: sai@42670000 { 787 compatible = "fsl,imx95-sai"; 788 reg = <0x42670000 0x10000>; 789 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 791 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 792 <&dummy>; 793 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 794 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 xcvr: xcvr@42680000 { 800 compatible = "fsl,imx95-xcvr"; 801 reg = <0x42680000 0x800>, <0x42680800 0x400>, 802 <0x42680c00 0x080>, <0x42680e00 0x080>; 803 reg-names = "ram", "regs", "rxfifo", "txfifo"; 804 interrupts = /* XCVR IRQ 0 */ 805 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 806 /* XCVR IRQ 1 */ 807 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 809 <&scmi_clk IMX95_CLK_SPDIF>, 810 <&dummy>, 811 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 812 clock-names = "ipg", "phy", "spba", "pll_ipg"; 813 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 814 dma-names = "rx", "tx"; 815 status = "disabled"; 816 }; 817 818 lpuart7: serial@42690000 { 819 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 820 "fsl,imx7ulp-lpuart"; 821 reg = <0x42690000 0x1000>; 822 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 824 clock-names = "ipg"; 825 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; 826 dma-names = "rx", "tx"; 827 status = "disabled"; 828 }; 829 830 lpuart8: serial@426a0000 { 831 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 832 "fsl,imx7ulp-lpuart"; 833 reg = <0x426a0000 0x1000>; 834 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 836 clock-names = "ipg"; 837 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; 838 dma-names = "rx", "tx"; 839 status = "disabled"; 840 }; 841 842 lpi2c5: i2c@426b0000 { 843 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 844 reg = <0x426b0000 0x10000>; 845 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 847 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 848 clock-names = "per", "ipg"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 852 dma-names = "tx", "rx"; 853 status = "disabled"; 854 }; 855 856 lpi2c6: i2c@426c0000 { 857 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 858 reg = <0x426c0000 0x10000>; 859 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 861 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 862 clock-names = "per", "ipg"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 866 dma-names = "tx", "rx"; 867 status = "disabled"; 868 }; 869 870 lpi2c7: i2c@426d0000 { 871 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 872 reg = <0x426d0000 0x10000>; 873 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 875 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 876 clock-names = "per", "ipg"; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 880 dma-names = "tx", "rx"; 881 status = "disabled"; 882 }; 883 884 lpi2c8: i2c@426e0000 { 885 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 886 reg = <0x426e0000 0x10000>; 887 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 889 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 890 clock-names = "per", "ipg"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 894 dma-names = "tx", "rx"; 895 status = "disabled"; 896 }; 897 898 lpspi5: spi@426f0000 { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 902 reg = <0x426f0000 0x10000>; 903 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 905 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 906 clock-names = "per", "ipg"; 907 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 908 dma-names = "tx", "rx"; 909 status = "disabled"; 910 }; 911 912 lpspi6: spi@42700000 { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 916 reg = <0x42700000 0x10000>; 917 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 919 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 920 clock-names = "per", "ipg"; 921 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 922 dma-names = "tx", "rx"; 923 status = "disabled"; 924 }; 925 926 lpspi7: spi@42710000 { 927 #address-cells = <1>; 928 #size-cells = <0>; 929 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 930 reg = <0x42710000 0x10000>; 931 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 933 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 934 clock-names = "per", "ipg"; 935 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 936 dma-names = "tx", "rx"; 937 status = "disabled"; 938 }; 939 940 lpspi8: spi@42720000 { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 944 reg = <0x42720000 0x10000>; 945 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 947 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 948 clock-names = "per", "ipg"; 949 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 950 dma-names = "tx", "rx"; 951 status = "disabled"; 952 }; 953 954 mu8: mailbox@42730000 { 955 compatible = "fsl,imx95-mu"; 956 reg = <0x42730000 0x10000>; 957 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 959 #mbox-cells = <2>; 960 status = "disabled"; 961 }; 962 963 flexcan4: can@427c0000 { 964 compatible = "fsl,imx95-flexcan"; 965 reg = <0x427c0000 0x10000>; 966 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 968 <&scmi_clk IMX95_CLK_CAN4>; 969 clock-names = "ipg", "per"; 970 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 971 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 972 assigned-clock-rates = <40000000>; 973 fsl,clk-source = /bits/ 8 <0>; 974 status = "disabled"; 975 }; 976 977 flexcan5: can@427d0000 { 978 compatible = "fsl,imx95-flexcan"; 979 reg = <0x427d0000 0x10000>; 980 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 982 <&scmi_clk IMX95_CLK_CAN5>; 983 clock-names = "ipg", "per"; 984 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 985 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 986 assigned-clock-rates = <40000000>; 987 fsl,clk-source = /bits/ 8 <0>; 988 status = "disabled"; 989 }; 990 }; 991 992 aips3: bus@42800000 { 993 compatible = "fsl,aips-bus", "simple-bus"; 994 reg = <0 0x42800000 0 0x800000>; 995 #address-cells = <1>; 996 #size-cells = <1>; 997 ranges = <0x42800000 0x0 0x42800000 0x800000>; 998 999 usdhc1: mmc@42850000 { 1000 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1001 reg = <0x42850000 0x10000>; 1002 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1004 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1005 <&scmi_clk IMX95_CLK_USDHC1>; 1006 clock-names = "ipg", "ahb", "per"; 1007 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1008 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1009 assigned-clock-rates = <400000000>; 1010 bus-width = <8>; 1011 fsl,tuning-start-tap = <1>; 1012 fsl,tuning-step= <2>; 1013 status = "disabled"; 1014 }; 1015 1016 usdhc2: mmc@42860000 { 1017 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1018 reg = <0x42860000 0x10000>; 1019 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1021 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1022 <&scmi_clk IMX95_CLK_USDHC2>; 1023 clock-names = "ipg", "ahb", "per"; 1024 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1025 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1026 assigned-clock-rates = <400000000>; 1027 bus-width = <4>; 1028 fsl,tuning-start-tap = <1>; 1029 fsl,tuning-step= <2>; 1030 status = "disabled"; 1031 }; 1032 1033 usdhc3: mmc@428b0000 { 1034 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1035 reg = <0x428b0000 0x10000>; 1036 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1038 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1039 <&scmi_clk IMX95_CLK_USDHC3>; 1040 clock-names = "ipg", "ahb", "per"; 1041 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1042 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1043 assigned-clock-rates = <400000000>; 1044 bus-width = <4>; 1045 fsl,tuning-start-tap = <1>; 1046 fsl,tuning-step= <2>; 1047 status = "disabled"; 1048 }; 1049 }; 1050 1051 gpio2: gpio@43810000 { 1052 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1053 reg = <0x0 0x43810000 0x0 0x1000>; 1054 gpio-controller; 1055 #gpio-cells = <2>; 1056 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-controller; 1059 #interrupt-cells = <2>; 1060 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1061 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1062 clock-names = "gpio", "port"; 1063 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1064 }; 1065 1066 gpio3: gpio@43820000 { 1067 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1068 reg = <0x0 0x43820000 0x0 0x1000>; 1069 gpio-controller; 1070 #gpio-cells = <2>; 1071 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-controller; 1074 #interrupt-cells = <2>; 1075 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1076 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1077 clock-names = "gpio", "port"; 1078 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1079 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1080 }; 1081 1082 gpio4: gpio@43840000 { 1083 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1084 reg = <0x0 0x43840000 0x0 0x1000>; 1085 gpio-controller; 1086 #gpio-cells = <2>; 1087 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1089 interrupt-controller; 1090 #interrupt-cells = <2>; 1091 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1092 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1093 clock-names = "gpio", "port"; 1094 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1095 }; 1096 1097 gpio5: gpio@43850000 { 1098 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1099 reg = <0x0 0x43850000 0x0 0x1000>; 1100 gpio-controller; 1101 #gpio-cells = <2>; 1102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1104 interrupt-controller; 1105 #interrupt-cells = <2>; 1106 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1107 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1108 clock-names = "gpio", "port"; 1109 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1110 }; 1111 1112 aips1: bus@44000000 { 1113 compatible = "fsl,aips-bus", "simple-bus"; 1114 reg = <0x0 0x44000000 0x0 0x800000>; 1115 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1116 #address-cells = <1>; 1117 #size-cells = <1>; 1118 1119 edma1: dma-controller@44000000 { 1120 compatible = "fsl,imx93-edma3"; 1121 reg = <0x44000000 0x200000>; 1122 #dma-cells = <3>; 1123 dma-channels = <31>; 1124 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1156 clock-names = "dma"; 1157 }; 1158 1159 mu1: mailbox@44220000 { 1160 compatible = "fsl,imx95-mu"; 1161 reg = <0x44220000 0x10000>; 1162 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1164 #mbox-cells = <2>; 1165 status = "disabled"; 1166 }; 1167 1168 tpm1: pwm@44310000 { 1169 compatible = "fsl,imx7ulp-pwm"; 1170 reg = <0x44310000 0x1000>; 1171 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1172 #pwm-cells = <3>; 1173 status = "disabled"; 1174 }; 1175 1176 tpm2: pwm@44320000 { 1177 compatible = "fsl,imx7ulp-pwm"; 1178 reg = <0x44320000 0x1000>; 1179 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1180 #pwm-cells = <3>; 1181 status = "disabled"; 1182 }; 1183 1184 lpi2c1: i2c@44340000 { 1185 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1186 reg = <0x44340000 0x10000>; 1187 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1189 <&scmi_clk IMX95_CLK_BUSAON>; 1190 clock-names = "per", "ipg"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1194 dma-names = "tx", "rx"; 1195 status = "disabled"; 1196 }; 1197 1198 lpi2c2: i2c@44350000 { 1199 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1200 reg = <0x44350000 0x10000>; 1201 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1203 <&scmi_clk IMX95_CLK_BUSAON>; 1204 clock-names = "per", "ipg"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1208 dma-names = "tx", "rx"; 1209 status = "disabled"; 1210 }; 1211 1212 lpspi1: spi@44360000 { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1216 reg = <0x44360000 0x10000>; 1217 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1219 <&scmi_clk IMX95_CLK_BUSAON>; 1220 clock-names = "per", "ipg"; 1221 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1222 dma-names = "tx", "rx"; 1223 status = "disabled"; 1224 }; 1225 1226 lpspi2: spi@44370000 { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1230 reg = <0x44370000 0x10000>; 1231 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1233 <&scmi_clk IMX95_CLK_BUSAON>; 1234 clock-names = "per", "ipg"; 1235 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1236 dma-names = "tx", "rx"; 1237 status = "disabled"; 1238 }; 1239 1240 lpuart1: serial@44380000 { 1241 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1242 "fsl,imx7ulp-lpuart"; 1243 reg = <0x44380000 0x1000>; 1244 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1246 clock-names = "ipg"; 1247 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1248 dma-names = "rx", "tx"; 1249 status = "disabled"; 1250 }; 1251 1252 lpuart2: serial@44390000 { 1253 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1254 "fsl,imx7ulp-lpuart"; 1255 reg = <0x44390000 0x1000>; 1256 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1258 clock-names = "ipg"; 1259 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1260 dma-names = "rx", "tx"; 1261 status = "disabled"; 1262 }; 1263 1264 flexcan1: can@443a0000 { 1265 compatible = "fsl,imx95-flexcan"; 1266 reg = <0x443a0000 0x10000>; 1267 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1269 <&scmi_clk IMX95_CLK_CAN1>; 1270 clock-names = "ipg", "per"; 1271 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1272 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1273 assigned-clock-rates = <40000000>; 1274 fsl,clk-source = /bits/ 8 <0>; 1275 status = "disabled"; 1276 }; 1277 1278 sai1: sai@443b0000 { 1279 compatible = "fsl,imx95-sai"; 1280 reg = <0x443b0000 0x10000>; 1281 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1283 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1284 <&dummy>; 1285 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1286 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1287 dma-names = "rx", "tx"; 1288 status = "disabled"; 1289 }; 1290 1291 micfil: micfil@44520000 { 1292 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1293 reg = <0x44520000 0x10000>; 1294 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1299 <&scmi_clk IMX95_CLK_PDM>, 1300 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1301 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1302 <&dummy>; 1303 clock-names = "ipg_clk", "ipg_clk_app", 1304 "pll8k", "pll11k", "clkext3"; 1305 dmas = <&edma1 6 0 5>; 1306 dma-names = "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 adc1: adc@44530000 { 1311 compatible = "nxp,imx93-adc"; 1312 reg = <0x44530000 0x10000>; 1313 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&scmi_clk IMX95_CLK_ADC>; 1317 clock-names = "ipg"; 1318 status = "disabled"; 1319 }; 1320 1321 mu2: mailbox@445b0000 { 1322 compatible = "fsl,imx95-mu"; 1323 reg = <0x445b0000 0x1000>; 1324 ranges; 1325 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1326 #address-cells = <1>; 1327 #size-cells = <1>; 1328 #mbox-cells = <2>; 1329 1330 sram0: sram@445b1000 { 1331 compatible = "mmio-sram"; 1332 reg = <0x445b1000 0x400>; 1333 ranges = <0x0 0x445b1000 0x400>; 1334 #address-cells = <1>; 1335 #size-cells = <1>; 1336 1337 scmi_buf0: scmi-sram-section@0 { 1338 compatible = "arm,scmi-shmem"; 1339 reg = <0x0 0x80>; 1340 }; 1341 1342 scmi_buf1: scmi-sram-section@80 { 1343 compatible = "arm,scmi-shmem"; 1344 reg = <0x80 0x80>; 1345 }; 1346 }; 1347 1348 }; 1349 1350 mu3: mailbox@445d0000 { 1351 compatible = "fsl,imx95-mu"; 1352 reg = <0x445d0000 0x10000>; 1353 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1355 #mbox-cells = <2>; 1356 status = "disabled"; 1357 }; 1358 1359 mu4: mailbox@445f0000 { 1360 compatible = "fsl,imx95-mu"; 1361 reg = <0x445f0000 0x10000>; 1362 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1363 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1364 #mbox-cells = <2>; 1365 status = "disabled"; 1366 }; 1367 1368 mu6: mailbox@44630000 { 1369 compatible = "fsl,imx95-mu"; 1370 reg = <0x44630000 0x10000>; 1371 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1373 #mbox-cells = <2>; 1374 status = "disabled"; 1375 }; 1376 }; 1377 1378 mailbox@47320000 { 1379 compatible = "fsl,imx95-mu-v2x"; 1380 reg = <0x0 0x47320000 0x0 0x10000>; 1381 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1382 #mbox-cells = <2>; 1383 }; 1384 1385 mailbox@47350000 { 1386 compatible = "fsl,imx95-mu-v2x"; 1387 reg = <0x0 0x47350000 0x0 0x10000>; 1388 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1389 #mbox-cells = <2>; 1390 }; 1391 1392 /* GPIO1 is under exclusive control of System Manager */ 1393 gpio1: gpio@47400000 { 1394 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1395 reg = <0x0 0x47400000 0x0 0x1000>; 1396 gpio-controller; 1397 #gpio-cells = <2>; 1398 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-controller; 1401 #interrupt-cells = <2>; 1402 clocks = <&scmi_clk IMX95_CLK_M33>, 1403 <&scmi_clk IMX95_CLK_M33>; 1404 clock-names = "gpio", "port"; 1405 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1406 status = "disabled"; 1407 }; 1408 1409 elemu0: mailbox@47520000 { 1410 compatible = "fsl,imx95-mu-ele"; 1411 reg = <0x0 0x47520000 0x0 0x10000>; 1412 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1413 #mbox-cells = <2>; 1414 status = "disabled"; 1415 }; 1416 1417 elemu1: mailbox@47530000 { 1418 compatible = "fsl,imx95-mu-ele"; 1419 reg = <0x0 0x47530000 0x0 0x10000>; 1420 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1421 #mbox-cells = <2>; 1422 status = "disabled"; 1423 }; 1424 1425 elemu2: mailbox@47540000 { 1426 compatible = "fsl,imx95-mu-ele"; 1427 reg = <0x0 0x47540000 0x0 0x10000>; 1428 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1429 #mbox-cells = <2>; 1430 status = "disabled"; 1431 }; 1432 1433 elemu3: mailbox@47550000 { 1434 compatible = "fsl,imx95-mu-ele"; 1435 reg = <0x0 0x47550000 0x0 0x10000>; 1436 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1437 #mbox-cells = <2>; 1438 }; 1439 1440 elemu4: mailbox@47560000 { 1441 compatible = "fsl,imx95-mu-ele"; 1442 reg = <0x0 0x47560000 0x0 0x10000>; 1443 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1444 #mbox-cells = <2>; 1445 status = "disabled"; 1446 }; 1447 1448 elemu5: mailbox@47570000 { 1449 compatible = "fsl,imx95-mu-ele"; 1450 reg = <0x0 0x47570000 0x0 0x10000>; 1451 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1452 #mbox-cells = <2>; 1453 status = "disabled"; 1454 }; 1455 1456 aips4: bus@49000000 { 1457 compatible = "fsl,aips-bus", "simple-bus"; 1458 reg = <0x0 0x49000000 0x0 0x800000>; 1459 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1460 #address-cells = <1>; 1461 #size-cells = <1>; 1462 1463 smmu: iommu@490d0000 { 1464 compatible = "arm,smmu-v3"; 1465 reg = <0x490d0000 0x100000>; 1466 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1467 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1468 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1469 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1470 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1471 #iommu-cells = <1>; 1472 status = "disabled"; 1473 }; 1474 }; 1475 1476 pcie0: pcie@4c300000 { 1477 compatible = "fsl,imx95-pcie"; 1478 reg = <0 0x4c300000 0 0x10000>, 1479 <0 0x60100000 0 0xfe00000>, 1480 <0 0x4c360000 0 0x10000>, 1481 <0 0x4c340000 0 0x2000>; 1482 reg-names = "dbi", "config", "atu", "app"; 1483 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1484 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1485 #address-cells = <3>; 1486 #size-cells = <2>; 1487 device_type = "pci"; 1488 linux,pci-domain = <0>; 1489 bus-range = <0x00 0xff>; 1490 num-lanes = <1>; 1491 num-viewport = <8>; 1492 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1493 interrupt-names = "msi"; 1494 #interrupt-cells = <1>; 1495 interrupt-map-mask = <0 0 0 0x7>; 1496 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1497 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1498 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1499 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1501 <&scmi_clk IMX95_CLK_HSIOPLL>, 1502 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1503 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1504 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1505 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1506 <&scmi_clk IMX95_CLK_HSIOPLL>, 1507 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1508 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1509 assigned-clock-parents = <0>, <0>, 1510 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1511 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1512 fsl,max-link-speed = <3>; 1513 status = "disabled"; 1514 }; 1515 1516 pcie0_ep: pcie-ep@4c300000 { 1517 compatible = "fsl,imx95-pcie-ep"; 1518 reg = <0 0x4c300000 0 0x10000>, 1519 <0 0x4c360000 0 0x1000>, 1520 <0 0x4c320000 0 0x1000>, 1521 <0 0x4c340000 0 0x2000>, 1522 <0 0x4c370000 0 0x10000>, 1523 <0x9 0 1 0>; 1524 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1525 num-lanes = <1>; 1526 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1527 interrupt-names = "dma"; 1528 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1529 <&scmi_clk IMX95_CLK_HSIOPLL>, 1530 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1531 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1532 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1533 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1534 <&scmi_clk IMX95_CLK_HSIOPLL>, 1535 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1536 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1537 assigned-clock-parents = <0>, <0>, 1538 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1539 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1540 status = "disabled"; 1541 }; 1542 1543 pcie1: pcie@4c380000 { 1544 compatible = "fsl,imx95-pcie"; 1545 reg = <0 0x4c380000 0 0x10000>, 1546 <8 0x80100000 0 0xfe00000>, 1547 <0 0x4c3e0000 0 0x10000>, 1548 <0 0x4c3c0000 0 0x2000>; 1549 reg-names = "dbi", "config", "atu", "app"; 1550 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1551 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1552 #address-cells = <3>; 1553 #size-cells = <2>; 1554 device_type = "pci"; 1555 linux,pci-domain = <1>; 1556 bus-range = <0x00 0xff>; 1557 num-lanes = <1>; 1558 num-viewport = <8>; 1559 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "msi"; 1561 #interrupt-cells = <1>; 1562 interrupt-map-mask = <0 0 0 0x7>; 1563 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1564 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1565 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1566 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1568 <&scmi_clk IMX95_CLK_HSIOPLL>, 1569 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1570 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1571 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1572 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1573 <&scmi_clk IMX95_CLK_HSIOPLL>, 1574 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1575 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1576 assigned-clock-parents = <0>, <0>, 1577 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1578 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1579 fsl,max-link-speed = <3>; 1580 status = "disabled"; 1581 }; 1582 1583 pcie1_ep: pcie-ep@4c380000 { 1584 compatible = "fsl,imx95-pcie-ep"; 1585 reg = <0 0x4c380000 0 0x10000>, 1586 <0 0x4c3e0000 0 0x1000>, 1587 <0 0x4c3a0000 0 0x1000>, 1588 <0 0x4c3c0000 0 0x2000>, 1589 <0 0x4c3f0000 0 0x10000>, 1590 <0xa 0 1 0>; 1591 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1592 num-lanes = <1>; 1593 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1594 interrupt-names = "dma"; 1595 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1596 <&scmi_clk IMX95_CLK_HSIOPLL>, 1597 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1598 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1599 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1600 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1601 <&scmi_clk IMX95_CLK_HSIOPLL>, 1602 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1603 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1604 assigned-clock-parents = <0>, <0>, 1605 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1606 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1607 status = "disabled"; 1608 }; 1609 1610 netcmix_blk_ctrl: syscon@4c810000 { 1611 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 1612 reg = <0x0 0x4c810000 0x0 0x10000>; 1613 #clock-cells = <1>; 1614 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1615 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1616 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1617 assigned-clock-rates = <133333333>; 1618 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1619 status = "disabled"; 1620 }; 1621 1622 sai2: sai@4c880000 { 1623 compatible = "fsl,imx95-sai"; 1624 reg = <0x0 0x4c880000 0x0 0x10000>; 1625 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 1627 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 1628 <&dummy>; 1629 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1630 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1631 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1632 dma-names = "rx", "tx"; 1633 status = "disabled"; 1634 }; 1635 1636 ddr-pmu@4e090dc0 { 1637 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 1638 reg = <0x0 0x4e090dc0 0x0 0x200>; 1639 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1640 }; 1641 }; 1642}; 1643