1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include "imx95.dtsi" 10 11/ { 12 model = "NXP i.MX95 19X19 board"; 13 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 14 15 aliases { 16 mmc0 = &usdhc1; 17 mmc1 = &usdhc2; 18 serial0 = &lpuart1; 19 }; 20 21 bt_sco_codec: audio-codec-bt-sco { 22 #sound-dai-cells = <1>; 23 compatible = "linux,bt-sco"; 24 }; 25 26 chosen { 27 stdout-path = &lpuart1; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x0 0x80000000 0 0x80000000>; 33 }; 34 35 fan0: pwm-fan { 36 compatible = "pwm-fan"; 37 #cooling-cells = <2>; 38 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 39 cooling-levels = <64 128 192 255>; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 linux_cma: linux,cma { 48 compatible = "shared-dma-pool"; 49 alloc-ranges = <0 0x80000000 0 0x7f000000>; 50 size = <0 0x3c000000>; 51 linux,cma-default; 52 reusable; 53 }; 54 }; 55 56 reg_3p3v: regulator-3p3v { 57 compatible = "regulator-fixed"; 58 regulator-max-microvolt = <3300000>; 59 regulator-min-microvolt = <3300000>; 60 regulator-name = "+V3.3_SW"; 61 }; 62 63 reg_audio_pwr: regulator-audio-pwr { 64 compatible = "regulator-fixed"; 65 regulator-name = "audio-pwr"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 regulator-always-on; 71 }; 72 73 reg_audio_slot: regulator-audio-slot { 74 compatible = "regulator-fixed"; 75 regulator-name = "audio-wm8962"; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 regulator-always-on; 81 status = "disabled"; 82 }; 83 84 reg_m2_pwr: regulator-m2-pwr { 85 compatible = "regulator-fixed"; 86 regulator-name = "M.2-power"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 }; 92 93 reg_pcie0: regulator-pcie { 94 compatible = "regulator-fixed"; 95 regulator-name = "PCIE_WLAN_EN"; 96 regulator-min-microvolt = <3300000>; 97 regulator-max-microvolt = <3300000>; 98 vin-supply = <®_m2_pwr>; 99 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 100 enable-active-high; 101 }; 102 103 reg_slot_pwr: regulator-slot-pwr { 104 compatible = "regulator-fixed"; 105 regulator-name = "PCIe slot-power"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 }; 111 112 reg_usdhc2_vmmc: regulator-usdhc2 { 113 compatible = "regulator-fixed"; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 116 regulator-name = "VDD_SD2_3V3"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 120 enable-active-high; 121 off-on-delay-us = <12000>; 122 }; 123 124 sound-bt-sco { 125 compatible = "simple-audio-card"; 126 simple-audio-card,name = "bt-sco-audio"; 127 simple-audio-card,format = "dsp_a"; 128 simple-audio-card,bitclock-inversion; 129 simple-audio-card,frame-master = <&btcpu>; 130 simple-audio-card,bitclock-master = <&btcpu>; 131 132 btcpu: simple-audio-card,cpu { 133 sound-dai = <&sai1>; 134 dai-tdm-slot-num = <2>; 135 dai-tdm-slot-width = <16>; 136 }; 137 138 simple-audio-card,codec { 139 sound-dai = <&bt_sco_codec 1>; 140 }; 141 }; 142 143 sound-micfil { 144 compatible = "fsl,imx-audio-card"; 145 model = "micfil-audio"; 146 147 pri-dai-link { 148 link-name = "micfil hifi"; 149 format = "i2s"; 150 cpu { 151 sound-dai = <&micfil>; 152 }; 153 }; 154 }; 155 156 sound-wm8962 { 157 compatible = "fsl,imx-audio-wm8962"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_hp>; 160 model = "wm8962-audio"; 161 audio-cpu = <&sai3>; 162 audio-codec = <&wm8962>; 163 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 164 audio-routing = "Headphone Jack", "HPOUTL", 165 "Headphone Jack", "HPOUTR", 166 "Ext Spk", "SPKOUTL", 167 "Ext Spk", "SPKOUTR", 168 "AMIC", "MICBIAS", 169 "IN3R", "AMIC", 170 "IN1R", "AMIC"; 171 }; 172}; 173 174&flexspi1 { 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_flexspi1>; 177 status = "okay"; 178 179 flash@0 { 180 compatible = "jedec,spi-nor"; 181 reg = <0>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_flexspi1_reset>; 184 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 spi-max-frequency = <200000000>; 188 spi-tx-bus-width = <8>; 189 spi-rx-bus-width = <8>; 190 }; 191}; 192 193&lpi2c4 { 194 clock-frequency = <400000>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_lpi2c4>; 197 status = "okay"; 198 199 wm8962: audio-codec@1a { 200 compatible = "wlf,wm8962"; 201 reg = <0x1a>; 202 clocks = <&scmi_clk IMX95_CLK_SAI3>; 203 DCVDD-supply = <®_audio_pwr>; 204 DBVDD-supply = <®_audio_pwr>; 205 AVDD-supply = <®_audio_pwr>; 206 CPVDD-supply = <®_audio_pwr>; 207 MICVDD-supply = <®_audio_pwr>; 208 PLLVDD-supply = <®_audio_pwr>; 209 SPKVDD1-supply = <®_audio_pwr>; 210 SPKVDD2-supply = <®_audio_pwr>; 211 gpio-cfg = < 0x0000 /* 0:Default */ 212 0x0000 /* 1:Default */ 213 0x0000 /* 2:FN_DMICCLK */ 214 0x0000 /* 3:Default */ 215 0x0000 /* 4:FN_DMICCDAT */ 216 0x0000 /* 5:Default */ 217 >; 218 }; 219 220 i2c4_gpio_expander_21: gpio@21 { 221 compatible = "nxp,pcal6408"; 222 reg = <0x21>; 223 #gpio-cells = <2>; 224 gpio-controller; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 interrupt-parent = <&gpio2>; 228 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 231 vcc-supply = <®_3p3v>; 232 }; 233}; 234 235&lpi2c7 { 236 clock-frequency = <1000000>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_lpi2c7>; 239 status = "okay"; 240 241 i2c7_pcal6524: i2c7-gpio@22 { 242 compatible = "nxp,pcal6524"; 243 reg = <0x22>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 interrupt-parent = <&gpio5>; 251 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 252 }; 253}; 254 255&lpuart1 { 256 /* console */ 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart1>; 259 status = "okay"; 260}; 261 262&micfil { 263 #sound-dai-cells = <0>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_pdm>; 266 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 267 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 268 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 269 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 270 <&scmi_clk IMX95_CLK_PDM>; 271 assigned-clock-parents = <0>, <0>, <0>, <0>, 272 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 273 assigned-clock-rates = <3932160000>, 274 <3612672000>, <393216000>, 275 <361267200>, <49152000>; 276 status = "okay"; 277}; 278 279&mu7 { 280 status = "okay"; 281}; 282 283&pcie0 { 284 pinctrl-0 = <&pinctrl_pcie0>; 285 pinctrl-names = "default"; 286 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 287 vpcie-supply = <®_pcie0>; 288 status = "okay"; 289}; 290 291&pcie1 { 292 pinctrl-0 = <&pinctrl_pcie1>; 293 pinctrl-names = "default"; 294 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 295 vpcie-supply = <®_slot_pwr>; 296 status = "okay"; 297}; 298 299&sai1 { 300 #sound-dai-cells = <0>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_sai1>; 303 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 304 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 305 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 306 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 307 <&scmi_clk IMX95_CLK_SAI1>; 308 assigned-clock-parents = <0>, <0>, <0>, <0>, 309 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 310 assigned-clock-rates = <3932160000>, 311 <3612672000>, <393216000>, 312 <361267200>, <12288000>; 313 fsl,sai-mclk-direction-output; 314 status = "okay"; 315}; 316 317&sai3 { 318 #sound-dai-cells = <0>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_sai3>; 321 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 322 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 323 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 324 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 325 <&scmi_clk IMX95_CLK_SAI3>; 326 assigned-clock-parents = <0>, <0>, <0>, <0>, 327 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 328 assigned-clock-rates = <3932160000>, 329 <3612672000>, <393216000>, 330 <361267200>, <12288000>; 331 fsl,sai-mclk-direction-output; 332 status = "okay"; 333}; 334 335&usdhc1 { 336 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 337 pinctrl-0 = <&pinctrl_usdhc1>; 338 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 339 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 340 pinctrl-3 = <&pinctrl_usdhc1>; 341 bus-width = <8>; 342 non-removable; 343 no-sdio; 344 no-sd; 345 status = "okay"; 346}; 347 348&usdhc2 { 349 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 350 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 351 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 352 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 353 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 354 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 355 vmmc-supply = <®_usdhc2_vmmc>; 356 bus-width = <4>; 357 status = "okay"; 358}; 359 360&wdog3 { 361 fsl,ext-reset-output; 362 status = "okay"; 363}; 364 365&scmi_iomuxc { 366 pinctrl_flexspi1: flexspi1grp { 367 fsl,pins = < 368 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe 369 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe 370 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe 371 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe 372 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe 373 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe 374 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe 375 IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe 376 IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe 377 IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe 378 IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe 379 >; 380 }; 381 382 pinctrl_flexspi1_reset: flexspi1-reset-grp { 383 fsl,pins = < 384 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe 385 >; 386 }; 387 388 pinctrl_hp: hpgrp { 389 fsl,pins = < 390 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 391 >; 392 }; 393 394 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 395 fsl,pins = < 396 IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e 397 >; 398 }; 399 400 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 401 fsl,pins = < 402 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 403 >; 404 }; 405 406 pinctrl_lpi2c4: lpi2c4grp { 407 fsl,pins = < 408 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 409 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 410 >; 411 }; 412 413 pinctrl_lpi2c7: lpi2c7grp { 414 fsl,pins = < 415 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 416 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 417 >; 418 }; 419 420 pinctrl_pcie0: pcie0grp { 421 fsl,pins = < 422 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 423 >; 424 }; 425 426 pinctrl_pcie1: pcie1grp { 427 fsl,pins = < 428 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 429 >; 430 }; 431 432 pinctrl_pdm: pdmgrp { 433 fsl,pins = < 434 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 435 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 436 >; 437 }; 438 439 pinctrl_sai1: sai1grp { 440 fsl,pins = < 441 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 442 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 443 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 444 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 445 >; 446 }; 447 448 pinctrl_sai2: sai2grp { 449 fsl,pins = < 450 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 451 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 452 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 453 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 454 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 455 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 456 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 457 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 458 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 459 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 460 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 461 >; 462 }; 463 464 pinctrl_sai3: sai3grp { 465 fsl,pins = < 466 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 467 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 468 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 469 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 470 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 471 >; 472 }; 473 474 pinctrl_tpm6: tpm6grp { 475 fsl,pins = < 476 IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e 477 >; 478 }; 479 480 pinctrl_uart1: uart1grp { 481 fsl,pins = < 482 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 483 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 484 >; 485 }; 486 487 pinctrl_usdhc1: usdhc1grp { 488 fsl,pins = < 489 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 490 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 491 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 492 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 493 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 494 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 495 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 496 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 497 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 498 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 499 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 500 >; 501 }; 502 503 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 504 fsl,pins = < 505 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 506 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 507 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 508 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 509 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 510 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 511 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 512 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 513 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 514 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 515 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 516 >; 517 }; 518 519 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 520 fsl,pins = < 521 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 522 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 523 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 524 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 525 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 526 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 527 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 528 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 529 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 530 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 531 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 532 >; 533 }; 534 535 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 536 fsl,pins = < 537 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 538 >; 539 }; 540 541 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 542 fsl,pins = < 543 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 544 >; 545 }; 546 547 pinctrl_usdhc2: usdhc2grp { 548 fsl,pins = < 549 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 550 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 551 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 552 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 553 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 554 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 555 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 556 >; 557 }; 558 559 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 560 fsl,pins = < 561 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 562 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 563 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 564 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 565 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 566 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 567 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 568 >; 569 }; 570 571 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 572 fsl,pins = < 573 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 574 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 575 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 576 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 577 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 578 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 579 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 580 >; 581 }; 582}; 583 584&thermal_zones { 585 a55-thermal { 586 trips { 587 atrip2: trip2 { 588 temperature = <55000>; 589 hysteresis = <2000>; 590 type = "active"; 591 }; 592 593 atrip3: trip3 { 594 temperature = <65000>; 595 hysteresis = <2000>; 596 type = "active"; 597 }; 598 599 atrip4: trip4 { 600 temperature = <75000>; 601 hysteresis = <2000>; 602 type = "active"; 603 }; 604 }; 605 606 cooling-maps { 607 map1 { 608 trip = <&atrip2>; 609 cooling-device = <&fan0 0 1>; 610 }; 611 612 map2 { 613 trip = <&atrip3>; 614 cooling-device = <&fan0 1 2>; 615 }; 616 617 map3 { 618 trip = <&atrip4>; 619 cooling-device = <&fan0 2 3>; 620 }; 621 }; 622 }; 623}; 624 625&tpm6 { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_tpm6>; 628 status = "okay"; 629}; 630