1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include "imx95.dtsi" 10 11#define FALLING_EDGE 1 12#define RISING_EDGE 2 13 14#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 15#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 16#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 17#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 18#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 19 20/ { 21 model = "NXP i.MX95 19X19 board"; 22 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &lpi2c1; 31 i2c1 = &lpi2c2; 32 i2c2 = &lpi2c3; 33 i2c3 = &lpi2c4; 34 i2c4 = &lpi2c5; 35 i2c5 = &lpi2c6; 36 i2c6 = &lpi2c7; 37 i2c7 = &lpi2c8; 38 mmc0 = &usdhc1; 39 mmc1 = &usdhc2; 40 serial0 = &lpuart1; 41 }; 42 43 bt_sco_codec: audio-codec-bt-sco { 44 #sound-dai-cells = <1>; 45 compatible = "linux,bt-sco"; 46 }; 47 48 chosen { 49 stdout-path = &lpuart1; 50 }; 51 52 memory@80000000 { 53 device_type = "memory"; 54 reg = <0x0 0x80000000 0 0x80000000>; 55 }; 56 57 fan0: pwm-fan { 58 compatible = "pwm-fan"; 59 #cooling-cells = <2>; 60 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 61 cooling-levels = <64 128 192 255>; 62 }; 63 64 reserved-memory { 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 linux_cma: linux,cma { 70 compatible = "shared-dma-pool"; 71 alloc-ranges = <0 0x80000000 0 0x7f000000>; 72 size = <0 0x3c000000>; 73 linux,cma-default; 74 reusable; 75 }; 76 }; 77 78 reg_3p3v: regulator-3p3v { 79 compatible = "regulator-fixed"; 80 regulator-max-microvolt = <3300000>; 81 regulator-min-microvolt = <3300000>; 82 regulator-name = "+V3.3_SW"; 83 }; 84 85 reg_audio_pwr: regulator-audio-pwr { 86 compatible = "regulator-fixed"; 87 regulator-name = "audio-pwr"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 regulator-always-on; 93 }; 94 95 reg_audio_slot: regulator-audio-slot { 96 compatible = "regulator-fixed"; 97 regulator-name = "audio-wm8962"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>; 101 enable-active-high; 102 regulator-always-on; 103 status = "disabled"; 104 }; 105 106 reg_m2_pwr: regulator-m2-pwr { 107 compatible = "regulator-fixed"; 108 regulator-name = "M.2-power"; 109 regulator-min-microvolt = <3300000>; 110 regulator-max-microvolt = <3300000>; 111 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 112 enable-active-high; 113 }; 114 115 reg_pcie0: regulator-pcie { 116 compatible = "regulator-fixed"; 117 regulator-name = "PCIE_WLAN_EN"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 vin-supply = <®_m2_pwr>; 121 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 122 enable-active-high; 123 }; 124 125 reg_slot_pwr: regulator-slot-pwr { 126 compatible = "regulator-fixed"; 127 regulator-name = "PCIe slot-power"; 128 regulator-min-microvolt = <3300000>; 129 regulator-max-microvolt = <3300000>; 130 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 131 enable-active-high; 132 }; 133 134 reg_usdhc2_vmmc: regulator-usdhc2 { 135 compatible = "regulator-fixed"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 138 regulator-name = "VDD_SD2_3V3"; 139 regulator-min-microvolt = <3300000>; 140 regulator-max-microvolt = <3300000>; 141 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 142 enable-active-high; 143 off-on-delay-us = <12000>; 144 }; 145 146 sound-bt-sco { 147 compatible = "simple-audio-card"; 148 simple-audio-card,name = "bt-sco-audio"; 149 simple-audio-card,format = "dsp_a"; 150 simple-audio-card,bitclock-inversion; 151 simple-audio-card,frame-master = <&btcpu>; 152 simple-audio-card,bitclock-master = <&btcpu>; 153 154 btcpu: simple-audio-card,cpu { 155 sound-dai = <&sai1>; 156 dai-tdm-slot-num = <2>; 157 dai-tdm-slot-width = <16>; 158 }; 159 160 simple-audio-card,codec { 161 sound-dai = <&bt_sco_codec 1>; 162 }; 163 }; 164 165 sound-micfil { 166 compatible = "fsl,imx-audio-card"; 167 model = "micfil-audio"; 168 169 pri-dai-link { 170 link-name = "micfil hifi"; 171 format = "i2s"; 172 cpu { 173 sound-dai = <&micfil>; 174 }; 175 }; 176 }; 177 178 sound-wm8962 { 179 compatible = "fsl,imx-audio-wm8962"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_hp>; 182 model = "wm8962-audio"; 183 audio-cpu = <&sai3>; 184 audio-codec = <&wm8962>; 185 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 186 audio-routing = "Headphone Jack", "HPOUTL", 187 "Headphone Jack", "HPOUTR", 188 "Ext Spk", "SPKOUTL", 189 "Ext Spk", "SPKOUTR", 190 "AMIC", "MICBIAS", 191 "IN3R", "AMIC", 192 "IN1R", "AMIC"; 193 }; 194}; 195 196&flexspi1 { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_flexspi1>; 199 status = "okay"; 200 201 flash@0 { 202 compatible = "jedec,spi-nor"; 203 reg = <0>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_flexspi1_reset>; 206 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 spi-max-frequency = <200000000>; 210 spi-tx-bus-width = <8>; 211 spi-rx-bus-width = <8>; 212 }; 213}; 214 215&lpi2c4 { 216 clock-frequency = <400000>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_lpi2c4>; 219 status = "okay"; 220 221 wm8962: audio-codec@1a { 222 compatible = "wlf,wm8962"; 223 reg = <0x1a>; 224 clocks = <&scmi_clk IMX95_CLK_SAI3>; 225 DCVDD-supply = <®_audio_pwr>; 226 DBVDD-supply = <®_audio_pwr>; 227 AVDD-supply = <®_audio_pwr>; 228 CPVDD-supply = <®_audio_pwr>; 229 MICVDD-supply = <®_audio_pwr>; 230 PLLVDD-supply = <®_audio_pwr>; 231 SPKVDD1-supply = <®_audio_pwr>; 232 SPKVDD2-supply = <®_audio_pwr>; 233 gpio-cfg = < 0x0000 /* 0:Default */ 234 0x0000 /* 1:Default */ 235 0x0000 /* 2:FN_DMICCLK */ 236 0x0000 /* 3:Default */ 237 0x0000 /* 4:FN_DMICCDAT */ 238 0x0000 /* 5:Default */ 239 >; 240 }; 241 242 i2c4_gpio_expander_21: gpio@21 { 243 compatible = "nxp,pcal6408"; 244 reg = <0x21>; 245 #gpio-cells = <2>; 246 gpio-controller; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 interrupt-parent = <&gpio2>; 250 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 253 vcc-supply = <®_3p3v>; 254 }; 255}; 256 257&lpi2c5 { 258 clock-frequency = <100000>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_lpi2c5>; 261 status = "okay"; 262 263 i2c5_pcal6408: gpio@21 { 264 compatible = "nxp,pcal6408"; 265 reg = <0x21>; 266 gpio-controller; 267 #gpio-cells = <2>; 268 vcc-supply = <®_3p3v>; 269 }; 270}; 271 272&lpi2c6 { 273 clock-frequency = <100000>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_lpi2c6>; 276 status = "okay"; 277 278 i2c6_pcal6416: gpio@21 { 279 compatible = "nxp,pcal6416"; 280 reg = <0x21>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 interrupt-parent = <&gpio4>; 286 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_pcal6416>; 289 vcc-supply = <®_3p3v>; 290 }; 291}; 292 293&lpi2c7 { 294 clock-frequency = <1000000>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_lpi2c7>; 297 status = "okay"; 298 299 i2c7_pcal6524: i2c7-gpio@22 { 300 compatible = "nxp,pcal6524"; 301 reg = <0x22>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 interrupt-parent = <&gpio5>; 309 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 310 }; 311}; 312 313&lpuart1 { 314 /* console */ 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_uart1>; 317 status = "okay"; 318}; 319 320&micfil { 321 #sound-dai-cells = <0>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_pdm>; 324 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 325 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 326 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 327 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 328 <&scmi_clk IMX95_CLK_PDM>; 329 assigned-clock-parents = <0>, <0>, <0>, <0>, 330 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 331 assigned-clock-rates = <3932160000>, 332 <3612672000>, <393216000>, 333 <361267200>, <49152000>; 334 status = "okay"; 335}; 336 337&mu7 { 338 status = "okay"; 339}; 340 341&pcie0 { 342 pinctrl-0 = <&pinctrl_pcie0>; 343 pinctrl-names = "default"; 344 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 345 vpcie-supply = <®_pcie0>; 346 status = "okay"; 347}; 348 349&pcie1 { 350 pinctrl-0 = <&pinctrl_pcie1>; 351 pinctrl-names = "default"; 352 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 353 vpcie-supply = <®_slot_pwr>; 354 status = "okay"; 355}; 356 357&sai1 { 358 #sound-dai-cells = <0>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_sai1>; 361 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 362 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 363 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 364 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 365 <&scmi_clk IMX95_CLK_SAI1>; 366 assigned-clock-parents = <0>, <0>, <0>, <0>, 367 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 368 assigned-clock-rates = <3932160000>, 369 <3612672000>, <393216000>, 370 <361267200>, <12288000>; 371 fsl,sai-mclk-direction-output; 372 status = "okay"; 373}; 374 375&sai3 { 376 #sound-dai-cells = <0>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_sai3>; 379 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 380 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 381 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 382 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 383 <&scmi_clk IMX95_CLK_SAI3>; 384 assigned-clock-parents = <0>, <0>, <0>, <0>, 385 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 386 assigned-clock-rates = <3932160000>, 387 <3612672000>, <393216000>, 388 <361267200>, <12288000>; 389 fsl,sai-mclk-direction-output; 390 status = "okay"; 391}; 392 393&usdhc1 { 394 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 395 pinctrl-0 = <&pinctrl_usdhc1>; 396 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 397 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 398 pinctrl-3 = <&pinctrl_usdhc1>; 399 bus-width = <8>; 400 non-removable; 401 no-sdio; 402 no-sd; 403 status = "okay"; 404}; 405 406&usdhc2 { 407 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 408 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 409 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 410 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 411 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 412 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 413 vmmc-supply = <®_usdhc2_vmmc>; 414 bus-width = <4>; 415 status = "okay"; 416}; 417 418&scmi_misc { 419 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 420 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 421 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 422 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 423 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 424}; 425 426&wdog3 { 427 fsl,ext-reset-output; 428 status = "okay"; 429}; 430 431&scmi_iomuxc { 432 pinctrl_flexspi1: flexspi1grp { 433 fsl,pins = < 434 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe 435 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe 436 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe 437 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe 438 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe 439 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe 440 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe 441 IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe 442 IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe 443 IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe 444 IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe 445 >; 446 }; 447 448 pinctrl_flexspi1_reset: flexspi1-reset-grp { 449 fsl,pins = < 450 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe 451 >; 452 }; 453 454 pinctrl_hp: hpgrp { 455 fsl,pins = < 456 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 457 >; 458 }; 459 460 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 461 fsl,pins = < 462 IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e 463 >; 464 }; 465 466 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 467 fsl,pins = < 468 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 469 >; 470 }; 471 472 pinctrl_lpi2c4: lpi2c4grp { 473 fsl,pins = < 474 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 475 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 476 >; 477 }; 478 479 pinctrl_lpi2c5: lpi2c5grp { 480 fsl,pins = < 481 IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 482 IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 483 >; 484 }; 485 486 pinctrl_lpi2c6: lpi2c6grp { 487 fsl,pins = < 488 IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 489 IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 490 >; 491 }; 492 493 pinctrl_lpi2c7: lpi2c7grp { 494 fsl,pins = < 495 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 496 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 497 >; 498 }; 499 500 pinctrl_pcie0: pcie0grp { 501 fsl,pins = < 502 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 503 >; 504 }; 505 506 pinctrl_pcie1: pcie1grp { 507 fsl,pins = < 508 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 509 >; 510 }; 511 512 pinctrl_pcal6416: pcal6416grp { 513 fsl,pins = < 514 IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 515 >; 516 }; 517 518 pinctrl_pdm: pdmgrp { 519 fsl,pins = < 520 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 521 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 522 >; 523 }; 524 525 pinctrl_sai1: sai1grp { 526 fsl,pins = < 527 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 528 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 529 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 530 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 531 >; 532 }; 533 534 pinctrl_sai2: sai2grp { 535 fsl,pins = < 536 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 537 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 538 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 539 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 540 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 541 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 542 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 543 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 544 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 545 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 546 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 547 >; 548 }; 549 550 pinctrl_sai3: sai3grp { 551 fsl,pins = < 552 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 553 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 554 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 555 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 556 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 557 >; 558 }; 559 560 pinctrl_tpm6: tpm6grp { 561 fsl,pins = < 562 IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e 563 >; 564 }; 565 566 pinctrl_uart1: uart1grp { 567 fsl,pins = < 568 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 569 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 570 >; 571 }; 572 573 pinctrl_usdhc1: usdhc1grp { 574 fsl,pins = < 575 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 576 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 577 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 578 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 579 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 580 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 581 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 582 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 583 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 584 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 585 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 586 >; 587 }; 588 589 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 590 fsl,pins = < 591 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 592 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 593 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 594 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 595 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 596 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 597 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 598 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 599 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 600 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 601 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 602 >; 603 }; 604 605 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 606 fsl,pins = < 607 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 608 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 609 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 610 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 611 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 612 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 613 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 614 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 615 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 616 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 617 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 618 >; 619 }; 620 621 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 622 fsl,pins = < 623 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 624 >; 625 }; 626 627 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 628 fsl,pins = < 629 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 630 >; 631 }; 632 633 pinctrl_usdhc2: usdhc2grp { 634 fsl,pins = < 635 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 636 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 637 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 638 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 639 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 640 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 641 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 642 >; 643 }; 644 645 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 646 fsl,pins = < 647 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 648 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 649 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 650 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 651 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 652 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 653 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 654 >; 655 }; 656 657 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 658 fsl,pins = < 659 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 660 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 661 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 662 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 663 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 664 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 665 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 666 >; 667 }; 668}; 669 670&thermal_zones { 671 a55-thermal { 672 trips { 673 atrip2: trip2 { 674 temperature = <55000>; 675 hysteresis = <2000>; 676 type = "active"; 677 }; 678 679 atrip3: trip3 { 680 temperature = <65000>; 681 hysteresis = <2000>; 682 type = "active"; 683 }; 684 685 atrip4: trip4 { 686 temperature = <75000>; 687 hysteresis = <2000>; 688 type = "active"; 689 }; 690 }; 691 692 cooling-maps { 693 map1 { 694 trip = <&atrip2>; 695 cooling-device = <&fan0 0 1>; 696 }; 697 698 map2 { 699 trip = <&atrip3>; 700 cooling-device = <&fan0 1 2>; 701 }; 702 703 map3 { 704 trip = <&atrip4>; 705 cooling-device = <&fan0 2 3>; 706 }; 707 }; 708 }; 709}; 710 711&tpm6 { 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pinctrl_tpm6>; 714 status = "okay"; 715}; 716