1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024-2025 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx943.dtsi" 9 10/ { 11 compatible = "fsl,imx943-evk", "fsl,imx94"; 12 model = "NXP i.MX943 EVK board"; 13 14 aliases { 15 mmc0 = &usdhc1; 16 mmc1 = &usdhc2; 17 serial0 = &lpuart1; 18 }; 19 20 chosen { 21 stdout-path = &lpuart1; 22 }; 23 24 reg_usdhc2_vmmc: regulator-usdhc2 { 25 compatible = "regulator-fixed"; 26 off-on-delay-us = <12000>; 27 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 28 pinctrl-names = "default"; 29 regulator-max-microvolt = <3300000>; 30 regulator-min-microvolt = <3300000>; 31 regulator-name = "VDD_SD2_3V3"; 32 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 33 enable-active-high; 34 }; 35 36 reserved-memory { 37 ranges; 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 linux,cma { 42 compatible = "shared-dma-pool"; 43 alloc-ranges = <0 0x80000000 0 0x7f000000>; 44 reusable; 45 size = <0 0x10000000>; 46 linux,cma-default; 47 }; 48 }; 49 50 memory@80000000 { 51 reg = <0x0 0x80000000 0x0 0x80000000>; 52 device_type = "memory"; 53 }; 54}; 55 56&lpuart1 { 57 pinctrl-0 = <&pinctrl_uart1>; 58 pinctrl-names = "default"; 59 status = "okay"; 60}; 61 62&scmi_iomuxc { 63 pinctrl_uart1: uart1grp { 64 fsl,pins = < 65 IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e 66 IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e 67 >; 68 }; 69 70 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 71 fsl,pins = < 72 IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e 73 IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e 74 IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 75 IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 76 IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 77 IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 78 IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 79 IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 80 IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 81 IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 82 IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 83 >; 84 }; 85 86 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 87 fsl,pins = < 88 IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe 89 IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe 90 IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 91 IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 92 IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 93 IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 94 IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 95 IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 96 IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 97 IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 98 IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 99 >; 100 }; 101 102 pinctrl_usdhc1: usdhc1grp { 103 fsl,pins = < 104 IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e 105 IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e 106 IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 107 IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 108 IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 109 IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 110 IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 111 IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 112 IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 113 IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 114 IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 115 >; 116 }; 117 118 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 119 fsl,pins = < 120 IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e 121 IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e 122 IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 123 IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 124 IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 125 IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 126 IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 127 >; 128 }; 129 130 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 131 fsl,pins = < 132 IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe 133 IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe 134 IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 135 IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 136 IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 137 IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 138 IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 139 >; 140 }; 141 142 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 143 fsl,pins = < 144 IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e 145 >; 146 }; 147 148 pinctrl_usdhc2: usdhc2grp { 149 fsl,pins = < 150 IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e 151 IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e 152 IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 153 IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 154 IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 155 IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 156 IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 157 >; 158 }; 159 160 pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { 161 fsl,pins = < 162 IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e 163 >; 164 }; 165}; 166 167&usdhc1 { 168 pinctrl-0 = <&pinctrl_usdhc1>; 169 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 170 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 171 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 172 bus-width = <8>; 173 non-removable; 174 no-sdio; 175 no-sd; 176 status = "okay"; 177}; 178 179&usdhc2 { 180 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 181 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 182 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 183 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 184 bus-width = <4>; 185 no-mmc; 186 no-sdio; 187 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 188 vmmc-supply = <®_usdhc2_vmmc>; 189 status = "okay"; 190}; 191 192&wdog3 { 193 fsl,ext-reset-output; 194 status = "okay"; 195}; 196