xref: /linux/arch/arm64/boot/dts/freescale/imx943-evk.dts (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2024-2025 NXP
4 */
5
6/dts-v1/;
7
8#include "imx943.dtsi"
9
10/ {
11	compatible = "fsl,imx943-evk", "fsl,imx94";
12	model = "NXP i.MX943 EVK board";
13
14	aliases {
15		i2c2 = &lpi2c3;
16		i2c3 = &lpi2c4;
17		i2c5 = &lpi2c6;
18		mmc0 = &usdhc1;
19		mmc1 = &usdhc2;
20		serial0 = &lpuart1;
21	};
22
23	bt_sco_codec: bt-sco-codec {
24		compatible = "linux,bt-sco";
25		#sound-dai-cells = <1>;
26	};
27
28	chosen {
29		stdout-path = &lpuart1;
30	};
31
32	dmic: dmic {
33		compatible = "dmic-codec";
34		#sound-dai-cells = <0>;
35	};
36
37	reg_usdhc2_vmmc: regulator-usdhc2 {
38		compatible = "regulator-fixed";
39		off-on-delay-us = <12000>;
40		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
41		pinctrl-names = "default";
42		regulator-max-microvolt = <3300000>;
43		regulator-min-microvolt = <3300000>;
44		regulator-name = "VDD_SD2_3V3";
45		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
46		enable-active-high;
47	};
48
49	reg_audio_pwr: regulator-wm8962-pwr {
50		compatible = "regulator-fixed";
51		regulator-max-microvolt = <3300000>;
52		regulator-min-microvolt = <3300000>;
53		regulator-name = "audio-pwr";
54		gpio = <&pcal6416_i2c3_u171 12 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	reserved-memory {
59		ranges;
60		#address-cells = <2>;
61		#size-cells = <2>;
62
63		linux,cma {
64			compatible = "shared-dma-pool";
65			alloc-ranges = <0 0x80000000 0 0x7f000000>;
66			reusable;
67			size = <0 0x10000000>;
68			linux,cma-default;
69		};
70	};
71
72	sound-bt-sco {
73		compatible = "simple-audio-card";
74		simple-audio-card,bitclock-inversion;
75		simple-audio-card,bitclock-master = <&btcpu>;
76		simple-audio-card,format = "dsp_a";
77		simple-audio-card,frame-master = <&btcpu>;
78		simple-audio-card,name = "bt-sco-audio";
79
80		simple-audio-card,codec {
81			sound-dai = <&bt_sco_codec 1>;
82		};
83
84		btcpu: simple-audio-card,cpu {
85			dai-tdm-slot-num = <2>;
86			dai-tdm-slot-width = <16>;
87			sound-dai = <&sai3>;
88		};
89	};
90
91	sound-micfil {
92		compatible = "fsl,imx-audio-card";
93		model = "micfil-audio";
94
95		pri-dai-link {
96			format = "i2s";
97			link-name = "micfil hifi";
98
99			codec {
100				sound-dai = <&dmic>;
101			};
102
103			cpu {
104				sound-dai = <&micfil>;
105			};
106		};
107	};
108
109	sound-wm8962 {
110		compatible = "fsl,imx-audio-wm8962";
111		audio-codec = <&wm8962>;
112		audio-cpu = <&sai1>;
113		audio-routing = "Headphone Jack", "HPOUTL",
114			"Headphone Jack", "HPOUTR",
115			"Ext Spk", "SPKOUTL",
116			"Ext Spk", "SPKOUTR",
117			"AMIC", "MICBIAS",
118			"IN3R", "AMIC",
119			"IN1R", "AMIC";
120		hp-det-gpio = <&pcal6416_i2c3_u48 14 GPIO_ACTIVE_HIGH>;
121		model = "wm8962-audio";
122	};
123
124	memory@80000000 {
125		reg = <0x0 0x80000000 0x0 0x80000000>;
126		device_type = "memory";
127	};
128};
129
130&lpi2c3 {
131	clock-frequency = <400000>;
132	pinctrl-0 = <&pinctrl_lpi2c3>;
133	pinctrl-names = "default";
134	status = "okay";
135
136	pca9670_i2c3: gpio@23 {
137		compatible = "nxp,pca9670";
138		reg = <0x23>;
139		#gpio-cells = <2>;
140		gpio-controller;
141	};
142
143	pca9548_i2c3: i2c-mux@77 {
144		compatible = "nxp,pca9548";
145		reg = <0x77>;
146		#address-cells = <1>;
147		#size-cells = <0>;
148
149		i2c@0 {
150			reg = <0>;
151			#address-cells = <1>;
152			#size-cells = <0>;
153		};
154
155		i2c@1 {
156			reg = <1>;
157			#address-cells = <1>;
158			#size-cells = <0>;
159		};
160
161		i2c@2 {
162			reg = <2>;
163			#address-cells = <1>;
164			#size-cells = <0>;
165		};
166
167		i2c@3 {
168			reg = <3>;
169			#address-cells = <1>;
170			#size-cells = <0>;
171		};
172
173		i2c@4 {
174			reg = <4>;
175			#address-cells = <1>;
176			#size-cells = <0>;
177
178			wm8962: codec@1a {
179				compatible = "wlf,wm8962";
180				reg = <0x1a>;
181				clocks = <&scmi_clk IMX94_CLK_SAI1>;
182				AVDD-supply = <&reg_audio_pwr>;
183				CPVDD-supply = <&reg_audio_pwr>;
184				DBVDD-supply = <&reg_audio_pwr>;
185				DCVDD-supply = <&reg_audio_pwr>;
186				gpio-cfg = <
187					0x0000 /* 0:Default */
188					0x0000 /* 1:Default */
189					0x0000 /* 2:FN_DMICCLK */
190					0x0000 /* 3:Default */
191					0x0000 /* 4:FN_DMICCDAT */
192					0x0000 /* 5:Default */
193				>;
194				MICVDD-supply = <&reg_audio_pwr>;
195				PLLVDD-supply = <&reg_audio_pwr>;
196				SPKVDD1-supply = <&reg_audio_pwr>;
197				SPKVDD2-supply = <&reg_audio_pwr>;
198			};
199		};
200
201		i2c@5 {
202			reg = <5>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205
206			pcal6416_i2c3_u46: gpio@20 {
207				compatible = "nxp,pcal6416";
208				reg = <0x20>;
209				#gpio-cells = <2>;
210				gpio-controller;
211
212				sd-card-on-hog {
213					gpios = <13 GPIO_ACTIVE_HIGH>;
214					gpio-hog;
215					output-high;
216				};
217			};
218
219			pcal6416_i2c3_u171: gpio@21 {
220				compatible = "nxp,pcal6416";
221				reg = <0x21>;
222				#gpio-cells = <2>;
223				gpio-controller;
224
225				audio-pwren-hog {
226					gpios = <12 GPIO_ACTIVE_HIGH>;
227					gpio-hog;
228					output-high;
229				};
230
231				mqs-mic-sel-hog {
232					gpios = <11 GPIO_ACTIVE_HIGH>;
233					gpio-hog;
234					output-low;
235				};
236			};
237		};
238
239		i2c@6 {
240			reg = <6>;
241			#address-cells = <1>;
242			#size-cells = <0>;
243
244			pcal6416_i2c3_u48: gpio@20 {
245				compatible = "nxp,pcal6416";
246				reg = <0x20>;
247				#interrupt-cells = <2>;
248				interrupt-controller;
249				interrupt-parent = <&gpio3>;
250				interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
251				#gpio-cells = <2>;
252				gpio-controller;
253				pinctrl-0 = <&pinctrl_ioexpander_int>;
254				pinctrl-names = "default";
255			};
256		};
257
258		i2c@7 {
259			reg = <7>;
260			#address-cells = <1>;
261			#size-cells = <0>;
262
263			pcal6408_i2c3_u172: gpio@20 {
264				compatible = "nxp,pcal6408";
265				reg = <0x20>;
266				#interrupt-cells = <2>;
267				interrupt-controller;
268				interrupt-parent = <&gpio3>;
269				/* shared int pin with u48 */
270				interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
271				#gpio-cells = <2>;
272				gpio-controller;
273			};
274		};
275	};
276};
277
278&lpi2c4 {
279	clock-frequency = <400000>;
280	pinctrl-0 = <&pinctrl_lpi2c4>;
281	pinctrl-names = "default";
282	status = "okay";
283};
284
285&lpi2c6 {
286	clock-frequency = <400000>;
287	pinctrl-0 = <&pinctrl_lpi2c6>;
288	pinctrl-names = "default";
289	status = "okay";
290
291	pca9544_i2c6: i2c-mux@77 {
292		compatible = "nxp,pca9544";
293		reg = <0x77>;
294		#address-cells = <1>;
295		#size-cells = <0>;
296
297		i2c@0 {
298			reg = <0>;
299			#address-cells = <1>;
300			#size-cells = <0>;
301		};
302
303		i2c@1 {
304			reg = <1>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307
308			pcal6416_i2c6_u50: gpio@21 {
309				compatible = "nxp,pcal6416";
310				reg = <0x21>;
311				#gpio-cells = <2>;
312				gpio-controller;
313			};
314		};
315
316		i2c@2 {
317			reg = <2>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320
321			pcal6408_i2c6_u170: gpio@20 {
322				compatible = "nxp,pcal6408";
323				reg = <0x20>;
324				#interrupt-cells = <2>;
325				interrupt-controller;
326				interrupt-parent = <&gpio4>;
327				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
328				#gpio-cells = <2>;
329				gpio-controller;
330				pinctrl-0 = <&pinctrl_ioexpander_int2>;
331				pinctrl-names = "default";
332			};
333		};
334
335		i2c@3 {
336			reg = <3>;
337			#address-cells = <1>;
338			#size-cells = <0>;
339
340			pcal6416_i2c6_u44: gpio@20 {
341				compatible = "nxp,pcal6416";
342				reg = <0x20>;
343				#gpio-cells = <2>;
344				gpio-controller;
345
346				/* pdm selection */
347				can-pdm-sel-hog {
348					gpios = <12 GPIO_ACTIVE_HIGH>;
349					gpio-hog;
350					output-low;
351				};
352
353				sai3-sel-hog {
354					gpios = <11 GPIO_ACTIVE_HIGH>;
355					gpio-hog;
356					output-high;
357				};
358
359				/* eMMC IOMUX selection */
360				sd1-sel-hog {
361					gpios = <0 GPIO_ACTIVE_HIGH>;
362					gpio-hog;
363					output-high;
364				};
365
366				/* SD card IOMUX selection */
367				sd2-sel-hog {
368					gpios = <1 GPIO_ACTIVE_HIGH>;
369					gpio-hog;
370					output-high;
371				};
372			};
373		};
374	};
375};
376
377&lpuart1 {
378	pinctrl-0 = <&pinctrl_uart1>;
379	pinctrl-names = "default";
380	status = "okay";
381};
382
383&micfil {
384	assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
385			  <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
386			  <&scmi_clk IMX94_CLK_AUDIOPLL1>,
387			  <&scmi_clk IMX94_CLK_AUDIOPLL2>,
388			  <&scmi_clk IMX94_CLK_PDM>;
389	assigned-clock-parents = <0>, <0>, <0>, <0>,
390				 <&scmi_clk IMX94_CLK_AUDIOPLL1>;
391	assigned-clock-rates = <3932160000>,
392			       <3612672000>, <393216000>,
393			       <361267200>, <49152000>;
394	pinctrl-0 = <&pinctrl_pdm>;
395	pinctrl-names = "default";
396	status = "okay";
397};
398
399&sai1 {
400	assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
401			  <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
402			  <&scmi_clk IMX94_CLK_AUDIOPLL1>,
403			  <&scmi_clk IMX94_CLK_AUDIOPLL2>,
404			  <&scmi_clk IMX94_CLK_SAI1>;
405	assigned-clock-parents = <0>, <0>, <0>, <0>,
406				 <&scmi_clk IMX94_CLK_AUDIOPLL1>;
407	assigned-clock-rates = <3932160000>,
408			       <3612672000>, <393216000>,
409			       <361267200>, <12288000>;
410	pinctrl-0 = <&pinctrl_sai1>;
411	pinctrl-names = "default";
412	fsl,sai-mclk-direction-output;
413	status = "okay";
414};
415
416&sai3 {
417	assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
418			  <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
419			  <&scmi_clk IMX94_CLK_AUDIOPLL1>,
420			  <&scmi_clk IMX94_CLK_AUDIOPLL2>,
421			  <&scmi_clk IMX94_CLK_SAI3>;
422	assigned-clock-parents = <0>, <0>, <0>, <0>,
423				 <&scmi_clk IMX94_CLK_AUDIOPLL1>;
424	assigned-clock-rates = <3932160000>,
425			       <3612672000>, <393216000>,
426			       <361267200>, <12288000>;
427	pinctrl-0 = <&pinctrl_sai3>;
428	pinctrl-names = "default";
429	fsl,sai-mclk-direction-output;
430	status = "okay";
431};
432
433&scmi_iomuxc {
434
435	pinctrl_ioexpander_int2: ioexpanderint2grp {
436		fsl,pins = <
437			IMX94_PAD_CCM_CLKO4__GPIO4_IO3		0x31e
438		>;
439	};
440
441	pinctrl_ioexpander_int: ioexpanderintgrp {
442		fsl,pins = <
443			IMX94_PAD_GPIO_IO45__GPIO3_IO13		0x31e
444		>;
445	};
446
447	pinctrl_lpi2c3: lpi2c3grp {
448		fsl,pins = <
449			IMX94_PAD_GPIO_IO16__LPI2C3_SDA		0x40000b9e
450			IMX94_PAD_GPIO_IO17__LPI2C3_SCL		0x40000b9e
451		>;
452	};
453
454	pinctrl_lpi2c4: lpi2c4grp {
455		fsl,pins = <
456			IMX94_PAD_GPIO_IO18__LPI2C4_SDA		0x40000b9e
457			IMX94_PAD_GPIO_IO19__LPI2C4_SCL		0x40000b9e
458		>;
459	};
460
461	pinctrl_lpi2c6: lpi2c6grp {
462		fsl,pins = <
463			IMX94_PAD_GPIO_IO29__LPI2C6_SDA		0x40000b9e
464			IMX94_PAD_GPIO_IO28__LPI2C6_SCL		0x40000b9e
465		>;
466	};
467
468	pinctrl_pdm: pdmgrp {
469		fsl,pins = <
470			IMX94_PAD_PDM_CLK__PDM_CLK			0x31e
471			IMX94_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0	0x31e
472			IMX94_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1	0x31e
473		>;
474	};
475
476	pinctrl_sai1: sai1grp {
477		fsl,pins = <
478			IMX94_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e
479			IMX94_PAD_SAI1_TXC__SAI1_TX_BCLK	0x31e
480			IMX94_PAD_SAI1_TXD0__SAI1_TX_DATA0	0x31e
481			IMX94_PAD_SAI1_RXD0__SAI1_RX_DATA0	0x31e
482			IMX94_PAD_I2C2_SDA__SAI1_MCLK		0x31e
483		>;
484	};
485
486	pinctrl_sai3: sai3grp {
487		fsl,pins = <
488			IMX94_PAD_GPIO_IO42__SAI3_TX_BCLK	0x31e
489			IMX94_PAD_GPIO_IO56__SAI3_TX_SYNC	0x31e
490			IMX94_PAD_GPIO_IO46__SAI3_RX_DATA0	0x31e
491			IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0	0x31e
492		>;
493	};
494
495	pinctrl_uart1: uart1grp {
496		fsl,pins = <
497			IMX94_PAD_UART1_TXD__LPUART1_TX		0x31e
498			IMX94_PAD_UART1_RXD__LPUART1_RX		0x31e
499		>;
500	};
501
502	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
503		fsl,pins = <
504			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e
505			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e
506			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
507			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
508			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
509			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
510			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
511			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
512			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
513			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
514			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
515		>;
516	};
517
518	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
519		fsl,pins = <
520			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x15fe
521			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x13fe
522			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
523			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
524			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
525			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
526			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
527			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
528			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
529			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
530			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
531		>;
532	};
533
534	pinctrl_usdhc1: usdhc1grp {
535		fsl,pins = <
536			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e
537			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e
538			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
539			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
540			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
541			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
542			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
543			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
544			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
545			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
546			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
547		>;
548	};
549
550	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
551		fsl,pins = <
552			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e
553			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e
554			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
555			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
556			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
557			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
558			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
559		>;
560	};
561
562	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
563		fsl,pins = <
564			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x15fe
565			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x13fe
566			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
567			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
568			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
569			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
570			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
571		>;
572	};
573
574	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
575		fsl,pins = <
576			IMX94_PAD_SD2_CD_B__GPIO4_IO20		0x31e
577		>;
578	};
579
580	pinctrl_usdhc2: usdhc2grp {
581		fsl,pins = <
582			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e
583			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e
584			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
585			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
586			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
587			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
588			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
589		>;
590	};
591
592	pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp {
593		fsl,pins = <
594			IMX94_PAD_SD2_RESET_B__GPIO4_IO27	0x31e
595		>;
596	};
597};
598
599&usdhc1 {
600	pinctrl-0 = <&pinctrl_usdhc1>;
601	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
602	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
603	pinctrl-names = "default", "state_100mhz", "state_200mhz";
604	bus-width = <8>;
605	non-removable;
606	no-sdio;
607	no-sd;
608	status = "okay";
609};
610
611&usdhc2 {
612	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
613	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
614	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
615	pinctrl-names = "default", "state_100mhz", "state_200mhz";
616	bus-width = <4>;
617	no-mmc;
618	no-sdio;
619	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
620	vmmc-supply = <&reg_usdhc2_vmmc>;
621	status = "okay";
622};
623
624&wdog3 {
625	fsl,ext-reset-output;
626	status = "okay";
627};
628