1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/fsl,imx93-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx93-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 i2c2 = &lpi2c3; 29 i2c3 = &lpi2c4; 30 i2c4 = &lpi2c5; 31 i2c5 = &lpi2c6; 32 i2c6 = &lpi2c7; 33 i2c7 = &lpi2c8; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 mmc2 = &usdhc3; 37 serial0 = &lpuart1; 38 serial1 = &lpuart2; 39 serial2 = &lpuart3; 40 serial3 = &lpuart4; 41 serial4 = &lpuart5; 42 serial5 = &lpuart6; 43 serial6 = &lpuart7; 44 serial7 = &lpuart8; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 idle-states { 52 entry-method = "psci"; 53 54 cpu_pd_wait: cpu-pd-wait { 55 compatible = "arm,idle-state"; 56 arm,psci-suspend-param = <0x0010033>; 57 local-timer-stop; 58 entry-latency-us = <10000>; 59 exit-latency-us = <7000>; 60 min-residency-us = <27000>; 61 wakeup-latency-us = <15000>; 62 }; 63 }; 64 65 A55_0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a55"; 68 reg = <0x0>; 69 enable-method = "psci"; 70 #cooling-cells = <2>; 71 cpu-idle-states = <&cpu_pd_wait>; 72 }; 73 74 A55_1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a55"; 77 reg = <0x100>; 78 enable-method = "psci"; 79 #cooling-cells = <2>; 80 cpu-idle-states = <&cpu_pd_wait>; 81 }; 82 83 }; 84 85 osc_32k: clock-osc-32k { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <32768>; 89 clock-output-names = "osc_32k"; 90 }; 91 92 osc_24m: clock-osc-24m { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <24000000>; 96 clock-output-names = "osc_24m"; 97 }; 98 99 clk_ext1: clock-ext1 { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <133000000>; 103 clock-output-names = "clk_ext1"; 104 }; 105 106 pmu { 107 compatible = "arm,cortex-a55-pmu"; 108 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 122 clock-frequency = <24000000>; 123 arm,no-tick-in-suspend; 124 interrupt-parent = <&gic>; 125 }; 126 127 gic: interrupt-controller@48000000 { 128 compatible = "arm,gic-v3"; 129 reg = <0 0x48000000 0 0x10000>, 130 <0 0x48040000 0 0xc0000>; 131 #interrupt-cells = <3>; 132 interrupt-controller; 133 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-parent = <&gic>; 135 }; 136 137 thermal-zones { 138 cpu-thermal { 139 polling-delay-passive = <250>; 140 polling-delay = <2000>; 141 142 thermal-sensors = <&tmu 0>; 143 144 trips { 145 cpu_alert: cpu-alert { 146 temperature = <80000>; 147 hysteresis = <2000>; 148 type = "passive"; 149 }; 150 151 cpu_crit: cpu-crit { 152 temperature = <90000>; 153 hysteresis = <2000>; 154 type = "critical"; 155 }; 156 }; 157 158 cooling-maps { 159 map0 { 160 trip = <&cpu_alert>; 161 cooling-device = 162 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 164 }; 165 }; 166 }; 167 }; 168 169 cm33: remoteproc-cm33 { 170 compatible = "fsl,imx93-cm33"; 171 clocks = <&clk IMX93_CLK_CM33_GATE>; 172 status = "disabled"; 173 }; 174 175 mqs1: mqs1 { 176 compatible = "fsl,imx93-mqs"; 177 gpr = <&aonmix_ns_gpr>; 178 status = "disabled"; 179 }; 180 181 mqs2: mqs2 { 182 compatible = "fsl,imx93-mqs"; 183 gpr = <&wakeupmix_gpr>; 184 status = "disabled"; 185 }; 186 187 usbphynop1: usbphynop1 { 188 compatible = "usb-nop-xceiv"; 189 #phy-cells = <0>; 190 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 191 clock-names = "main_clk"; 192 }; 193 194 usbphynop2: usbphynop2 { 195 compatible = "usb-nop-xceiv"; 196 #phy-cells = <0>; 197 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 198 clock-names = "main_clk"; 199 }; 200 201 soc@0 { 202 compatible = "simple-bus"; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges = <0x0 0x0 0x0 0x80000000>, 206 <0x28000000 0x0 0x28000000 0x10000000>; 207 208 aips1: bus@44000000 { 209 compatible = "fsl,aips-bus", "simple-bus"; 210 reg = <0x44000000 0x800000>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 edma1: dma-controller@44000000 { 216 compatible = "fsl,imx93-edma3"; 217 reg = <0x44000000 0x200000>; 218 #dma-cells = <3>; 219 dma-channels = <31>; 220 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved 221 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 222 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved 223 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 224 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 225 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus 226 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus 227 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX 228 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX 229 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX 230 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX 231 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX 232 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX 233 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX 234 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX 235 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 236 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX 237 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX 238 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX 239 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX 240 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 241 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX 242 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX 243 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 244 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 245 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow 246 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 247 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 248 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow 249 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM 250 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 251 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 252 clock-names = "dma"; 253 }; 254 255 aonmix_ns_gpr: syscon@44210000 { 256 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 257 reg = <0x44210000 0x1000>; 258 }; 259 260 mu1: mailbox@44230000 { 261 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 262 reg = <0x44230000 0x10000>; 263 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 265 #mbox-cells = <2>; 266 status = "disabled"; 267 }; 268 269 system_counter: timer@44290000 { 270 compatible = "nxp,sysctr-timer"; 271 reg = <0x44290000 0x30000>; 272 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&osc_24m>; 274 clock-names = "per"; 275 nxp,no-divider; 276 }; 277 278 wdog1: watchdog@442d0000 { 279 compatible = "fsl,imx93-wdt"; 280 reg = <0x442d0000 0x10000>; 281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clk IMX93_CLK_WDOG1_GATE>; 283 timeout-sec = <40>; 284 status = "disabled"; 285 }; 286 287 wdog2: watchdog@442e0000 { 288 compatible = "fsl,imx93-wdt"; 289 reg = <0x442e0000 0x10000>; 290 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX93_CLK_WDOG2_GATE>; 292 timeout-sec = <40>; 293 status = "disabled"; 294 }; 295 296 tpm1: pwm@44310000 { 297 compatible = "fsl,imx7ulp-pwm"; 298 reg = <0x44310000 0x1000>; 299 clocks = <&clk IMX93_CLK_TPM1_GATE>; 300 #pwm-cells = <3>; 301 status = "disabled"; 302 }; 303 304 tpm2: pwm@44320000 { 305 compatible = "fsl,imx7ulp-pwm"; 306 reg = <0x44320000 0x10000>; 307 clocks = <&clk IMX93_CLK_TPM2_GATE>; 308 #pwm-cells = <3>; 309 status = "disabled"; 310 }; 311 312 i3c1: i3c@44330000 { 313 compatible = "silvaco,i3c-master-v1"; 314 reg = <0x44330000 0x10000>; 315 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <3>; 317 #size-cells = <0>; 318 clocks = <&clk IMX93_CLK_BUS_AON>, 319 <&clk IMX93_CLK_I3C1_GATE>, 320 <&clk IMX93_CLK_I3C1_SLOW>; 321 clock-names = "pclk", "fast_clk", "slow_clk"; 322 status = "disabled"; 323 }; 324 325 lpi2c1: i2c@44340000 { 326 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 327 reg = <0x44340000 0x10000>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 332 <&clk IMX93_CLK_BUS_AON>; 333 clock-names = "per", "ipg"; 334 dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; 335 dma-names = "tx", "rx"; 336 status = "disabled"; 337 }; 338 339 lpi2c2: i2c@44350000 { 340 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 341 reg = <0x44350000 0x10000>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 346 <&clk IMX93_CLK_BUS_AON>; 347 clock-names = "per", "ipg"; 348 dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; 349 dma-names = "tx", "rx"; 350 status = "disabled"; 351 }; 352 353 lpspi1: spi@44360000 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 357 reg = <0x44360000 0x10000>; 358 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 360 <&clk IMX93_CLK_BUS_AON>; 361 clock-names = "per", "ipg"; 362 dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; 363 dma-names = "tx", "rx"; 364 status = "disabled"; 365 }; 366 367 lpspi2: spi@44370000 { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 371 reg = <0x44370000 0x10000>; 372 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 374 <&clk IMX93_CLK_BUS_AON>; 375 clock-names = "per", "ipg"; 376 dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; 377 dma-names = "tx", "rx"; 378 status = "disabled"; 379 }; 380 381 lpuart1: serial@44380000 { 382 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 383 reg = <0x44380000 0x1000>; 384 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 386 clock-names = "ipg"; 387 dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; 388 dma-names = "rx", "tx"; 389 status = "disabled"; 390 }; 391 392 lpuart2: serial@44390000 { 393 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 394 reg = <0x44390000 0x1000>; 395 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 397 clock-names = "ipg"; 398 dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 }; 402 403 flexcan1: can@443a0000 { 404 compatible = "fsl,imx93-flexcan"; 405 reg = <0x443a0000 0x10000>; 406 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clk IMX93_CLK_BUS_AON>, 408 <&clk IMX93_CLK_CAN1_GATE>; 409 clock-names = "ipg", "per"; 410 assigned-clocks = <&clk IMX93_CLK_CAN1>; 411 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 412 assigned-clock-rates = <40000000>; 413 fsl,clk-source = /bits/ 8 <0>; 414 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; 415 status = "disabled"; 416 }; 417 418 sai1: sai@443b0000 { 419 compatible = "fsl,imx93-sai"; 420 reg = <0x443b0000 0x10000>; 421 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 423 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 424 <&clk IMX93_CLK_DUMMY>; 425 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 426 dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; 427 dma-names = "rx", "tx"; 428 status = "disabled"; 429 }; 430 431 iomuxc: pinctrl@443c0000 { 432 compatible = "fsl,imx93-iomuxc"; 433 reg = <0x443c0000 0x10000>; 434 status = "okay"; 435 }; 436 437 bbnsm: bbnsm@44440000 { 438 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 439 reg = <0x44440000 0x10000>; 440 441 bbnsm_rtc: rtc { 442 compatible = "nxp,imx93-bbnsm-rtc"; 443 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 444 }; 445 446 bbnsm_pwrkey: pwrkey { 447 compatible = "nxp,imx93-bbnsm-pwrkey"; 448 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 449 linux,code = <KEY_POWER>; 450 }; 451 }; 452 453 clk: clock-controller@44450000 { 454 compatible = "fsl,imx93-ccm"; 455 reg = <0x44450000 0x10000>; 456 #clock-cells = <1>; 457 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 458 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 459 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; 460 assigned-clock-rates = <393216000>; 461 status = "okay"; 462 }; 463 464 src: system-controller@44460000 { 465 compatible = "fsl,imx93-src", "syscon"; 466 reg = <0x44460000 0x10000>; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 ranges; 470 471 mlmix: power-domain@44461800 { 472 compatible = "fsl,imx93-src-slice"; 473 reg = <0x44461800 0x400>, <0x44464800 0x400>; 474 #power-domain-cells = <0>; 475 clocks = <&clk IMX93_CLK_ML_APB>, 476 <&clk IMX93_CLK_ML>; 477 }; 478 479 mediamix: power-domain@44462400 { 480 compatible = "fsl,imx93-src-slice"; 481 reg = <0x44462400 0x400>, <0x44465800 0x400>; 482 #power-domain-cells = <0>; 483 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, 484 <&clk IMX93_CLK_MEDIA_APB>; 485 }; 486 }; 487 488 clock-controller@44480000 { 489 compatible = "fsl,imx93-anatop"; 490 reg = <0x44480000 0x2000>; 491 #clock-cells = <1>; 492 }; 493 494 tmu: tmu@44482000 { 495 compatible = "fsl,qoriq-tmu"; 496 reg = <0x44482000 0x1000>; 497 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk IMX93_CLK_TMC_GATE>; 499 little-endian; 500 fsl,tmu-range = <0x800000da 0x800000e9 501 0x80000102 0x8000012a 502 0x80000166 0x800001a7 503 0x800001b6>; 504 fsl,tmu-calibration = <0x00000000 0x0000000e 505 0x00000001 0x00000029 506 0x00000002 0x00000056 507 0x00000003 0x000000a2 508 0x00000004 0x00000116 509 0x00000005 0x00000195 510 0x00000006 0x000001b2>; 511 #thermal-sensor-cells = <1>; 512 }; 513 514 micfil: micfil@44520000 { 515 compatible = "fsl,imx93-micfil"; 516 reg = <0x44520000 0x10000>; 517 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX93_CLK_PDM_IPG>, 522 <&clk IMX93_CLK_PDM_GATE>, 523 <&clk IMX93_CLK_AUDIO_PLL>; 524 clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; 525 dmas = <&edma1 29 0 5>; 526 dma-names = "rx"; 527 status = "disabled"; 528 }; 529 530 adc1: adc@44530000 { 531 compatible = "nxp,imx93-adc"; 532 reg = <0x44530000 0x10000>; 533 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX93_CLK_ADC1_GATE>; 537 clock-names = "ipg"; 538 #io-channel-cells = <1>; 539 status = "disabled"; 540 }; 541 }; 542 543 aips2: bus@42000000 { 544 compatible = "fsl,aips-bus", "simple-bus"; 545 reg = <0x42000000 0x800000>; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 ranges; 549 550 edma2: dma-controller@42000000 { 551 compatible = "fsl,imx93-edma4"; 552 reg = <0x42000000 0x210000>; 553 #dma-cells = <3>; 554 dma-channels = <64>; 555 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clk IMX93_CLK_EDMA2_GATE>; 620 clock-names = "dma"; 621 }; 622 623 wakeupmix_gpr: syscon@42420000 { 624 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 625 reg = <0x42420000 0x1000>; 626 }; 627 628 mu2: mailbox@42440000 { 629 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 630 reg = <0x42440000 0x10000>; 631 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 633 #mbox-cells = <2>; 634 status = "disabled"; 635 }; 636 637 wdog3: watchdog@42490000 { 638 compatible = "fsl,imx93-wdt"; 639 reg = <0x42490000 0x10000>; 640 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clk IMX93_CLK_WDOG3_GATE>; 642 timeout-sec = <40>; 643 status = "disabled"; 644 }; 645 646 wdog4: watchdog@424a0000 { 647 compatible = "fsl,imx93-wdt"; 648 reg = <0x424a0000 0x10000>; 649 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&clk IMX93_CLK_WDOG4_GATE>; 651 timeout-sec = <40>; 652 status = "disabled"; 653 }; 654 655 wdog5: watchdog@424b0000 { 656 compatible = "fsl,imx93-wdt"; 657 reg = <0x424b0000 0x10000>; 658 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clk IMX93_CLK_WDOG5_GATE>; 660 timeout-sec = <40>; 661 status = "disabled"; 662 }; 663 664 tpm3: pwm@424e0000 { 665 compatible = "fsl,imx7ulp-pwm"; 666 reg = <0x424e0000 0x1000>; 667 clocks = <&clk IMX93_CLK_TPM3_GATE>; 668 #pwm-cells = <3>; 669 status = "disabled"; 670 }; 671 672 tpm4: pwm@424f0000 { 673 compatible = "fsl,imx7ulp-pwm"; 674 reg = <0x424f0000 0x10000>; 675 clocks = <&clk IMX93_CLK_TPM4_GATE>; 676 #pwm-cells = <3>; 677 status = "disabled"; 678 }; 679 680 tpm5: pwm@42500000 { 681 compatible = "fsl,imx7ulp-pwm"; 682 reg = <0x42500000 0x10000>; 683 clocks = <&clk IMX93_CLK_TPM5_GATE>; 684 #pwm-cells = <3>; 685 status = "disabled"; 686 }; 687 688 tpm6: pwm@42510000 { 689 compatible = "fsl,imx7ulp-pwm"; 690 reg = <0x42510000 0x10000>; 691 clocks = <&clk IMX93_CLK_TPM6_GATE>; 692 #pwm-cells = <3>; 693 status = "disabled"; 694 }; 695 696 i3c2: i3c@42520000 { 697 compatible = "silvaco,i3c-master-v1"; 698 reg = <0x42520000 0x10000>; 699 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 700 #address-cells = <3>; 701 #size-cells = <0>; 702 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 703 <&clk IMX93_CLK_I3C2_GATE>, 704 <&clk IMX93_CLK_I3C2_SLOW>; 705 clock-names = "pclk", "fast_clk", "slow_clk"; 706 status = "disabled"; 707 }; 708 709 lpi2c3: i2c@42530000 { 710 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 711 reg = <0x42530000 0x10000>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 716 <&clk IMX93_CLK_BUS_WAKEUP>; 717 clock-names = "per", "ipg"; 718 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 719 dma-names = "tx", "rx"; 720 status = "disabled"; 721 }; 722 723 lpi2c4: i2c@42540000 { 724 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 725 reg = <0x42540000 0x10000>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 730 <&clk IMX93_CLK_BUS_WAKEUP>; 731 clock-names = "per", "ipg"; 732 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 733 dma-names = "tx", "rx"; 734 status = "disabled"; 735 }; 736 737 lpspi3: spi@42550000 { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 741 reg = <0x42550000 0x10000>; 742 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 744 <&clk IMX93_CLK_BUS_WAKEUP>; 745 clock-names = "per", "ipg"; 746 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 747 dma-names = "tx", "rx"; 748 status = "disabled"; 749 }; 750 751 lpspi4: spi@42560000 { 752 #address-cells = <1>; 753 #size-cells = <0>; 754 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 755 reg = <0x42560000 0x10000>; 756 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 758 <&clk IMX93_CLK_BUS_WAKEUP>; 759 clock-names = "per", "ipg"; 760 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 761 dma-names = "tx", "rx"; 762 status = "disabled"; 763 }; 764 765 lpuart3: serial@42570000 { 766 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 767 reg = <0x42570000 0x1000>; 768 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 770 clock-names = "ipg"; 771 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 lpuart4: serial@42580000 { 777 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 778 reg = <0x42580000 0x1000>; 779 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 781 clock-names = "ipg"; 782 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 783 dma-names = "rx", "tx"; 784 status = "disabled"; 785 }; 786 787 lpuart5: serial@42590000 { 788 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 789 reg = <0x42590000 0x1000>; 790 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 792 clock-names = "ipg"; 793 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 794 dma-names = "rx", "tx"; 795 status = "disabled"; 796 }; 797 798 lpuart6: serial@425a0000 { 799 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 800 reg = <0x425a0000 0x1000>; 801 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 803 clock-names = "ipg"; 804 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 805 dma-names = "rx", "tx"; 806 status = "disabled"; 807 }; 808 809 flexcan2: can@425b0000 { 810 compatible = "fsl,imx93-flexcan"; 811 reg = <0x425b0000 0x10000>; 812 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 814 <&clk IMX93_CLK_CAN2_GATE>; 815 clock-names = "ipg", "per"; 816 assigned-clocks = <&clk IMX93_CLK_CAN2>; 817 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 818 assigned-clock-rates = <40000000>; 819 fsl,clk-source = /bits/ 8 <0>; 820 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; 821 status = "disabled"; 822 }; 823 824 flexspi1: spi@425e0000 { 825 compatible = "nxp,imx8mm-fspi"; 826 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 827 reg-names = "fspi_base", "fspi_mmap"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 832 <&clk IMX93_CLK_FLEXSPI1_GATE>; 833 clock-names = "fspi_en", "fspi"; 834 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 835 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 836 status = "disabled"; 837 }; 838 839 sai2: sai@42650000 { 840 compatible = "fsl,imx93-sai"; 841 reg = <0x42650000 0x10000>; 842 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, 844 <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, 845 <&clk IMX93_CLK_DUMMY>; 846 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 847 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 848 dma-names = "rx", "tx"; 849 status = "disabled"; 850 }; 851 852 sai3: sai@42660000 { 853 compatible = "fsl,imx93-sai"; 854 reg = <0x42660000 0x10000>; 855 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, 857 <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, 858 <&clk IMX93_CLK_DUMMY>; 859 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 860 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 861 dma-names = "rx", "tx"; 862 status = "disabled"; 863 }; 864 865 xcvr: xcvr@42680000 { 866 compatible = "fsl,imx93-xcvr"; 867 reg = <0x42680000 0x800>, 868 <0x42680800 0x400>, 869 <0x42680c00 0x080>, 870 <0x42680e00 0x080>; 871 reg-names = "ram", "regs", "rxfifo", "txfifo"; 872 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 875 <&clk IMX93_CLK_SPDIF_GATE>, 876 <&clk IMX93_CLK_DUMMY>, 877 <&clk IMX93_CLK_AUD_XCVR_GATE>; 878 clock-names = "ipg", "phy", "spba", "pll_ipg"; 879 dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; 880 dma-names = "rx", "tx"; 881 status = "disabled"; 882 }; 883 884 lpuart7: serial@42690000 { 885 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 886 reg = <0x42690000 0x1000>; 887 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 889 clock-names = "ipg"; 890 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 891 dma-names = "rx", "tx"; 892 status = "disabled"; 893 }; 894 895 lpuart8: serial@426a0000 { 896 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 897 reg = <0x426a0000 0x1000>; 898 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 900 clock-names = "ipg"; 901 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 902 dma-names = "rx", "tx"; 903 status = "disabled"; 904 }; 905 906 lpi2c5: i2c@426b0000 { 907 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 908 reg = <0x426b0000 0x10000>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 913 <&clk IMX93_CLK_BUS_WAKEUP>; 914 clock-names = "per", "ipg"; 915 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 916 dma-names = "tx", "rx"; 917 status = "disabled"; 918 }; 919 920 lpi2c6: i2c@426c0000 { 921 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 922 reg = <0x426c0000 0x10000>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 927 <&clk IMX93_CLK_BUS_WAKEUP>; 928 clock-names = "per", "ipg"; 929 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 930 dma-names = "tx", "rx"; 931 status = "disabled"; 932 }; 933 934 lpi2c7: i2c@426d0000 { 935 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 936 reg = <0x426d0000 0x10000>; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 941 <&clk IMX93_CLK_BUS_WAKEUP>; 942 clock-names = "per", "ipg"; 943 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 944 dma-names = "tx", "rx"; 945 status = "disabled"; 946 }; 947 948 lpi2c8: i2c@426e0000 { 949 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 950 reg = <0x426e0000 0x10000>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 955 <&clk IMX93_CLK_BUS_WAKEUP>; 956 clock-names = "per", "ipg"; 957 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 958 dma-names = "tx", "rx"; 959 status = "disabled"; 960 }; 961 962 lpspi5: spi@426f0000 { 963 #address-cells = <1>; 964 #size-cells = <0>; 965 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 966 reg = <0x426f0000 0x10000>; 967 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 969 <&clk IMX93_CLK_BUS_WAKEUP>; 970 clock-names = "per", "ipg"; 971 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 972 dma-names = "tx", "rx"; 973 status = "disabled"; 974 }; 975 976 lpspi6: spi@42700000 { 977 #address-cells = <1>; 978 #size-cells = <0>; 979 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 980 reg = <0x42700000 0x10000>; 981 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 983 <&clk IMX93_CLK_BUS_WAKEUP>; 984 clock-names = "per", "ipg"; 985 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 986 dma-names = "tx", "rx"; 987 status = "disabled"; 988 }; 989 990 lpspi7: spi@42710000 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 994 reg = <0x42710000 0x10000>; 995 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 997 <&clk IMX93_CLK_BUS_WAKEUP>; 998 clock-names = "per", "ipg"; 999 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1000 dma-names = "tx", "rx"; 1001 status = "disabled"; 1002 }; 1003 1004 lpspi8: spi@42720000 { 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1008 reg = <0x42720000 0x10000>; 1009 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 1011 <&clk IMX93_CLK_BUS_WAKEUP>; 1012 clock-names = "per", "ipg"; 1013 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1014 dma-names = "tx", "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 }; 1019 1020 aips3: bus@42800000 { 1021 compatible = "fsl,aips-bus", "simple-bus"; 1022 reg = <0x42800000 0x800000>; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 ranges; 1026 1027 usdhc1: mmc@42850000 { 1028 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1029 reg = <0x42850000 0x10000>; 1030 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1032 <&clk IMX93_CLK_WAKEUP_AXI>, 1033 <&clk IMX93_CLK_USDHC1_GATE>; 1034 clock-names = "ipg", "ahb", "per"; 1035 assigned-clocks = <&clk IMX93_CLK_USDHC1>; 1036 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1037 assigned-clock-rates = <400000000>; 1038 bus-width = <8>; 1039 fsl,tuning-start-tap = <1>; 1040 fsl,tuning-step = <2>; 1041 status = "disabled"; 1042 }; 1043 1044 usdhc2: mmc@42860000 { 1045 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1046 reg = <0x42860000 0x10000>; 1047 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1049 <&clk IMX93_CLK_WAKEUP_AXI>, 1050 <&clk IMX93_CLK_USDHC2_GATE>; 1051 clock-names = "ipg", "ahb", "per"; 1052 assigned-clocks = <&clk IMX93_CLK_USDHC2>; 1053 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1054 assigned-clock-rates = <400000000>; 1055 bus-width = <4>; 1056 fsl,tuning-start-tap = <1>; 1057 fsl,tuning-step = <2>; 1058 status = "disabled"; 1059 }; 1060 1061 fec: ethernet@42890000 { 1062 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1063 reg = <0x42890000 0x10000>; 1064 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clk IMX93_CLK_ENET1_GATE>, 1069 <&clk IMX93_CLK_ENET1_GATE>, 1070 <&clk IMX93_CLK_ENET_TIMER1>, 1071 <&clk IMX93_CLK_ENET_REF>, 1072 <&clk IMX93_CLK_ENET_REF_PHY>; 1073 clock-names = "ipg", "ahb", "ptp", 1074 "enet_clk_ref", "enet_out"; 1075 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 1076 <&clk IMX93_CLK_ENET_REF>, 1077 <&clk IMX93_CLK_ENET_REF_PHY>; 1078 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1079 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 1080 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1081 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 1082 fsl,num-tx-queues = <3>; 1083 fsl,num-rx-queues = <3>; 1084 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; 1085 nvmem-cells = <ð_mac1>; 1086 nvmem-cell-names = "mac-address"; 1087 status = "disabled"; 1088 }; 1089 1090 eqos: ethernet@428a0000 { 1091 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 1092 reg = <0x428a0000 0x10000>; 1093 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1095 interrupt-names = "macirq", "eth_wake_irq"; 1096 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 1097 <&clk IMX93_CLK_ENET_QOS_GATE>, 1098 <&clk IMX93_CLK_ENET_TIMER2>, 1099 <&clk IMX93_CLK_ENET>, 1100 <&clk IMX93_CLK_ENET_QOS_GATE>; 1101 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 1102 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 1103 <&clk IMX93_CLK_ENET>; 1104 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1105 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 1106 assigned-clock-rates = <100000000>, <250000000>; 1107 intf_mode = <&wakeupmix_gpr 0x28>; 1108 snps,clk-csr = <0>; 1109 nvmem-cells = <ð_mac2>; 1110 nvmem-cell-names = "mac-address"; 1111 status = "disabled"; 1112 }; 1113 1114 usdhc3: mmc@428b0000 { 1115 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1116 reg = <0x428b0000 0x10000>; 1117 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1119 <&clk IMX93_CLK_WAKEUP_AXI>, 1120 <&clk IMX93_CLK_USDHC3_GATE>; 1121 clock-names = "ipg", "ahb", "per"; 1122 assigned-clocks = <&clk IMX93_CLK_USDHC3>; 1123 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1124 assigned-clock-rates = <400000000>; 1125 bus-width = <4>; 1126 fsl,tuning-start-tap = <1>; 1127 fsl,tuning-step = <2>; 1128 status = "disabled"; 1129 }; 1130 }; 1131 1132 gpio2: gpio@43810000 { 1133 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1134 reg = <0x43810000 0x1000>; 1135 gpio-controller; 1136 #gpio-cells = <2>; 1137 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-controller; 1140 #interrupt-cells = <2>; 1141 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 1142 <&clk IMX93_CLK_GPIO2_GATE>; 1143 clock-names = "gpio", "port"; 1144 gpio-ranges = <&iomuxc 0 4 30>; 1145 }; 1146 1147 gpio3: gpio@43820000 { 1148 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1149 reg = <0x43820000 0x1000>; 1150 gpio-controller; 1151 #gpio-cells = <2>; 1152 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 1157 <&clk IMX93_CLK_GPIO3_GATE>; 1158 clock-names = "gpio", "port"; 1159 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 1160 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 1161 }; 1162 1163 gpio4: gpio@43830000 { 1164 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1165 reg = <0x43830000 0x1000>; 1166 gpio-controller; 1167 #gpio-cells = <2>; 1168 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1170 interrupt-controller; 1171 #interrupt-cells = <2>; 1172 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 1173 <&clk IMX93_CLK_GPIO4_GATE>; 1174 clock-names = "gpio", "port"; 1175 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 1176 }; 1177 1178 gpio1: gpio@47400000 { 1179 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1180 reg = <0x47400000 0x1000>; 1181 gpio-controller; 1182 #gpio-cells = <2>; 1183 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 1188 <&clk IMX93_CLK_GPIO1_GATE>; 1189 clock-names = "gpio", "port"; 1190 gpio-ranges = <&iomuxc 0 92 16>; 1191 }; 1192 1193 ocotp: efuse@47510000 { 1194 compatible = "fsl,imx93-ocotp", "syscon"; 1195 reg = <0x47510000 0x10000>; 1196 #address-cells = <1>; 1197 #size-cells = <1>; 1198 1199 eth_mac1: mac-address@4ec { 1200 reg = <0x4ec 0x6>; 1201 }; 1202 1203 eth_mac2: mac-address@4f2 { 1204 reg = <0x4f2 0x6>; 1205 }; 1206 1207 }; 1208 1209 s4muap: mailbox@47520000 { 1210 compatible = "fsl,imx93-mu-s4"; 1211 reg = <0x47520000 0x10000>; 1212 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1214 interrupt-names = "tx", "rx"; 1215 #mbox-cells = <2>; 1216 }; 1217 1218 media_blk_ctrl: system-controller@4ac10000 { 1219 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 1220 reg = <0x4ac10000 0x10000>; 1221 power-domains = <&mediamix>; 1222 clocks = <&clk IMX93_CLK_MEDIA_APB>, 1223 <&clk IMX93_CLK_MEDIA_AXI>, 1224 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 1225 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 1226 <&clk IMX93_CLK_CAM_PIX>, 1227 <&clk IMX93_CLK_PXP_GATE>, 1228 <&clk IMX93_CLK_LCDIF_GATE>, 1229 <&clk IMX93_CLK_ISI_GATE>, 1230 <&clk IMX93_CLK_MIPI_CSI_GATE>, 1231 <&clk IMX93_CLK_MIPI_DSI_GATE>; 1232 clock-names = "apb", "axi", "nic", "disp", "cam", 1233 "pxp", "lcdif", "isi", "csi", "dsi"; 1234 #power-domain-cells = <1>; 1235 status = "disabled"; 1236 }; 1237 1238 usbotg1: usb@4c100000 { 1239 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1240 reg = <0x4c100000 0x200>; 1241 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1243 <&clk IMX93_CLK_HSIO_32K_GATE>; 1244 clock-names = "usb_ctrl_root", "usb_wakeup"; 1245 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1246 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1247 assigned-clock-rates = <133000000>; 1248 phys = <&usbphynop1>; 1249 fsl,usbmisc = <&usbmisc1 0>; 1250 status = "disabled"; 1251 }; 1252 1253 usbmisc1: usbmisc@4c100200 { 1254 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1255 "fsl,imx6q-usbmisc"; 1256 reg = <0x4c100200 0x200>; 1257 #index-cells = <1>; 1258 }; 1259 1260 usbotg2: usb@4c200000 { 1261 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1262 reg = <0x4c200000 0x200>; 1263 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1265 <&clk IMX93_CLK_HSIO_32K_GATE>; 1266 clock-names = "usb_ctrl_root", "usb_wakeup"; 1267 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1268 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1269 assigned-clock-rates = <133000000>; 1270 phys = <&usbphynop2>; 1271 fsl,usbmisc = <&usbmisc2 0>; 1272 status = "disabled"; 1273 }; 1274 1275 usbmisc2: usbmisc@4c200200 { 1276 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1277 "fsl,imx6q-usbmisc"; 1278 reg = <0x4c200200 0x200>; 1279 #index-cells = <1>; 1280 }; 1281 1282 ddr-pmu@4e300dc0 { 1283 compatible = "fsl,imx93-ddr-pmu"; 1284 reg = <0x4e300dc0 0x200>; 1285 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1286 }; 1287 }; 1288}; 1289