1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/fsl,imx93-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx93-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 i2c2 = &lpi2c3; 29 i2c3 = &lpi2c4; 30 i2c4 = &lpi2c5; 31 i2c5 = &lpi2c6; 32 i2c6 = &lpi2c7; 33 i2c7 = &lpi2c8; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 mmc2 = &usdhc3; 37 serial0 = &lpuart1; 38 serial1 = &lpuart2; 39 serial2 = &lpuart3; 40 serial3 = &lpuart4; 41 serial4 = &lpuart5; 42 serial5 = &lpuart6; 43 serial6 = &lpuart7; 44 serial7 = &lpuart8; 45 spi0 = &lpspi1; 46 spi1 = &lpspi2; 47 spi2 = &lpspi3; 48 spi3 = &lpspi4; 49 spi4 = &lpspi5; 50 spi5 = &lpspi6; 51 spi6 = &lpspi7; 52 spi7 = &lpspi8; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 idle-states { 60 entry-method = "psci"; 61 62 cpu_pd_wait: cpu-pd-wait { 63 compatible = "arm,idle-state"; 64 arm,psci-suspend-param = <0x0010033>; 65 local-timer-stop; 66 entry-latency-us = <10000>; 67 exit-latency-us = <7000>; 68 min-residency-us = <27000>; 69 wakeup-latency-us = <15000>; 70 }; 71 }; 72 73 A55_0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a55"; 76 reg = <0x0>; 77 enable-method = "psci"; 78 #cooling-cells = <2>; 79 cpu-idle-states = <&cpu_pd_wait>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_cache_l0>; 87 }; 88 89 A55_1: cpu@100 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a55"; 92 reg = <0x100>; 93 enable-method = "psci"; 94 #cooling-cells = <2>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 i-cache-size = <32768>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <128>; 99 d-cache-size = <32768>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <128>; 102 next-level-cache = <&l2_cache_l1>; 103 }; 104 105 l2_cache_l0: l2-cache-l0 { 106 compatible = "cache"; 107 cache-size = <65536>; 108 cache-line-size = <64>; 109 cache-sets = <256>; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_cache>; 113 }; 114 115 l2_cache_l1: l2-cache-l1 { 116 compatible = "cache"; 117 cache-size = <65536>; 118 cache-line-size = <64>; 119 cache-sets = <256>; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_cache>; 123 }; 124 125 l3_cache: l3-cache { 126 compatible = "cache"; 127 cache-size = <262144>; 128 cache-line-size = <64>; 129 cache-sets = <256>; 130 cache-level = <3>; 131 cache-unified; 132 }; 133 }; 134 135 osc_32k: clock-osc-32k { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <32768>; 139 clock-output-names = "osc_32k"; 140 }; 141 142 osc_24m: clock-osc-24m { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <24000000>; 146 clock-output-names = "osc_24m"; 147 }; 148 149 clk_ext1: clock-ext1 { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <133000000>; 153 clock-output-names = "clk_ext1"; 154 }; 155 156 pmu { 157 compatible = "arm,cortex-a55-pmu"; 158 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 159 }; 160 161 psci { 162 compatible = "arm,psci-1.0"; 163 method = "smc"; 164 }; 165 166 timer { 167 compatible = "arm,armv8-timer"; 168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 172 clock-frequency = <24000000>; 173 arm,no-tick-in-suspend; 174 interrupt-parent = <&gic>; 175 }; 176 177 gic: interrupt-controller@48000000 { 178 compatible = "arm,gic-v3"; 179 reg = <0 0x48000000 0 0x10000>, 180 <0 0x48040000 0 0xc0000>; 181 #interrupt-cells = <3>; 182 interrupt-controller; 183 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-parent = <&gic>; 185 }; 186 187 thermal-zones { 188 cpu-thermal { 189 polling-delay-passive = <250>; 190 polling-delay = <2000>; 191 192 thermal-sensors = <&tmu 0>; 193 194 trips { 195 cpu_alert: cpu-alert { 196 temperature = <80000>; 197 hysteresis = <2000>; 198 type = "passive"; 199 }; 200 201 cpu_crit: cpu-crit { 202 temperature = <90000>; 203 hysteresis = <2000>; 204 type = "critical"; 205 }; 206 }; 207 208 cooling-maps { 209 map0 { 210 trip = <&cpu_alert>; 211 cooling-device = 212 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214 }; 215 }; 216 }; 217 }; 218 219 cm33: remoteproc-cm33 { 220 compatible = "fsl,imx93-cm33"; 221 clocks = <&clk IMX93_CLK_CM33_GATE>; 222 status = "disabled"; 223 }; 224 225 mqs1: mqs1 { 226 compatible = "fsl,imx93-mqs"; 227 gpr = <&aonmix_ns_gpr>; 228 status = "disabled"; 229 }; 230 231 mqs2: mqs2 { 232 compatible = "fsl,imx93-mqs"; 233 gpr = <&wakeupmix_gpr>; 234 status = "disabled"; 235 }; 236 237 usbphynop1: usbphynop1 { 238 compatible = "usb-nop-xceiv"; 239 #phy-cells = <0>; 240 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 241 clock-names = "main_clk"; 242 }; 243 244 usbphynop2: usbphynop2 { 245 compatible = "usb-nop-xceiv"; 246 #phy-cells = <0>; 247 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 248 clock-names = "main_clk"; 249 }; 250 251 soc@0 { 252 compatible = "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x0 0x0 0x80000000>, 256 <0x28000000 0x0 0x28000000 0x10000000>; 257 258 aips1: bus@44000000 { 259 compatible = "fsl,aips-bus", "simple-bus"; 260 reg = <0x44000000 0x800000>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges; 264 265 edma1: dma-controller@44000000 { 266 compatible = "fsl,imx93-edma3"; 267 reg = <0x44000000 0x200000>; 268 #dma-cells = <3>; 269 dma-channels = <31>; 270 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved 271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved 273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus 276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus 277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX 278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX 279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX 280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX 281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX 282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX 283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX 284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX 285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX 287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX 288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX 289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX 290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX 292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX 293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 294 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 295 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow 296 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 297 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 298 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow 299 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM 300 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 301 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 302 clock-names = "dma"; 303 }; 304 305 aonmix_ns_gpr: syscon@44210000 { 306 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 307 reg = <0x44210000 0x1000>; 308 }; 309 310 mu1: mailbox@44230000 { 311 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 312 reg = <0x44230000 0x10000>; 313 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 315 #mbox-cells = <2>; 316 status = "disabled"; 317 }; 318 319 system_counter: timer@44290000 { 320 compatible = "nxp,sysctr-timer"; 321 reg = <0x44290000 0x30000>; 322 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&osc_24m>; 324 clock-names = "per"; 325 nxp,no-divider; 326 }; 327 328 wdog1: watchdog@442d0000 { 329 compatible = "fsl,imx93-wdt"; 330 reg = <0x442d0000 0x10000>; 331 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX93_CLK_WDOG1_GATE>; 333 timeout-sec = <40>; 334 status = "disabled"; 335 }; 336 337 wdog2: watchdog@442e0000 { 338 compatible = "fsl,imx93-wdt"; 339 reg = <0x442e0000 0x10000>; 340 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clk IMX93_CLK_WDOG2_GATE>; 342 timeout-sec = <40>; 343 status = "disabled"; 344 }; 345 346 tpm1: pwm@44310000 { 347 compatible = "fsl,imx7ulp-pwm"; 348 reg = <0x44310000 0x1000>; 349 clocks = <&clk IMX93_CLK_TPM1_GATE>; 350 #pwm-cells = <3>; 351 status = "disabled"; 352 }; 353 354 tpm2: pwm@44320000 { 355 compatible = "fsl,imx7ulp-pwm"; 356 reg = <0x44320000 0x10000>; 357 clocks = <&clk IMX93_CLK_TPM2_GATE>; 358 #pwm-cells = <3>; 359 status = "disabled"; 360 }; 361 362 i3c1: i3c@44330000 { 363 compatible = "silvaco,i3c-master-v1"; 364 reg = <0x44330000 0x10000>; 365 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <3>; 367 #size-cells = <0>; 368 clocks = <&clk IMX93_CLK_BUS_AON>, 369 <&clk IMX93_CLK_I3C1_GATE>, 370 <&clk IMX93_CLK_I3C1_SLOW>; 371 clock-names = "pclk", "fast_clk", "slow_clk"; 372 status = "disabled"; 373 }; 374 375 lpi2c1: i2c@44340000 { 376 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 377 reg = <0x44340000 0x10000>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 382 <&clk IMX93_CLK_BUS_AON>; 383 clock-names = "per", "ipg"; 384 dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; 385 dma-names = "tx", "rx"; 386 status = "disabled"; 387 }; 388 389 lpi2c2: i2c@44350000 { 390 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 391 reg = <0x44350000 0x10000>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 396 <&clk IMX93_CLK_BUS_AON>; 397 clock-names = "per", "ipg"; 398 dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; 399 dma-names = "tx", "rx"; 400 status = "disabled"; 401 }; 402 403 lpspi1: spi@44360000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 407 reg = <0x44360000 0x10000>; 408 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 410 <&clk IMX93_CLK_BUS_AON>; 411 clock-names = "per", "ipg"; 412 dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; 413 dma-names = "tx", "rx"; 414 status = "disabled"; 415 }; 416 417 lpspi2: spi@44370000 { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 421 reg = <0x44370000 0x10000>; 422 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 424 <&clk IMX93_CLK_BUS_AON>; 425 clock-names = "per", "ipg"; 426 dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; 427 dma-names = "tx", "rx"; 428 status = "disabled"; 429 }; 430 431 lpuart1: serial@44380000 { 432 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 433 reg = <0x44380000 0x1000>; 434 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 436 clock-names = "ipg"; 437 dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; 438 dma-names = "rx", "tx"; 439 status = "disabled"; 440 }; 441 442 lpuart2: serial@44390000 { 443 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 444 reg = <0x44390000 0x1000>; 445 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 447 clock-names = "ipg"; 448 dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 flexcan1: can@443a0000 { 454 compatible = "fsl,imx93-flexcan"; 455 reg = <0x443a0000 0x10000>; 456 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clk IMX93_CLK_BUS_AON>, 458 <&clk IMX93_CLK_CAN1_GATE>; 459 clock-names = "ipg", "per"; 460 assigned-clocks = <&clk IMX93_CLK_CAN1>; 461 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 462 assigned-clock-rates = <40000000>; 463 fsl,clk-source = /bits/ 8 <0>; 464 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; 465 status = "disabled"; 466 }; 467 468 sai1: sai@443b0000 { 469 compatible = "fsl,imx93-sai"; 470 reg = <0x443b0000 0x10000>; 471 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 473 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 474 <&clk IMX93_CLK_DUMMY>; 475 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 476 dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; 477 dma-names = "rx", "tx"; 478 #sound-dai-cells = <0>; 479 status = "disabled"; 480 }; 481 482 iomuxc: pinctrl@443c0000 { 483 compatible = "fsl,imx93-iomuxc"; 484 reg = <0x443c0000 0x10000>; 485 status = "okay"; 486 }; 487 488 bbnsm: bbnsm@44440000 { 489 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 490 reg = <0x44440000 0x10000>; 491 492 bbnsm_rtc: rtc { 493 compatible = "nxp,imx93-bbnsm-rtc"; 494 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 495 }; 496 497 bbnsm_pwrkey: pwrkey { 498 compatible = "nxp,imx93-bbnsm-pwrkey"; 499 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 500 linux,code = <KEY_POWER>; 501 }; 502 }; 503 504 clk: clock-controller@44450000 { 505 compatible = "fsl,imx93-ccm"; 506 reg = <0x44450000 0x10000>; 507 #clock-cells = <1>; 508 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 509 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 510 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; 511 assigned-clock-rates = <393216000>; 512 status = "okay"; 513 }; 514 515 src: system-controller@44460000 { 516 compatible = "fsl,imx93-src", "syscon"; 517 reg = <0x44460000 0x10000>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 522 mlmix: power-domain@44461800 { 523 compatible = "fsl,imx93-src-slice"; 524 reg = <0x44461800 0x400>, <0x44464800 0x400>; 525 #power-domain-cells = <0>; 526 clocks = <&clk IMX93_CLK_ML_APB>, 527 <&clk IMX93_CLK_ML>; 528 }; 529 530 mediamix: power-domain@44462400 { 531 compatible = "fsl,imx93-src-slice"; 532 reg = <0x44462400 0x400>, <0x44465800 0x400>; 533 #power-domain-cells = <0>; 534 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, 535 <&clk IMX93_CLK_MEDIA_APB>; 536 }; 537 }; 538 539 clock-controller@44480000 { 540 compatible = "fsl,imx93-anatop"; 541 reg = <0x44480000 0x2000>; 542 #clock-cells = <1>; 543 }; 544 545 tmu: tmu@44482000 { 546 compatible = "fsl,qoriq-tmu"; 547 reg = <0x44482000 0x1000>; 548 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clk IMX93_CLK_TMC_GATE>; 550 little-endian; 551 fsl,tmu-range = <0x800000da 0x800000e9 552 0x80000102 0x8000012a 553 0x80000166 0x800001a7 554 0x800001b6>; 555 fsl,tmu-calibration = <0x00000000 0x0000000e 556 0x00000001 0x00000029 557 0x00000002 0x00000056 558 0x00000003 0x000000a2 559 0x00000004 0x00000116 560 0x00000005 0x00000195 561 0x00000006 0x000001b2>; 562 #thermal-sensor-cells = <1>; 563 }; 564 565 micfil: micfil@44520000 { 566 compatible = "fsl,imx93-micfil"; 567 reg = <0x44520000 0x10000>; 568 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clk IMX93_CLK_PDM_IPG>, 573 <&clk IMX93_CLK_PDM_GATE>, 574 <&clk IMX93_CLK_AUDIO_PLL>; 575 clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; 576 dmas = <&edma1 29 0 5>; 577 dma-names = "rx"; 578 #sound-dai-cells = <0>; 579 status = "disabled"; 580 }; 581 582 adc1: adc@44530000 { 583 compatible = "nxp,imx93-adc"; 584 reg = <0x44530000 0x10000>; 585 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX93_CLK_ADC1_GATE>; 589 clock-names = "ipg"; 590 #io-channel-cells = <1>; 591 status = "disabled"; 592 }; 593 }; 594 595 aips2: bus@42000000 { 596 compatible = "fsl,aips-bus", "simple-bus"; 597 reg = <0x42000000 0x800000>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges; 601 602 edma2: dma-controller@42000000 { 603 compatible = "fsl,imx93-edma4"; 604 reg = <0x42000000 0x210000>; 605 #dma-cells = <3>; 606 dma-channels = <64>; 607 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&clk IMX93_CLK_EDMA2_GATE>; 672 clock-names = "dma"; 673 }; 674 675 wakeupmix_gpr: syscon@42420000 { 676 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 677 reg = <0x42420000 0x1000>; 678 }; 679 680 mu2: mailbox@42440000 { 681 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 682 reg = <0x42440000 0x10000>; 683 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 685 #mbox-cells = <2>; 686 status = "disabled"; 687 }; 688 689 wdog3: watchdog@42490000 { 690 compatible = "fsl,imx93-wdt"; 691 reg = <0x42490000 0x10000>; 692 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&clk IMX93_CLK_WDOG3_GATE>; 694 timeout-sec = <40>; 695 status = "disabled"; 696 }; 697 698 wdog4: watchdog@424a0000 { 699 compatible = "fsl,imx93-wdt"; 700 reg = <0x424a0000 0x10000>; 701 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&clk IMX93_CLK_WDOG4_GATE>; 703 timeout-sec = <40>; 704 status = "disabled"; 705 }; 706 707 wdog5: watchdog@424b0000 { 708 compatible = "fsl,imx93-wdt"; 709 reg = <0x424b0000 0x10000>; 710 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clk IMX93_CLK_WDOG5_GATE>; 712 timeout-sec = <40>; 713 status = "disabled"; 714 }; 715 716 tpm3: pwm@424e0000 { 717 compatible = "fsl,imx7ulp-pwm"; 718 reg = <0x424e0000 0x1000>; 719 clocks = <&clk IMX93_CLK_TPM3_GATE>; 720 #pwm-cells = <3>; 721 status = "disabled"; 722 }; 723 724 tpm4: pwm@424f0000 { 725 compatible = "fsl,imx7ulp-pwm"; 726 reg = <0x424f0000 0x10000>; 727 clocks = <&clk IMX93_CLK_TPM4_GATE>; 728 #pwm-cells = <3>; 729 status = "disabled"; 730 }; 731 732 tpm5: pwm@42500000 { 733 compatible = "fsl,imx7ulp-pwm"; 734 reg = <0x42500000 0x10000>; 735 clocks = <&clk IMX93_CLK_TPM5_GATE>; 736 #pwm-cells = <3>; 737 status = "disabled"; 738 }; 739 740 tpm6: pwm@42510000 { 741 compatible = "fsl,imx7ulp-pwm"; 742 reg = <0x42510000 0x10000>; 743 clocks = <&clk IMX93_CLK_TPM6_GATE>; 744 #pwm-cells = <3>; 745 status = "disabled"; 746 }; 747 748 i3c2: i3c@42520000 { 749 compatible = "silvaco,i3c-master-v1"; 750 reg = <0x42520000 0x10000>; 751 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <3>; 753 #size-cells = <0>; 754 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 755 <&clk IMX93_CLK_I3C2_GATE>, 756 <&clk IMX93_CLK_I3C2_SLOW>; 757 clock-names = "pclk", "fast_clk", "slow_clk"; 758 status = "disabled"; 759 }; 760 761 lpi2c3: i2c@42530000 { 762 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 763 reg = <0x42530000 0x10000>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 768 <&clk IMX93_CLK_BUS_WAKEUP>; 769 clock-names = "per", "ipg"; 770 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 771 dma-names = "tx", "rx"; 772 status = "disabled"; 773 }; 774 775 lpi2c4: i2c@42540000 { 776 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 777 reg = <0x42540000 0x10000>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 782 <&clk IMX93_CLK_BUS_WAKEUP>; 783 clock-names = "per", "ipg"; 784 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 785 dma-names = "tx", "rx"; 786 status = "disabled"; 787 }; 788 789 lpspi3: spi@42550000 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 793 reg = <0x42550000 0x10000>; 794 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 796 <&clk IMX93_CLK_BUS_WAKEUP>; 797 clock-names = "per", "ipg"; 798 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 799 dma-names = "tx", "rx"; 800 status = "disabled"; 801 }; 802 803 lpspi4: spi@42560000 { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 807 reg = <0x42560000 0x10000>; 808 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 810 <&clk IMX93_CLK_BUS_WAKEUP>; 811 clock-names = "per", "ipg"; 812 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 813 dma-names = "tx", "rx"; 814 status = "disabled"; 815 }; 816 817 lpuart3: serial@42570000 { 818 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 819 reg = <0x42570000 0x1000>; 820 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 822 clock-names = "ipg"; 823 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 824 dma-names = "rx", "tx"; 825 status = "disabled"; 826 }; 827 828 lpuart4: serial@42580000 { 829 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 830 reg = <0x42580000 0x1000>; 831 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 833 clock-names = "ipg"; 834 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 835 dma-names = "rx", "tx"; 836 status = "disabled"; 837 }; 838 839 lpuart5: serial@42590000 { 840 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 841 reg = <0x42590000 0x1000>; 842 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 844 clock-names = "ipg"; 845 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 lpuart6: serial@425a0000 { 851 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 852 reg = <0x425a0000 0x1000>; 853 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 855 clock-names = "ipg"; 856 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 857 dma-names = "rx", "tx"; 858 status = "disabled"; 859 }; 860 861 flexcan2: can@425b0000 { 862 compatible = "fsl,imx93-flexcan"; 863 reg = <0x425b0000 0x10000>; 864 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 866 <&clk IMX93_CLK_CAN2_GATE>; 867 clock-names = "ipg", "per"; 868 assigned-clocks = <&clk IMX93_CLK_CAN2>; 869 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 870 assigned-clock-rates = <40000000>; 871 fsl,clk-source = /bits/ 8 <0>; 872 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; 873 status = "disabled"; 874 }; 875 876 flexspi1: spi@425e0000 { 877 compatible = "nxp,imx8mm-fspi"; 878 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 879 reg-names = "fspi_base", "fspi_mmap"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 884 <&clk IMX93_CLK_FLEXSPI1_GATE>; 885 clock-names = "fspi_en", "fspi"; 886 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 887 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 888 status = "disabled"; 889 }; 890 891 sai2: sai@42650000 { 892 compatible = "fsl,imx93-sai"; 893 reg = <0x42650000 0x10000>; 894 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, 896 <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, 897 <&clk IMX93_CLK_DUMMY>; 898 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 899 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 900 dma-names = "rx", "tx"; 901 #sound-dai-cells = <0>; 902 status = "disabled"; 903 }; 904 905 sai3: sai@42660000 { 906 compatible = "fsl,imx93-sai"; 907 reg = <0x42660000 0x10000>; 908 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, 910 <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, 911 <&clk IMX93_CLK_DUMMY>; 912 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 913 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 914 dma-names = "rx", "tx"; 915 #sound-dai-cells = <0>; 916 status = "disabled"; 917 }; 918 919 xcvr: xcvr@42680000 { 920 compatible = "fsl,imx93-xcvr"; 921 reg = <0x42680000 0x800>, 922 <0x42680800 0x400>, 923 <0x42680c00 0x080>, 924 <0x42680e00 0x080>; 925 reg-names = "ram", "regs", "rxfifo", "txfifo"; 926 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 929 <&clk IMX93_CLK_SPDIF_GATE>, 930 <&clk IMX93_CLK_DUMMY>, 931 <&clk IMX93_CLK_AUD_XCVR_GATE>; 932 clock-names = "ipg", "phy", "spba", "pll_ipg"; 933 dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; 934 dma-names = "rx", "tx"; 935 #sound-dai-cells = <0>; 936 status = "disabled"; 937 }; 938 939 lpuart7: serial@42690000 { 940 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 941 reg = <0x42690000 0x1000>; 942 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 944 clock-names = "ipg"; 945 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 946 dma-names = "rx", "tx"; 947 status = "disabled"; 948 }; 949 950 lpuart8: serial@426a0000 { 951 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 952 reg = <0x426a0000 0x1000>; 953 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 955 clock-names = "ipg"; 956 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 957 dma-names = "rx", "tx"; 958 status = "disabled"; 959 }; 960 961 lpi2c5: i2c@426b0000 { 962 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 963 reg = <0x426b0000 0x10000>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 968 <&clk IMX93_CLK_BUS_WAKEUP>; 969 clock-names = "per", "ipg"; 970 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 lpi2c6: i2c@426c0000 { 976 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 977 reg = <0x426c0000 0x10000>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 982 <&clk IMX93_CLK_BUS_WAKEUP>; 983 clock-names = "per", "ipg"; 984 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 lpi2c7: i2c@426d0000 { 990 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 991 reg = <0x426d0000 0x10000>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 996 <&clk IMX93_CLK_BUS_WAKEUP>; 997 clock-names = "per", "ipg"; 998 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 999 dma-names = "tx", "rx"; 1000 status = "disabled"; 1001 }; 1002 1003 lpi2c8: i2c@426e0000 { 1004 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 1005 reg = <0x426e0000 0x10000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 1010 <&clk IMX93_CLK_BUS_WAKEUP>; 1011 clock-names = "per", "ipg"; 1012 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 lpspi5: spi@426f0000 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1021 reg = <0x426f0000 0x10000>; 1022 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 1024 <&clk IMX93_CLK_BUS_WAKEUP>; 1025 clock-names = "per", "ipg"; 1026 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 1027 dma-names = "tx", "rx"; 1028 status = "disabled"; 1029 }; 1030 1031 lpspi6: spi@42700000 { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1035 reg = <0x42700000 0x10000>; 1036 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 1038 <&clk IMX93_CLK_BUS_WAKEUP>; 1039 clock-names = "per", "ipg"; 1040 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1041 dma-names = "tx", "rx"; 1042 status = "disabled"; 1043 }; 1044 1045 lpspi7: spi@42710000 { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1049 reg = <0x42710000 0x10000>; 1050 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 1052 <&clk IMX93_CLK_BUS_WAKEUP>; 1053 clock-names = "per", "ipg"; 1054 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1055 dma-names = "tx", "rx"; 1056 status = "disabled"; 1057 }; 1058 1059 lpspi8: spi@42720000 { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 1063 reg = <0x42720000 0x10000>; 1064 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 1066 <&clk IMX93_CLK_BUS_WAKEUP>; 1067 clock-names = "per", "ipg"; 1068 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1069 dma-names = "tx", "rx"; 1070 status = "disabled"; 1071 }; 1072 1073 }; 1074 1075 aips3: bus@42800000 { 1076 compatible = "fsl,aips-bus", "simple-bus"; 1077 reg = <0x42800000 0x800000>; 1078 #address-cells = <1>; 1079 #size-cells = <1>; 1080 ranges; 1081 1082 usdhc1: mmc@42850000 { 1083 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1084 reg = <0x42850000 0x10000>; 1085 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1087 <&clk IMX93_CLK_WAKEUP_AXI>, 1088 <&clk IMX93_CLK_USDHC1_GATE>; 1089 clock-names = "ipg", "ahb", "per"; 1090 assigned-clocks = <&clk IMX93_CLK_USDHC1>; 1091 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1092 assigned-clock-rates = <400000000>; 1093 bus-width = <8>; 1094 fsl,tuning-start-tap = <1>; 1095 fsl,tuning-step = <2>; 1096 status = "disabled"; 1097 }; 1098 1099 usdhc2: mmc@42860000 { 1100 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1101 reg = <0x42860000 0x10000>; 1102 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1104 <&clk IMX93_CLK_WAKEUP_AXI>, 1105 <&clk IMX93_CLK_USDHC2_GATE>; 1106 clock-names = "ipg", "ahb", "per"; 1107 assigned-clocks = <&clk IMX93_CLK_USDHC2>; 1108 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1109 assigned-clock-rates = <400000000>; 1110 bus-width = <4>; 1111 fsl,tuning-start-tap = <1>; 1112 fsl,tuning-step = <2>; 1113 status = "disabled"; 1114 }; 1115 1116 fec: ethernet@42890000 { 1117 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1118 reg = <0x42890000 0x10000>; 1119 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&clk IMX93_CLK_ENET1_GATE>, 1124 <&clk IMX93_CLK_ENET1_GATE>, 1125 <&clk IMX93_CLK_ENET_TIMER1>, 1126 <&clk IMX93_CLK_ENET_REF>, 1127 <&clk IMX93_CLK_ENET_REF_PHY>; 1128 clock-names = "ipg", "ahb", "ptp", 1129 "enet_clk_ref", "enet_out"; 1130 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 1131 <&clk IMX93_CLK_ENET_REF>, 1132 <&clk IMX93_CLK_ENET_REF_PHY>; 1133 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1134 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 1135 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1136 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 1137 fsl,num-tx-queues = <3>; 1138 fsl,num-rx-queues = <3>; 1139 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; 1140 nvmem-cells = <ð_mac1>; 1141 nvmem-cell-names = "mac-address"; 1142 status = "disabled"; 1143 }; 1144 1145 eqos: ethernet@428a0000 { 1146 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 1147 reg = <0x428a0000 0x10000>; 1148 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1150 interrupt-names = "macirq", "eth_wake_irq"; 1151 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 1152 <&clk IMX93_CLK_ENET_QOS_GATE>, 1153 <&clk IMX93_CLK_ENET_TIMER2>, 1154 <&clk IMX93_CLK_ENET>, 1155 <&clk IMX93_CLK_ENET_QOS_GATE>; 1156 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 1157 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 1158 <&clk IMX93_CLK_ENET>; 1159 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 1160 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 1161 assigned-clock-rates = <100000000>, <250000000>; 1162 intf_mode = <&wakeupmix_gpr 0x28>; 1163 snps,clk-csr = <6>; 1164 nvmem-cells = <ð_mac2>; 1165 nvmem-cell-names = "mac-address"; 1166 status = "disabled"; 1167 }; 1168 1169 usdhc3: mmc@428b0000 { 1170 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1171 reg = <0x428b0000 0x10000>; 1172 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1174 <&clk IMX93_CLK_WAKEUP_AXI>, 1175 <&clk IMX93_CLK_USDHC3_GATE>; 1176 clock-names = "ipg", "ahb", "per"; 1177 assigned-clocks = <&clk IMX93_CLK_USDHC3>; 1178 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1179 assigned-clock-rates = <400000000>; 1180 bus-width = <4>; 1181 fsl,tuning-start-tap = <1>; 1182 fsl,tuning-step = <2>; 1183 status = "disabled"; 1184 }; 1185 }; 1186 1187 gpio2: gpio@43810000 { 1188 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1189 reg = <0x43810000 0x1000>; 1190 gpio-controller; 1191 #gpio-cells = <2>; 1192 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1194 interrupt-controller; 1195 #interrupt-cells = <2>; 1196 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 1197 <&clk IMX93_CLK_GPIO2_GATE>; 1198 clock-names = "gpio", "port"; 1199 gpio-ranges = <&iomuxc 0 4 30>; 1200 }; 1201 1202 gpio3: gpio@43820000 { 1203 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1204 reg = <0x43820000 0x1000>; 1205 gpio-controller; 1206 #gpio-cells = <2>; 1207 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1209 interrupt-controller; 1210 #interrupt-cells = <2>; 1211 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 1212 <&clk IMX93_CLK_GPIO3_GATE>; 1213 clock-names = "gpio", "port"; 1214 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 1215 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 1216 }; 1217 1218 gpio4: gpio@43830000 { 1219 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1220 reg = <0x43830000 0x1000>; 1221 gpio-controller; 1222 #gpio-cells = <2>; 1223 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1225 interrupt-controller; 1226 #interrupt-cells = <2>; 1227 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 1228 <&clk IMX93_CLK_GPIO4_GATE>; 1229 clock-names = "gpio", "port"; 1230 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 1231 }; 1232 1233 gpio1: gpio@47400000 { 1234 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1235 reg = <0x47400000 0x1000>; 1236 gpio-controller; 1237 #gpio-cells = <2>; 1238 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1240 interrupt-controller; 1241 #interrupt-cells = <2>; 1242 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 1243 <&clk IMX93_CLK_GPIO1_GATE>; 1244 clock-names = "gpio", "port"; 1245 gpio-ranges = <&iomuxc 0 92 16>; 1246 }; 1247 1248 ocotp: efuse@47510000 { 1249 compatible = "fsl,imx93-ocotp", "syscon"; 1250 reg = <0x47510000 0x10000>; 1251 #address-cells = <1>; 1252 #size-cells = <1>; 1253 1254 eth_mac1: mac-address@4ec { 1255 reg = <0x4ec 0x6>; 1256 }; 1257 1258 eth_mac2: mac-address@4f2 { 1259 reg = <0x4f2 0x6>; 1260 }; 1261 1262 }; 1263 1264 s4muap: mailbox@47520000 { 1265 compatible = "fsl,imx93-mu-s4"; 1266 reg = <0x47520000 0x10000>; 1267 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-names = "tx", "rx"; 1270 #mbox-cells = <2>; 1271 }; 1272 1273 media_blk_ctrl: system-controller@4ac10000 { 1274 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 1275 reg = <0x4ac10000 0x10000>; 1276 power-domains = <&mediamix>; 1277 clocks = <&clk IMX93_CLK_MEDIA_APB>, 1278 <&clk IMX93_CLK_MEDIA_AXI>, 1279 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 1280 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 1281 <&clk IMX93_CLK_CAM_PIX>, 1282 <&clk IMX93_CLK_PXP_GATE>, 1283 <&clk IMX93_CLK_LCDIF_GATE>, 1284 <&clk IMX93_CLK_ISI_GATE>, 1285 <&clk IMX93_CLK_MIPI_CSI_GATE>, 1286 <&clk IMX93_CLK_MIPI_DSI_GATE>; 1287 clock-names = "apb", "axi", "nic", "disp", "cam", 1288 "pxp", "lcdif", "isi", "csi", "dsi"; 1289 #power-domain-cells = <1>; 1290 status = "disabled"; 1291 }; 1292 1293 usbotg1: usb@4c100000 { 1294 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1295 reg = <0x4c100000 0x200>; 1296 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1298 <&clk IMX93_CLK_HSIO_32K_GATE>; 1299 clock-names = "usb_ctrl_root", "usb_wakeup"; 1300 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1301 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1302 assigned-clock-rates = <133000000>; 1303 phys = <&usbphynop1>; 1304 fsl,usbmisc = <&usbmisc1 0>; 1305 status = "disabled"; 1306 }; 1307 1308 usbmisc1: usbmisc@4c100200 { 1309 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1310 "fsl,imx6q-usbmisc"; 1311 reg = <0x4c100200 0x200>; 1312 #index-cells = <1>; 1313 }; 1314 1315 usbotg2: usb@4c200000 { 1316 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1317 reg = <0x4c200000 0x200>; 1318 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1320 <&clk IMX93_CLK_HSIO_32K_GATE>; 1321 clock-names = "usb_ctrl_root", "usb_wakeup"; 1322 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1323 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1324 assigned-clock-rates = <133000000>; 1325 phys = <&usbphynop2>; 1326 fsl,usbmisc = <&usbmisc2 0>; 1327 status = "disabled"; 1328 }; 1329 1330 usbmisc2: usbmisc@4c200200 { 1331 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1332 "fsl,imx6q-usbmisc"; 1333 reg = <0x4c200200 0x200>; 1334 #index-cells = <1>; 1335 }; 1336 1337 ddr-pmu@4e300dc0 { 1338 compatible = "fsl,imx93-ddr-pmu"; 1339 reg = <0x4e300dc0 0x200>; 1340 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1341 }; 1342 }; 1343}; 1344