1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 * Copyright 2023 Variscite Ltd. 5 */ 6 7/dts-v1/; 8 9#include "imx93.dtsi" 10 11/{ 12 model = "Variscite VAR-SOM-MX93 module"; 13 compatible = "variscite,var-som-mx93", "fsl,imx93"; 14 15 mmc_pwrseq: mmc-pwrseq { 16 compatible = "mmc-pwrseq-simple"; 17 post-power-on-delay-ms = <100>; 18 power-off-delay-us = <10000>; 19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 20 <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 21 }; 22}; 23 24&eqos { 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_eqos>; 27 /* 28 * The required RGMII TX and RX 2ns delays are implemented directly 29 * in hardware via passive delay elements on the SOM PCB. 30 * No delay configuration is needed in software via PHY driver. 31 */ 32 phy-mode = "rgmii"; 33 phy-handle = <ðphy0>; 34 snps,clk-csr = <5>; 35 status = "okay"; 36 37 mdio { 38 compatible = "snps,dwmac-mdio"; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 clock-frequency = <1000000>; 42 43 ethphy0: ethernet-phy@0 { 44 compatible = "ethernet-phy-ieee802.3-c22"; 45 reg = <0>; 46 eee-broken-1000t; 47 reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 48 reset-assert-us = <10000>; 49 reset-deassert-us = <100000>; 50 51 leds { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 led@0 { 56 reg = <0>; 57 color = <LED_COLOR_ID_YELLOW>; 58 function = LED_FUNCTION_LAN; 59 linux,default-trigger = "netdev"; 60 }; 61 62 led@1 { 63 reg = <1>; 64 color = <LED_COLOR_ID_GREEN>; 65 function = LED_FUNCTION_LAN; 66 linux,default-trigger = "netdev"; 67 }; 68 }; 69 }; 70 }; 71}; 72 73/* eMMC */ 74&usdhc1 { 75 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 76 pinctrl-0 = <&pinctrl_usdhc1>; 77 pinctrl-1 = <&pinctrl_usdhc1>; 78 pinctrl-2 = <&pinctrl_usdhc1>; 79 bus-width = <8>; 80 non-removable; 81 status = "okay"; 82}; 83 84&iomuxc { 85 pinctrl_eqos: eqosgrp { 86 fsl,pins = < 87 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 88 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 89 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 90 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 91 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 92 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 93 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 94 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 95 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 96 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 97 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 98 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 99 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 100 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 101 MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e 102 >; 103 }; 104 105 pinctrl_reg_eqos_phy: regeqosgrp { 106 fsl,pins = < 107 MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e 108 >; 109 }; 110 111 pinctrl_usdhc1: usdhc1grp { 112 fsl,pins = < 113 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 114 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 115 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 116 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 117 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 118 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 119 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 120 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 121 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 122 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 123 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 124 >; 125 }; 126}; 127