1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 * Copyright 2023 Variscite Ltd. 5 */ 6 7/dts-v1/; 8 9#include "imx93.dtsi" 10 11/{ 12 model = "Variscite VAR-SOM-MX93 module"; 13 compatible = "variscite,var-som-mx93", "fsl,imx93"; 14 15 mmc_pwrseq: mmc-pwrseq { 16 compatible = "mmc-pwrseq-simple"; 17 post-power-on-delay-ms = <100>; 18 power-off-delay-us = <10000>; 19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 20 <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 21 }; 22 23 reg_eqos_phy: regulator-eqos-phy { 24 compatible = "regulator-fixed"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_reg_eqos_phy>; 27 regulator-name = "eth_phy_pwr"; 28 regulator-min-microvolt = <3300000>; 29 regulator-max-microvolt = <3300000>; 30 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 31 enable-active-high; 32 startup-delay-us = <100000>; 33 regulator-always-on; 34 }; 35}; 36 37&eqos { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_eqos>; 40 phy-mode = "rgmii"; 41 phy-handle = <ðphy0>; 42 status = "okay"; 43 44 mdio { 45 compatible = "snps,dwmac-mdio"; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 clock-frequency = <1000000>; 49 50 ethphy0: ethernet-phy@0 { 51 compatible = "ethernet-phy-ieee802.3-c22"; 52 reg = <0>; 53 eee-broken-1000t; 54 }; 55 }; 56}; 57 58/* eMMC */ 59&usdhc1 { 60 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 61 pinctrl-0 = <&pinctrl_usdhc1>; 62 pinctrl-1 = <&pinctrl_usdhc1>; 63 pinctrl-2 = <&pinctrl_usdhc1>; 64 bus-width = <8>; 65 non-removable; 66 status = "okay"; 67}; 68 69&iomuxc { 70 pinctrl_eqos: eqosgrp { 71 fsl,pins = < 72 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 73 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 74 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 75 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 76 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 77 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 78 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 79 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 80 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 81 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 82 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 83 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 84 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 85 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 86 >; 87 }; 88 89 pinctrl_reg_eqos_phy: regeqosgrp { 90 fsl,pins = < 91 MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e 92 >; 93 }; 94 95 pinctrl_usdhc1: usdhc1grp { 96 fsl,pins = < 97 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 98 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 99 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 100 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 101 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 102 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 103 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 104 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 105 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 106 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 107 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 108 >; 109 }; 110}; 111