1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 * Copyright 2023 Variscite Ltd. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include "imx93-var-som.dtsi" 11 12/{ 13 model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; 14 compatible = "variscite,var-som-mx93-symphony", 15 "variscite,var-som-mx93", "fsl,imx93"; 16 17 aliases { 18 ethernet0 = &eqos; 19 ethernet1 = &fec; 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 i2c0 = &lpi2c1; 24 i2c1 = &lpi2c2; 25 i2c2 = &lpi2c3; 26 i2c3 = &lpi2c4; 27 i2c4 = &lpi2c5; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 serial0 = &lpuart1; 31 serial1 = &lpuart2; 32 serial2 = &lpuart3; 33 serial3 = &lpuart4; 34 serial4 = &lpuart5; 35 serial5 = &lpuart6; 36 }; 37 38 39 chosen { 40 stdout-path = &lpuart1; 41 }; 42 43 /* 44 * Needed only for Symphony <= v1.5 45 */ 46 reg_fec_phy: regulator-fec-phy { 47 compatible = "regulator-fixed"; 48 regulator-name = "fec-phy"; 49 regulator-min-microvolt = <1800000>; 50 regulator-max-microvolt = <1800000>; 51 regulator-enable-ramp-delay = <20000>; 52 gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; 53 enable-active-high; 54 regulator-always-on; 55 }; 56 57 reg_usdhc2_vmmc: regulator-usdhc2 { 58 compatible = "regulator-fixed"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 61 regulator-name = "VSD_3V3"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; 65 off-on-delay-us = <20000>; 66 enable-active-high; 67 }; 68 69 reg_vref_1v8: regulator-adc-vref { 70 compatible = "regulator-fixed"; 71 regulator-name = "vref_1v8"; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <1800000>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 ethosu_mem: ethosu-region@88000000 { 82 compatible = "shared-dma-pool"; 83 reusable; 84 reg = <0x0 0x88000000 0x0 0x8000000>; 85 }; 86 87 vdev0vring0: vdev0vring0@87ee0000 { 88 reg = <0 0x87ee0000 0 0x8000>; 89 no-map; 90 }; 91 92 vdev0vring1: vdev0vring1@87ee8000 { 93 reg = <0 0x87ee8000 0 0x8000>; 94 no-map; 95 }; 96 97 vdev1vring0: vdev1vring0@87ef0000 { 98 reg = <0 0x87ef0000 0 0x8000>; 99 no-map; 100 }; 101 102 vdev1vring1: vdev1vring1@87ef8000 { 103 reg = <0 0x87ef8000 0 0x8000>; 104 no-map; 105 }; 106 107 rsc_table: rsc-table@2021f000 { 108 reg = <0 0x2021f000 0 0x1000>; 109 no-map; 110 }; 111 112 vdevbuffer: vdevbuffer@87f00000 { 113 compatible = "shared-dma-pool"; 114 reg = <0 0x87f00000 0 0x100000>; 115 no-map; 116 }; 117 118 ele_reserved: ele-reserved@87de0000 { 119 compatible = "shared-dma-pool"; 120 reg = <0 0x87de0000 0 0x100000>; 121 no-map; 122 }; 123 }; 124 125 gpio-keys { 126 compatible = "gpio-keys"; 127 128 key-back { 129 label = "Back"; 130 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 131 linux,code = <KEY_BACK>; 132 }; 133 134 key-home { 135 label = "Home"; 136 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 137 linux,code = <KEY_HOME>; 138 }; 139 140 key-menu { 141 label = "Menu"; 142 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 143 linux,code = <KEY_MENU>; 144 }; 145 }; 146 147 leds { 148 compatible = "gpio-leds"; 149 150 led-0 { 151 function = LED_FUNCTION_STATUS; 152 color = <LED_COLOR_ID_GREEN>; 153 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 154 linux,default-trigger = "heartbeat"; 155 }; 156 }; 157}; 158 159/* Use external instead of internal RTC*/ 160&bbnsm_rtc { 161 status = "disabled"; 162}; 163 164&eqos { 165 mdio { 166 ethphy1: ethernet-phy@5 { 167 compatible = "ethernet-phy-ieee802.3-c22"; 168 reg = <5>; 169 qca,disable-smarteee; 170 eee-broken-1000t; 171 reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; 172 reset-assert-us = <10000>; 173 reset-deassert-us = <20000>; 174 vddio-supply = <&vddio1>; 175 176 vddio1: vddio-regulator { 177 regulator-min-microvolt = <1800000>; 178 regulator-max-microvolt = <1800000>; 179 }; 180 }; 181 }; 182}; 183 184&fec { 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_fec>; 187 phy-mode = "rgmii"; 188 phy-handle = <ðphy1>; 189 phy-supply = <®_fec_phy>; 190 status = "okay"; 191}; 192 193&flexcan1 { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_flexcan1>; 196 status = "okay"; 197}; 198 199&lpi2c1 { 200 clock-frequency = <400000>; 201 pinctrl-names = "default", "sleep", "gpio"; 202 pinctrl-0 = <&pinctrl_lpi2c1>; 203 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 204 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 205 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 206 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 207 status = "okay"; 208 209 /* DS1337 RTC module */ 210 rtc@68 { 211 compatible = "dallas,ds1337"; 212 reg = <0x68>; 213 }; 214}; 215 216&lpi2c5 { 217 clock-frequency = <400000>; 218 pinctrl-names = "default", "sleep", "gpio"; 219 pinctrl-0 = <&pinctrl_lpi2c5>; 220 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 221 pinctrl-2 = <&pinctrl_lpi2c5_gpio>; 222 scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; 223 sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; 224 status = "okay"; 225 226 pca9534: gpio@20 { 227 compatible = "nxp,pca9534"; 228 reg = <0x20>; 229 gpio-controller; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_pca9534>; 232 interrupt-parent = <&gpio3>; 233 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 234 #gpio-cells = <2>; 235 wakeup-source; 236 }; 237}; 238 239/* Console */ 240&lpuart1 { 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_uart1>; 243 status = "okay"; 244}; 245 246/* J18.7, J18.9 */ 247&lpuart6 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_uart6>; 250 status = "okay"; 251}; 252 253/* SD */ 254&usdhc2 { 255 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 256 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 257 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 258 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 259 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 260 vmmc-supply = <®_usdhc2_vmmc>; 261 bus-width = <4>; 262 status = "okay"; 263 no-sdio; 264 no-mmc; 265}; 266 267/* Watchdog */ 268&wdog3 { 269 status = "okay"; 270}; 271 272&iomuxc { 273 pinctrl_fec: fecgrp { 274 fsl,pins = < 275 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 276 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 277 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 278 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 279 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 280 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 281 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 282 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 283 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 284 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 285 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 286 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 287 >; 288 }; 289 290 pinctrl_flexcan1: flexcan1grp { 291 fsl,pins = < 292 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 293 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 294 >; 295 }; 296 297 pinctrl_lpi2c1: lpi2c1grp { 298 fsl,pins = < 299 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 300 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 301 >; 302 }; 303 304 pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { 305 fsl,pins = < 306 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e 307 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e 308 >; 309 }; 310 311 pinctrl_lpi2c5: lpi2c5grp { 312 fsl,pins = < 313 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 314 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 315 >; 316 }; 317 318 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { 319 fsl,pins = < 320 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 321 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 322 >; 323 }; 324 325 pinctrl_pca9534: pca9534grp { 326 fsl,pins = < 327 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 328 >; 329 }; 330 331 pinctrl_uart1: uart1grp { 332 fsl,pins = < 333 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 334 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 335 >; 336 }; 337 338 pinctrl_uart6: uart6grp { 339 fsl,pins = < 340 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 341 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 342 >; 343 }; 344 345 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 346 fsl,pins = < 347 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e 348 >; 349 }; 350 351 pinctrl_usdhc2: usdhc2grp { 352 fsl,pins = < 353 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 354 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 355 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 356 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 357 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 358 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 359 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 360 >; 361 }; 362 363 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 364 fsl,pins = < 365 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 366 >; 367 }; 368}; 369