1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 * Copyright 2023 Variscite Ltd. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include "imx93-var-som.dtsi" 11 12/{ 13 model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; 14 compatible = "variscite,var-som-mx93-symphony", 15 "variscite,var-som-mx93", "fsl,imx93"; 16 17 aliases { 18 ethernet0 = &eqos; 19 ethernet1 = &fec; 20 }; 21 22 chosen { 23 stdout-path = &lpuart1; 24 }; 25 26 /* 27 * Needed only for Symphony <= v1.5 28 */ 29 reg_fec_phy: regulator-fec-phy { 30 compatible = "regulator-fixed"; 31 regulator-name = "fec-phy"; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <1800000>; 34 regulator-enable-ramp-delay = <20000>; 35 gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; 36 enable-active-high; 37 regulator-always-on; 38 }; 39 40 reg_usdhc2_vmmc: regulator-usdhc2 { 41 compatible = "regulator-fixed"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 44 regulator-name = "VSD_3V3"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; 48 off-on-delay-us = <20000>; 49 enable-active-high; 50 }; 51 52 reg_vref_1v8: regulator-adc-vref { 53 compatible = "regulator-fixed"; 54 regulator-name = "vref_1v8"; 55 regulator-min-microvolt = <1800000>; 56 regulator-max-microvolt = <1800000>; 57 }; 58 59 reserved-memory { 60 #address-cells = <2>; 61 #size-cells = <2>; 62 ranges; 63 64 ethosu_mem: ethosu-region@88000000 { 65 compatible = "shared-dma-pool"; 66 reusable; 67 reg = <0x0 0x88000000 0x0 0x8000000>; 68 }; 69 70 vdev0vring0: vdev0vring0@87ee0000 { 71 reg = <0 0x87ee0000 0 0x8000>; 72 no-map; 73 }; 74 75 vdev0vring1: vdev0vring1@87ee8000 { 76 reg = <0 0x87ee8000 0 0x8000>; 77 no-map; 78 }; 79 80 vdev1vring0: vdev1vring0@87ef0000 { 81 reg = <0 0x87ef0000 0 0x8000>; 82 no-map; 83 }; 84 85 vdev1vring1: vdev1vring1@87ef8000 { 86 reg = <0 0x87ef8000 0 0x8000>; 87 no-map; 88 }; 89 90 rsc_table: rsc-table@2021f000 { 91 reg = <0 0x2021f000 0 0x1000>; 92 no-map; 93 }; 94 95 vdevbuffer: vdevbuffer@87f00000 { 96 compatible = "shared-dma-pool"; 97 reg = <0 0x87f00000 0 0x100000>; 98 no-map; 99 }; 100 101 ele_reserved: ele-reserved@87de0000 { 102 compatible = "shared-dma-pool"; 103 reg = <0 0x87de0000 0 0x100000>; 104 no-map; 105 }; 106 }; 107 108 gpio-keys { 109 compatible = "gpio-keys"; 110 111 key-back { 112 label = "Back"; 113 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 114 linux,code = <KEY_BACK>; 115 }; 116 117 key-home { 118 label = "Home"; 119 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 120 linux,code = <KEY_HOME>; 121 }; 122 123 key-menu { 124 label = "Menu"; 125 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 126 linux,code = <KEY_MENU>; 127 }; 128 }; 129 130 leds { 131 compatible = "gpio-leds"; 132 133 led-0 { 134 function = LED_FUNCTION_STATUS; 135 color = <LED_COLOR_ID_GREEN>; 136 gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; 137 linux,default-trigger = "heartbeat"; 138 }; 139 }; 140}; 141 142/* Use external instead of internal RTC*/ 143&bbnsm_rtc { 144 status = "disabled"; 145}; 146 147&eqos { 148 mdio { 149 ethphy1: ethernet-phy@5 { 150 compatible = "ethernet-phy-ieee802.3-c22"; 151 reg = <5>; 152 qca,disable-smarteee; 153 eee-broken-1000t; 154 reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; 155 reset-assert-us = <10000>; 156 reset-deassert-us = <20000>; 157 vddio-supply = <&vddio1>; 158 159 vddio1: vddio-regulator { 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 }; 164 }; 165}; 166 167&fec { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_fec>; 170 phy-mode = "rgmii"; 171 phy-handle = <ðphy1>; 172 phy-supply = <®_fec_phy>; 173 status = "okay"; 174}; 175 176&flexcan1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_flexcan1>; 179 status = "okay"; 180}; 181 182&lpi2c1 { 183 clock-frequency = <400000>; 184 pinctrl-names = "default", "sleep", "gpio"; 185 pinctrl-0 = <&pinctrl_lpi2c1>; 186 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 187 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 188 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 189 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 190 status = "okay"; 191 192 /* DS1337 RTC module */ 193 rtc@68 { 194 compatible = "dallas,ds1337"; 195 reg = <0x68>; 196 }; 197}; 198 199&lpi2c5 { 200 clock-frequency = <400000>; 201 pinctrl-names = "default", "sleep", "gpio"; 202 pinctrl-0 = <&pinctrl_lpi2c5>; 203 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 204 pinctrl-2 = <&pinctrl_lpi2c5_gpio>; 205 scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; 206 sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; 207 status = "okay"; 208 209 pca9534: gpio@20 { 210 compatible = "nxp,pca9534"; 211 reg = <0x20>; 212 gpio-controller; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_pca9534>; 215 interrupt-parent = <&gpio3>; 216 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 217 #gpio-cells = <2>; 218 wakeup-source; 219 }; 220}; 221 222/* Console */ 223&lpuart1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_uart1>; 226 status = "okay"; 227}; 228 229/* J18.7, J18.9 */ 230&lpuart6 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_uart6>; 233 status = "okay"; 234}; 235 236/* SD */ 237&usdhc2 { 238 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 239 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 240 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 241 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 242 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 243 vmmc-supply = <®_usdhc2_vmmc>; 244 bus-width = <4>; 245 status = "okay"; 246 no-sdio; 247 no-mmc; 248}; 249 250/* Watchdog */ 251&wdog3 { 252 status = "okay"; 253}; 254 255&iomuxc { 256 pinctrl_fec: fecgrp { 257 fsl,pins = < 258 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 259 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 260 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 261 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 262 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 263 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 264 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 265 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 266 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 267 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 268 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 269 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 270 >; 271 }; 272 273 pinctrl_flexcan1: flexcan1grp { 274 fsl,pins = < 275 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 276 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 277 >; 278 }; 279 280 pinctrl_lpi2c1: lpi2c1grp { 281 fsl,pins = < 282 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 283 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 284 >; 285 }; 286 287 pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { 288 fsl,pins = < 289 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e 290 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e 291 >; 292 }; 293 294 pinctrl_lpi2c5: lpi2c5grp { 295 fsl,pins = < 296 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 297 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 298 >; 299 }; 300 301 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { 302 fsl,pins = < 303 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 304 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 305 >; 306 }; 307 308 pinctrl_pca9534: pca9534grp { 309 fsl,pins = < 310 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 311 >; 312 }; 313 314 pinctrl_uart1: uart1grp { 315 fsl,pins = < 316 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 317 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 318 >; 319 }; 320 321 pinctrl_uart6: uart6grp { 322 fsl,pins = < 323 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 324 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 325 >; 326 }; 327 328 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 329 fsl,pins = < 330 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e 331 >; 332 }; 333 334 pinctrl_usdhc2: usdhc2grp { 335 fsl,pins = < 336 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 337 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 338 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 339 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 340 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 341 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 342 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 343 >; 344 }; 345 346 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 347 fsl,pins = < 348 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 349 >; 350 }; 351}; 352