1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 */ 7 8#include "imx93.dtsi" 9 10/{ 11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; 12 compatible = "tq,imx93-tqma9352", "fsl,imx93"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 /* our minimum RAM config will be 1024 MiB */ 17 reg = <0x00000000 0x80000000 0 0x40000000>; 18 }; 19 20 reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 linux,cma { 26 compatible = "shared-dma-pool"; 27 reusable; 28 alloc-ranges = <0 0x80000000 0 0x40000000>; 29 size = <0 0x10000000>; 30 linux,cma-default; 31 }; 32 }; 33 34 /* SD2 RST# via PMIC SW_EN */ 35 reg_usdhc2_vmmc: regulator-usdhc2 { 36 compatible = "regulator-fixed"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 39 regulator-name = "VSD_3V3"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&buck4>; 43 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46}; 47 48&adc1 { 49 vref-supply = <&buck5>; 50}; 51 52&flexspi1 { 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_flexspi1>; 55 status = "okay"; 56 57 flash0: flash@0 { 58 compatible = "jedec,spi-nor"; 59 reg = <0>; 60 /* 61 * no DQS, RXCLKSRC internal loop back, max 66 MHz 62 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST 63 * selected value together with root from 64 * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to 65 * respect the maximum value. 66 */ 67 spi-max-frequency = <62000000>; 68 spi-tx-bus-width = <4>; 69 spi-rx-bus-width = <4>; 70 71 partitions { 72 compatible = "fixed-partitions"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 }; 76 }; 77}; 78 79&lpi2c1 { 80 clock-frequency = <400000>; 81 pinctrl-names = "default", "sleep"; 82 pinctrl-0 = <&pinctrl_lpi2c1>; 83 pinctrl-1 = <&pinctrl_lpi2c1>; 84 status = "okay"; 85 86 se97_som: temperature-sensor@1b { 87 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 88 reg = <0x1b>; 89 }; 90 91 pca9451a: pmic@25 { 92 compatible = "nxp,pca9451a"; 93 reg = <0x25>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_pca9451>; 96 interrupt-parent = <&gpio1>; 97 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 98 99 regulators { 100 /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ 101 buck1: BUCK1 { 102 regulator-name = "BUCK1"; 103 regulator-min-microvolt = <750000>; 104 regulator-max-microvolt = <900000>; 105 regulator-boot-on; 106 regulator-always-on; 107 regulator-ramp-delay = <3125>; 108 }; 109 110 /* V_DDRQ - 0.6 V for LPDDR4X */ 111 buck2: BUCK2 { 112 regulator-name = "BUCK2"; 113 regulator-min-microvolt = <600000>; 114 regulator-max-microvolt = <600000>; 115 regulator-boot-on; 116 regulator-always-on; 117 regulator-ramp-delay = <3125>; 118 }; 119 120 /* V_3V3 - EEPROM, RTC, ... */ 121 buck4: BUCK4 { 122 regulator-name = "BUCK4"; 123 regulator-min-microvolt = <3300000>; 124 regulator-max-microvolt = <3300000>; 125 regulator-boot-on; 126 regulator-always-on; 127 }; 128 129 /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ 130 buck5: BUCK5 { 131 regulator-name = "BUCK5"; 132 regulator-min-microvolt = <1800000>; 133 regulator-max-microvolt = <1800000>; 134 regulator-boot-on; 135 regulator-always-on; 136 }; 137 138 /* V_1V1 - RAM VDD2*/ 139 buck6: BUCK6 { 140 regulator-name = "BUCK6"; 141 regulator-min-microvolt = <1100000>; 142 regulator-max-microvolt = <1100000>; 143 regulator-boot-on; 144 regulator-always-on; 145 }; 146 147 /* V_1V8_BBSM, fix 1.8 */ 148 ldo1: LDO1 { 149 regulator-name = "LDO1"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <1800000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 156 /* V_0V8_ANA */ 157 ldo4: LDO4 { 158 regulator-name = "LDO4"; 159 regulator-min-microvolt = <800000>; 160 regulator-max-microvolt = <800000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ 166 ldo5: LDO5 { 167 regulator-name = "LDO5"; 168 regulator-min-microvolt = <1800000>; 169 regulator-max-microvolt = <3300000>; 170 regulator-boot-on; 171 regulator-always-on; 172 }; 173 }; 174 }; 175 176 pcf85063: rtc@51 { 177 compatible = "nxp,pcf85063a"; 178 reg = <0x51>; 179 quartz-load-femtofarads = <7000>; 180 }; 181 182 eeprom0: eeprom@53 { 183 compatible = "nxp,se97b", "atmel,24c02"; 184 reg = <0x53>; 185 pagesize = <16>; 186 read-only; 187 vcc-supply = <&buck4>; 188 }; 189 190 eeprom1: eeprom@57 { 191 compatible = "atmel,24c64"; 192 reg = <0x57>; 193 pagesize = <32>; 194 vcc-supply = <&buck4>; 195 }; 196 197 /* protectable identification memory (part of M24C64-D @57) */ 198 eeprom@5f { 199 compatible = "atmel,24c64d-wl"; 200 reg = <0x5f>; 201 vcc-supply = <&buck4>; 202 }; 203 204 imu@6a { 205 compatible = "st,ism330dhcx"; 206 reg = <0x6a>; 207 vdd-supply = <&buck4>; 208 vddio-supply = <&buck4>; 209 }; 210}; 211 212&usdhc1 { 213 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 214 pinctrl-0 = <&pinctrl_usdhc1>; 215 pinctrl-1 = <&pinctrl_usdhc1>; 216 pinctrl-2 = <&pinctrl_usdhc1>; 217 vmmc-supply = <&buck4>; 218 vqmmc-supply = <&buck5>; 219 bus-width = <8>; 220 non-removable; 221 no-sdio; 222 no-sd; 223 status = "okay"; 224}; 225 226&wdog3 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_wdog>; 229 fsl,ext-reset-output; 230 status = "okay"; 231}; 232 233&iomuxc { 234 pinctrl_flexspi1: flexspi1grp { 235 fsl,pins = < 236 /* FSEL 3 | DSE X6 */ 237 MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe 238 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe 239 /* HYS | PU | FSEL 3 | DSE X6 */ 240 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x13fe 241 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x13fe 242 /* HYS | FSEL 3 | DSE X6 (external PU) */ 243 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x11fe 244 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x11fe 245 >; 246 }; 247 248 pinctrl_lpi2c1: lpi2c1grp { 249 fsl,pins = < 250 /* SION | OD | FSEL 3 | DSE X4 */ 251 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e 252 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e 253 >; 254 }; 255 256 pinctrl_pca9451: pca9451grp { 257 fsl,pins = < 258 /* HYS | PU */ 259 MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1200 260 >; 261 }; 262 263 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 264 fsl,pins = < 265 /* FSEL 2 | DSE X2 */ 266 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106 267 >; 268 }; 269 270 /* enable SION for data and cmd pad due to ERR052021 */ 271 pinctrl_usdhc1: usdhc1grp { 272 fsl,pins = < 273 /* PD | FSEL 3 | DSE X5 */ 274 MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be 275 /* HYS | FSEL 0 | no drive */ 276 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000 277 /* HYS | FSEL 3 | X5 */ 278 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be 279 /* HYS | FSEL 3 | X4 */ 280 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e 281 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e 282 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e 283 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e 284 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e 285 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e 286 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e 287 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e 288 >; 289 }; 290 291 pinctrl_wdog: wdoggrp { 292 fsl,pins = < 293 /* PU | FSEL 1 | DSE X4 */ 294 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 295 >; 296 }; 297}; 298